xref: /illumos-kvm/linux/include/asm-x86/kvm.h (revision 44f65dde)
1 #ifndef KVM_UNIFDEF_H
2 #define KVM_UNIFDEF_H
3 
4 #ifdef __i386__
5 #ifndef CONFIG_X86_32
6 #define CONFIG_X86_32 1
7 #endif
8 #endif
9 
10 #ifdef __x86_64__
11 #ifndef CONFIG_X86_64
12 #define CONFIG_X86_64 1
13 #endif
14 #endif
15 
16 #if defined(__i386__) || defined (__x86_64__)
17 #ifndef CONFIG_X86
18 #define CONFIG_X86 1
19 #endif
20 #endif
21 
22 #ifdef __ia64__
23 #ifndef CONFIG_IA64
24 #define CONFIG_IA64 1
25 #endif
26 #endif
27 
28 #ifdef __PPC__
29 #ifndef CONFIG_PPC
30 #define CONFIG_PPC 1
31 #endif
32 #endif
33 
34 #ifdef __s390__
35 #ifndef CONFIG_S390
36 #define CONFIG_S390 1
37 #endif
38 #endif
39 
40 #endif
41 #ifndef _ASM_X86_KVM_H
42 #define _ASM_X86_KVM_H
43 
44 /*
45  * KVM x86 specific structures and definitions
46  *
47  */
48 
49 #include <asm/types.h>
50 #include <linux/ioctl.h>
51 
52 /* Select x86 specific features in <linux/kvm.h> */
53 #define __KVM_HAVE_PIT
54 #define __KVM_HAVE_IOAPIC
55 #define __KVM_HAVE_DEVICE_ASSIGNMENT
56 #define __KVM_HAVE_MSI
57 #define __KVM_HAVE_USER_NMI
58 #define __KVM_HAVE_GUEST_DEBUG
59 #define __KVM_HAVE_MSIX
60 #define __KVM_HAVE_MCE
61 #define __KVM_HAVE_PIT_STATE2
62 #define __KVM_HAVE_XEN_HVM
63 #define __KVM_HAVE_VCPU_EVENTS
64 
65 /* Architectural interrupt line count. */
66 #define KVM_NR_INTERRUPTS 256
67 
68 struct kvm_memory_alias {
69 	__u32 slot;  /* this has a different namespace than memory slots */
70 	__u32 flags;
71 	__u64 guest_phys_addr;
72 	__u64 memory_size;
73 	__u64 target_phys_addr;
74 };
75 
76 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
77 struct kvm_pic_state {
78 	__u8 last_irr;	/* edge detection */
79 	__u8 irr;		/* interrupt request register */
80 	__u8 imr;		/* interrupt mask register */
81 	__u8 isr;		/* interrupt service register */
82 	__u8 priority_add;	/* highest irq priority */
83 	__u8 irq_base;
84 	__u8 read_reg_select;
85 	__u8 poll;
86 	__u8 special_mask;
87 	__u8 init_state;
88 	__u8 auto_eoi;
89 	__u8 rotate_on_auto_eoi;
90 	__u8 special_fully_nested_mode;
91 	__u8 init4;		/* true if 4 byte init */
92 	__u8 elcr;		/* PIIX edge/trigger selection */
93 	__u8 elcr_mask;
94 };
95 
96 #define KVM_IOAPIC_NUM_PINS  24
97 struct kvm_ioapic_state {
98 	__u64 base_address;
99 	__u32 ioregsel;
100 	__u32 id;
101 	__u32 irr;
102 	__u32 pad;
103 	union {
104 		__u64 bits;
105 		struct {
106 			__u8 vector;
107 			__u8 delivery_mode:3;
108 			__u8 dest_mode:1;
109 			__u8 delivery_status:1;
110 			__u8 polarity:1;
111 			__u8 remote_irr:1;
112 			__u8 trig_mode:1;
113 			__u8 mask:1;
114 			__u8 reserve:7;
115 			__u8 reserved[4];
116 			__u8 dest_id;
117 		} fields;
118 	} redirtbl[KVM_IOAPIC_NUM_PINS];
119 };
120 
121 #define KVM_IRQCHIP_PIC_MASTER   0
122 #define KVM_IRQCHIP_PIC_SLAVE    1
123 #define KVM_IRQCHIP_IOAPIC       2
124 #define KVM_NR_IRQCHIPS          3
125 
126 /* for KVM_GET_REGS and KVM_SET_REGS */
127 struct kvm_regs {
128 	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
129 	__u64 rax, rbx, rcx, rdx;
130 	__u64 rsi, rdi, rsp, rbp;
131 	__u64 r8,  r9,  r10, r11;
132 	__u64 r12, r13, r14, r15;
133 	__u64 rip, rflags;
134 };
135 
136 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */
137 #define KVM_APIC_REG_SIZE 0x400
138 struct kvm_lapic_state {
139 	char regs[KVM_APIC_REG_SIZE];
140 };
141 
142 struct kvm_segment {
143 	__u64 base;
144 	__u32 limit;
145 	__u16 selector;
146 	__u8  type;
147 	__u8  present, dpl, db, s, l, g, avl;
148 	__u8  unusable;
149 	__u8  padding;
150 };
151 
152 struct kvm_dtable {
153 	__u64 base;
154 	__u16 limit;
155 	__u16 padding[3];
156 };
157 
158 
159 /* for KVM_GET_SREGS and KVM_SET_SREGS */
160 struct kvm_sregs {
161 	/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
162 	struct kvm_segment cs, ds, es, fs, gs, ss;
163 	struct kvm_segment tr, ldt;
164 	struct kvm_dtable gdt, idt;
165 	__u64 cr0, cr2, cr3, cr4, cr8;
166 	__u64 efer;
167 	__u64 apic_base;
168 	__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
169 };
170 
171 /* for KVM_GET_FPU and KVM_SET_FPU */
172 struct kvm_fpu {
173 	__u8  fpr[8][16];
174 	__u16 fcw;
175 	__u16 fsw;
176 	__u8  ftwx;  /* in fxsave format */
177 	__u8  pad1;
178 	__u16 last_opcode;
179 	__u64 last_ip;
180 	__u64 last_dp;
181 	__u8  xmm[16][16];
182 	__u32 mxcsr;
183 	__u32 pad2;
184 };
185 
186 struct kvm_msr_entry {
187 	__u32 index;
188 	__u32 reserved;
189 	__u64 data;
190 };
191 
192 /* for KVM_GET_MSRS and KVM_SET_MSRS */
193 struct kvm_msrs {
194 	__u32 nmsrs; /* number of msrs in entries */
195 	__u32 pad;
196 
197 	struct kvm_msr_entry entries[0];
198 };
199 
200 /* for KVM_GET_MSR_INDEX_LIST */
201 struct kvm_msr_list {
202 	__u32 nmsrs; /* number of msrs in entries */
203 	__u32 indices[0];
204 };
205 
206 
207 struct kvm_cpuid_entry {
208 	__u32 function;
209 	__u32 eax;
210 	__u32 ebx;
211 	__u32 ecx;
212 	__u32 edx;
213 	__u32 padding;
214 };
215 
216 /* for KVM_SET_CPUID */
217 struct kvm_cpuid {
218 	__u32 nent;
219 	__u32 padding;
220 	struct kvm_cpuid_entry entries[0];
221 };
222 
223 struct kvm_cpuid_entry2 {
224 	__u32 function;
225 	__u32 index;
226 	__u32 flags;
227 	__u32 eax;
228 	__u32 ebx;
229 	__u32 ecx;
230 	__u32 edx;
231 	__u32 padding[3];
232 };
233 
234 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
235 #define KVM_CPUID_FLAG_STATEFUL_FUNC    2
236 #define KVM_CPUID_FLAG_STATE_READ_NEXT  4
237 
238 /* for KVM_SET_CPUID2 */
239 struct kvm_cpuid2 {
240 	__u32 nent;
241 	__u32 padding;
242 	struct kvm_cpuid_entry2 entries[0];
243 };
244 
245 /* for KVM_GET_PIT and KVM_SET_PIT */
246 struct kvm_pit_channel_state {
247 	__u32 count; /* can be 65536 */
248 	__u16 latched_count;
249 	__u8 count_latched;
250 	__u8 status_latched;
251 	__u8 status;
252 	__u8 read_state;
253 	__u8 write_state;
254 	__u8 write_latch;
255 	__u8 rw_mode;
256 	__u8 mode;
257 	__u8 bcd;
258 	__u8 gate;
259 	__s64 count_load_time;
260 };
261 
262 struct kvm_debug_exit_arch {
263 	__u32 exception;
264 	__u32 pad;
265 	__u64 pc;
266 	__u64 dr6;
267 	__u64 dr7;
268 };
269 
270 #define KVM_GUESTDBG_USE_SW_BP		0x00010000
271 #define KVM_GUESTDBG_USE_HW_BP		0x00020000
272 #define KVM_GUESTDBG_INJECT_DB		0x00040000
273 #define KVM_GUESTDBG_INJECT_BP		0x00080000
274 
275 /* for KVM_SET_GUEST_DEBUG */
276 struct kvm_guest_debug_arch {
277 	__u64 debugreg[8];
278 };
279 
280 struct kvm_pit_state {
281 	struct kvm_pit_channel_state channels[3];
282 };
283 
284 #define KVM_PIT_FLAGS_HPET_LEGACY  0x00000001
285 
286 struct kvm_pit_state2 {
287 	struct kvm_pit_channel_state channels[3];
288 	__u32 flags;
289 	__u32 reserved[9];
290 };
291 
292 struct kvm_reinject_control {
293 	__u8 pit_reinject;
294 	__u8 reserved[31];
295 };
296 
297 /* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
298 #define KVM_VCPUEVENT_VALID_NMI_PENDING	0x00000001
299 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR	0x00000002
300 
301 /* for KVM_GET/SET_VCPU_EVENTS */
302 struct kvm_vcpu_events {
303 	struct {
304 		__u8 injected;
305 		__u8 nr;
306 		__u8 has_error_code;
307 		__u8 pad;
308 		__u32 error_code;
309 	} exception;
310 	struct {
311 		__u8 injected;
312 		__u8 nr;
313 		__u8 soft;
314 		__u8 pad;
315 	} interrupt;
316 	struct {
317 		__u8 injected;
318 		__u8 pending;
319 		__u8 masked;
320 		__u8 pad;
321 	} nmi;
322 	__u32 sipi_vector;
323 	__u32 flags;
324 	__u32 reserved[10];
325 };
326 
327 #endif /* _ASM_X86_KVM_H */
328