xref: /illumos-kvm/kvm_vmx.h (revision 2a9ff8dc)
1 #ifndef VMX_H
2 #define	VMX_H
3 
4 /*
5  * vmx.h: VMX Architecture related definitions
6  * Copyright (c) 2004, Intel Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19  * Place - Suite 330, Boston, MA 02111-1307 USA.
20  *
21  * A few random additions are:
22  * Copyright (C) 2006 Qumranet
23  *    Avi Kivity <avi@qumranet.com>
24  *    Yaniv Kamay <yaniv@qumranet.com>
25  *
26  * Copyright 2011 Joyent, Inc.
27  */
28 
29 /*
30  * Currently we use one kernel module for all of kvm. This is the entry point
31  * for initializing and tearing down the VMX subsystem.
32  */
33 extern int vmx_init(void);
34 extern void vmx_fini(void);
35 
36 /*
37  * Definitions of Primary Processor-Based VM-Execution Controls.
38  */
39 #define	CPU_BASED_VIRTUAL_INTR_PENDING		0x00000004
40 #define	CPU_BASED_USE_TSC_OFFSETING		0x00000008
41 #define	CPU_BASED_HLT_EXITING			0x00000080
42 #define	CPU_BASED_INVLPG_EXITING		0x00000200
43 #define	CPU_BASED_MWAIT_EXITING			0x00000400
44 #define	CPU_BASED_RDPMC_EXITING			0x00000800
45 #define	CPU_BASED_RDTSC_EXITING			0x00001000
46 #define	CPU_BASED_CR3_LOAD_EXITING		0x00008000
47 #define	CPU_BASED_CR3_STORE_EXITING		0x00010000
48 #define	CPU_BASED_CR8_LOAD_EXITING		0x00080000
49 #define	CPU_BASED_CR8_STORE_EXITING		0x00100000
50 #define	CPU_BASED_TPR_SHADOW			0x00200000
51 #define	CPU_BASED_VIRTUAL_NMI_PENDING		0x00400000
52 #define	CPU_BASED_MOV_DR_EXITING		0x00800000
53 #define	CPU_BASED_UNCOND_IO_EXITING		0x01000000
54 #define	CPU_BASED_USE_IO_BITMAPS		0x02000000
55 #define	CPU_BASED_USE_MSR_BITMAPS		0x10000000
56 #define	CPU_BASED_MONITOR_EXITING		0x20000000
57 #define	CPU_BASED_PAUSE_EXITING			0x40000000
58 #define	CPU_BASED_ACTIVATE_SECONDARY_CONTROLS	0x80000000
59 /*
60  * Definitions of Secondary Processor-Based VM-Execution Controls.
61  */
62 #define	SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES	0x00000001
63 #define	SECONDARY_EXEC_ENABLE_EPT		0x00000002
64 #define	SECONDARY_EXEC_RDTSCP			0x00000008
65 #define	SECONDARY_EXEC_ENABLE_VPID		0x00000020
66 #define	SECONDARY_EXEC_WBINVD_EXITING		0x00000040
67 #define	SECONDARY_EXEC_UNRESTRICTED_GUEST	0x00000080
68 #define	SECONDARY_EXEC_PAUSE_LOOP_EXITING	0x00000400
69 
70 
71 #define	PIN_BASED_EXT_INTR_MASK			0x00000001
72 #define	PIN_BASED_NMI_EXITING			0x00000008
73 #define	PIN_BASED_VIRTUAL_NMIS			0x00000020
74 
75 #define	VM_EXIT_HOST_ADDR_SPACE_SIZE		0x00000200
76 #define	VM_EXIT_ACK_INTR_ON_EXIT		0x00008000
77 #define	VM_EXIT_SAVE_IA32_PAT			0x00040000
78 #define	VM_EXIT_LOAD_IA32_PAT			0x00080000
79 
80 #define	VM_ENTRY_IA32E_MODE			0x00000200
81 #define	VM_ENTRY_SMM				0x00000400
82 #define	VM_ENTRY_DEACT_DUAL_MONITOR		0x00000800
83 #define	VM_ENTRY_LOAD_IA32_PAT			0x00004000
84 
85 /* VMCS Encodings */
86 enum vmcs_field {
87 	VIRTUAL_PROCESSOR_ID		= 0x00000000,
88 	GUEST_ES_SELECTOR		= 0x00000800,
89 	GUEST_CS_SELECTOR		= 0x00000802,
90 	GUEST_SS_SELECTOR		= 0x00000804,
91 	GUEST_DS_SELECTOR		= 0x00000806,
92 	GUEST_FS_SELECTOR		= 0x00000808,
93 	GUEST_GS_SELECTOR		= 0x0000080a,
94 	GUEST_LDTR_SELECTOR		= 0x0000080c,
95 	GUEST_TR_SELECTOR		= 0x0000080e,
96 	HOST_ES_SELECTOR		= 0x00000c00,
97 	HOST_CS_SELECTOR		= 0x00000c02,
98 	HOST_SS_SELECTOR		= 0x00000c04,
99 	HOST_DS_SELECTOR		= 0x00000c06,
100 	HOST_FS_SELECTOR		= 0x00000c08,
101 	HOST_GS_SELECTOR		= 0x00000c0a,
102 	HOST_TR_SELECTOR		= 0x00000c0c,
103 	IO_BITMAP_A			= 0x00002000,
104 	IO_BITMAP_A_HIGH		= 0x00002001,
105 	IO_BITMAP_B			= 0x00002002,
106 	IO_BITMAP_B_HIGH		= 0x00002003,
107 	MSR_BITMAP			= 0x00002004,
108 	MSR_BITMAP_HIGH			= 0x00002005,
109 	VM_EXIT_MSR_STORE_ADDR		= 0x00002006,
110 	VM_EXIT_MSR_STORE_ADDR_HIGH	= 0x00002007,
111 	VM_EXIT_MSR_LOAD_ADDR		= 0x00002008,
112 	VM_EXIT_MSR_LOAD_ADDR_HIGH	= 0x00002009,
113 	VM_ENTRY_MSR_LOAD_ADDR		= 0x0000200a,
114 	VM_ENTRY_MSR_LOAD_ADDR_HIGH	= 0x0000200b,
115 	TSC_OFFSET			= 0x00002010,
116 	TSC_OFFSET_HIGH			= 0x00002011,
117 	VIRTUAL_APIC_PAGE_ADDR		= 0x00002012,
118 	VIRTUAL_APIC_PAGE_ADDR_HIGH	= 0x00002013,
119 	APIC_ACCESS_ADDR		= 0x00002014,
120 	APIC_ACCESS_ADDR_HIGH		= 0x00002015,
121 	EPT_POINTER			= 0x0000201a,
122 	EPT_POINTER_HIGH		= 0x0000201b,
123 	GUEST_PHYSICAL_ADDRESS		= 0x00002400,
124 	GUEST_PHYSICAL_ADDRESS_HIGH	= 0x00002401,
125 	VMCS_LINK_POINTER		= 0x00002800,
126 	VMCS_LINK_POINTER_HIGH		= 0x00002801,
127 	GUEST_IA32_DEBUGCTL		= 0x00002802,
128 	GUEST_IA32_DEBUGCTL_HIGH	= 0x00002803,
129 	GUEST_IA32_PAT			= 0x00002804,
130 	GUEST_IA32_PAT_HIGH		= 0x00002805,
131 	GUEST_PDPTR0			= 0x0000280a,
132 	GUEST_PDPTR0_HIGH		= 0x0000280b,
133 	GUEST_PDPTR1			= 0x0000280c,
134 	GUEST_PDPTR1_HIGH		= 0x0000280d,
135 	GUEST_PDPTR2			= 0x0000280e,
136 	GUEST_PDPTR2_HIGH		= 0x0000280f,
137 	GUEST_PDPTR3			= 0x00002810,
138 	GUEST_PDPTR3_HIGH		= 0x00002811,
139 	HOST_IA32_PAT			= 0x00002c00,
140 	HOST_IA32_PAT_HIGH		= 0x00002c01,
141 	PIN_BASED_VM_EXEC_CONTROL	= 0x00004000,
142 	CPU_BASED_VM_EXEC_CONTROL	= 0x00004002,
143 	EXCEPTION_BITMAP		= 0x00004004,
144 	PAGE_FAULT_ERROR_CODE_MASK	= 0x00004006,
145 	PAGE_FAULT_ERROR_CODE_MATCH	= 0x00004008,
146 	CR3_TARGET_COUNT		= 0x0000400a,
147 	VM_EXIT_CONTROLS		= 0x0000400c,
148 	VM_EXIT_MSR_STORE_COUNT		= 0x0000400e,
149 	VM_EXIT_MSR_LOAD_COUNT		= 0x00004010,
150 	VM_ENTRY_CONTROLS		= 0x00004012,
151 	VM_ENTRY_MSR_LOAD_COUNT		= 0x00004014,
152 	VM_ENTRY_INTR_INFO_FIELD	= 0x00004016,
153 	VM_ENTRY_EXCEPTION_ERROR_CODE	= 0x00004018,
154 	VM_ENTRY_INSTRUCTION_LEN	= 0x0000401a,
155 	TPR_THRESHOLD			= 0x0000401c,
156 	SECONDARY_VM_EXEC_CONTROL	= 0x0000401e,
157 	PLE_GAP				= 0x00004020,
158 	PLE_WINDOW			= 0x00004022,
159 	VM_INSTRUCTION_ERROR		= 0x00004400,
160 	VM_EXIT_REASON			= 0x00004402,
161 	VM_EXIT_INTR_INFO		= 0x00004404,
162 	VM_EXIT_INTR_ERROR_CODE		= 0x00004406,
163 	IDT_VECTORING_INFO_FIELD	= 0x00004408,
164 	IDT_VECTORING_ERROR_CODE	= 0x0000440a,
165 	VM_EXIT_INSTRUCTION_LEN		= 0x0000440c,
166 	VMX_INSTRUCTION_INFO		= 0x0000440e,
167 	GUEST_ES_LIMIT			= 0x00004800,
168 	GUEST_CS_LIMIT			= 0x00004802,
169 	GUEST_SS_LIMIT			= 0x00004804,
170 	GUEST_DS_LIMIT			= 0x00004806,
171 	GUEST_FS_LIMIT			= 0x00004808,
172 	GUEST_GS_LIMIT			= 0x0000480a,
173 	GUEST_LDTR_LIMIT		= 0x0000480c,
174 	GUEST_TR_LIMIT			= 0x0000480e,
175 	GUEST_GDTR_LIMIT		= 0x00004810,
176 	GUEST_IDTR_LIMIT		= 0x00004812,
177 	GUEST_ES_AR_BYTES		= 0x00004814,
178 	GUEST_CS_AR_BYTES		= 0x00004816,
179 	GUEST_SS_AR_BYTES		= 0x00004818,
180 	GUEST_DS_AR_BYTES		= 0x0000481a,
181 	GUEST_FS_AR_BYTES		= 0x0000481c,
182 	GUEST_GS_AR_BYTES		= 0x0000481e,
183 	GUEST_LDTR_AR_BYTES		= 0x00004820,
184 	GUEST_TR_AR_BYTES		= 0x00004822,
185 	GUEST_INTERRUPTIBILITY_INFO	= 0x00004824,
186 	GUEST_ACTIVITY_STATE		= 0X00004826,
187 	GUEST_SYSENTER_CS		= 0x0000482A,
188 	HOST_IA32_SYSENTER_CS		= 0x00004c00,
189 	CR0_GUEST_HOST_MASK		= 0x00006000,
190 	CR4_GUEST_HOST_MASK		= 0x00006002,
191 	CR0_READ_SHADOW			= 0x00006004,
192 	CR4_READ_SHADOW			= 0x00006006,
193 	CR3_TARGET_VALUE0		= 0x00006008,
194 	CR3_TARGET_VALUE1		= 0x0000600a,
195 	CR3_TARGET_VALUE2		= 0x0000600c,
196 	CR3_TARGET_VALUE3		= 0x0000600e,
197 	EXIT_QUALIFICATION		= 0x00006400,
198 	GUEST_LINEAR_ADDRESS		= 0x0000640a,
199 	GUEST_CR0			= 0x00006800,
200 	GUEST_CR3			= 0x00006802,
201 	GUEST_CR4			= 0x00006804,
202 	GUEST_ES_BASE			= 0x00006806,
203 	GUEST_CS_BASE			= 0x00006808,
204 	GUEST_SS_BASE			= 0x0000680a,
205 	GUEST_DS_BASE			= 0x0000680c,
206 	GUEST_FS_BASE			= 0x0000680e,
207 	GUEST_GS_BASE			= 0x00006810,
208 	GUEST_LDTR_BASE			= 0x00006812,
209 	GUEST_TR_BASE			= 0x00006814,
210 	GUEST_GDTR_BASE			= 0x00006816,
211 	GUEST_IDTR_BASE			= 0x00006818,
212 	GUEST_DR7			= 0x0000681a,
213 	GUEST_RSP			= 0x0000681c,
214 	GUEST_RIP			= 0x0000681e,
215 	GUEST_RFLAGS			= 0x00006820,
216 	GUEST_PENDING_DBG_EXCEPTIONS	= 0x00006822,
217 	GUEST_SYSENTER_ESP		= 0x00006824,
218 	GUEST_SYSENTER_EIP		= 0x00006826,
219 	HOST_CR0			= 0x00006c00,
220 	HOST_CR3			= 0x00006c02,
221 	HOST_CR4			= 0x00006c04,
222 	HOST_FS_BASE			= 0x00006c06,
223 	HOST_GS_BASE			= 0x00006c08,
224 	HOST_TR_BASE			= 0x00006c0a,
225 	HOST_GDTR_BASE			= 0x00006c0c,
226 	HOST_IDTR_BASE			= 0x00006c0e,
227 	HOST_IA32_SYSENTER_ESP		= 0x00006c10,
228 	HOST_IA32_SYSENTER_EIP		= 0x00006c12,
229 	HOST_RSP			= 0x00006c14,
230 	HOST_RIP			= 0x00006c16,
231 };
232 
233 #define	VMX_EXIT_REASONS_FAILED_VMENTRY		0x80000000
234 
235 #define	EXIT_REASON_EXCEPTION_NMI		0
236 #define	EXIT_REASON_EXTERNAL_INTERRUPT		1
237 #define	EXIT_REASON_TRIPLE_FAULT		2
238 
239 #define	EXIT_REASON_PENDING_INTERRUPT		7
240 #define	EXIT_REASON_NMI_WINDOW			8
241 #define	EXIT_REASON_TASK_SWITCH			9
242 #define	EXIT_REASON_CPUID			10
243 #define	EXIT_REASON_HLT				12
244 #define	EXIT_REASON_INVLPG			14
245 #define	EXIT_REASON_RDPMC			15
246 #define	EXIT_REASON_RDTSC			16
247 #define	EXIT_REASON_VMCALL			18
248 #define	EXIT_REASON_VMCLEAR			19
249 #define	EXIT_REASON_VMLAUNCH			20
250 #define	EXIT_REASON_VMPTRLD			21
251 #define	EXIT_REASON_VMPTRST			22
252 #define	EXIT_REASON_VMREAD			23
253 #define	EXIT_REASON_VMRESUME			24
254 #define	EXIT_REASON_VMWRITE			25
255 #define	EXIT_REASON_VMOFF			26
256 #define	EXIT_REASON_VMON			27
257 #define	EXIT_REASON_CR_ACCESS			28
258 #define	EXIT_REASON_DR_ACCESS			29
259 #define	EXIT_REASON_IO_INSTRUCTION		30
260 #define	EXIT_REASON_MSR_READ			31
261 #define	EXIT_REASON_MSR_WRITE			32
262 #define	EXIT_REASON_MWAIT_INSTRUCTION		36
263 #define	EXIT_REASON_MONITOR_INSTRUCTION		39
264 #define	EXIT_REASON_PAUSE_INSTRUCTION		40
265 #define	EXIT_REASON_MCE_DURING_VMENTRY		41
266 #define	EXIT_REASON_TPR_BELOW_THRESHOLD		43
267 #define	EXIT_REASON_APIC_ACCESS			44
268 #define	EXIT_REASON_EPT_VIOLATION		48
269 #define	EXIT_REASON_EPT_MISCONFIG		49
270 #define	EXIT_REASON_WBINVD			54
271 
272 /*
273  * Interruption-information format
274  */
275 #define	INTR_INFO_VECTOR_MASK			0xff		/* 7:0 */
276 #define	INTR_INFO_INTR_TYPE_MASK		0x700		/* 10:8 */
277 #define	INTR_INFO_DELIVER_CODE_MASK		0x800		/* 11 */
278 #define	INTR_INFO_UNBLOCK_NMI			0x1000		/* 12 */
279 #define	INTR_INFO_VALID_MASK			0x80000000	/* 31 */
280 #define	INTR_INFO_RESVD_BITS_MASK		0x7ffff000
281 
282 #define	VECTORING_INFO_VECTOR_MASK		INTR_INFO_VECTOR_MASK
283 #define	VECTORING_INFO_TYPE_MASK		INTR_INFO_INTR_TYPE_MASK
284 #define	VECTORING_INFO_DELIVER_CODE_MASK	INTR_INFO_DELIVER_CODE_MASK
285 #define	VECTORING_INFO_VALID_MASK		INTR_INFO_VALID_MASK
286 
287 #define	INTR_TYPE_EXT_INTR			(0 << 8)
288 #define	INTR_TYPE_NMI_INTR			(2 << 8)
289 #define	INTR_TYPE_HARD_EXCEPTION		(3 << 8)
290 #define	INTR_TYPE_SOFT_INTR			(4 << 8)
291 #define	INTR_TYPE_SOFT_EXCEPTION		(6 << 8)
292 
293 /* GUEST_INTERRUPTIBILITY_INFO flags. */
294 #define	GUEST_INTR_STATE_STI			0x00000001
295 #define	GUEST_INTR_STATE_MOV_SS			0x00000002
296 #define	GUEST_INTR_STATE_SMI			0x00000004
297 #define	GUEST_INTR_STATE_NMI			0x00000008
298 
299 /*
300  * Exit Qualifications for MOV for Control Register Access
301  *
302  * CONTROL_REG_ACCESS_NUM	2:0, number of control reg.
303  * CONTROL_REG_ACCESS_TYPE	5:4, access type
304  * CONTROL_REG_ACCESS_SHIFT	10:8, general purpose reg.
305  * LMSW_SOURCE_DATA		16:31 lmsw source
306  */
307 #define	CONTROL_REG_ACCESS_NUM		0x7
308 #define	CONTROL_REG_ACCESS_TYPE		0x30
309 #define	CONTROL_REG_ACCESS_REG		0xf00
310 #define	LMSW_SOURCE_DATA_SHIFT		16
311 #define	LMSW_SOURCE_DATA		(0xFFFF << LMSW_SOURCE_DATA_SHIFT)
312 #define	REG_EAX				(0 << 8)
313 #define	REG_ECX				(1 << 8)
314 #define	REG_EDX				(2 << 8)
315 #define	REG_EBX				(3 << 8)
316 #define	REG_ESP				(4 << 8)
317 #define	REG_EBP				(5 << 8)
318 #define	REG_ESI				(6 << 8)
319 #define	REG_EDI				(7 << 8)
320 
321 /*
322  * Exit Qualifications for MOV for Debug Register Access
323  *
324  * DEBUG_REG_ACCESS_NUM		2:0, number of debug reg.
325  * DEBUG_REG_ACCESS_TYPE	4, direction of access
326  * DEBUG_REG_ACCESS_REG(eq)	11:8, general purpose reg.
327  */
328 #define	DEBUG_REG_ACCESS_NUM		0x7
329 #define	DEBUG_REG_ACCESS_TYPE		0x10
330 #define	TYPE_MOV_TO_DR			(0 << 4)
331 #define	TYPE_MOV_FROM_DR		(1 << 4)
332 #define	DEBUG_REG_ACCESS_REG(eq)	(((eq) >> 8) & 0xf)
333 
334 
335 /* segment AR */
336 #define	SEGMENT_AR_L_MASK		(1 << 13)
337 
338 #define	AR_TYPE_ACCESSES_MASK		1
339 #define	AR_TYPE_READABLE_MASK		(1 << 1)
340 #define	AR_TYPE_WRITEABLE_MASK		(1 << 2)
341 #define	AR_TYPE_CODE_MASK		(1 << 3)
342 #define	AR_TYPE_MASK			0x0f
343 #define	AR_TYPE_BUSY_64_TSS		11
344 #define	AR_TYPE_BUSY_32_TSS		11
345 #define	AR_TYPE_BUSY_16_TSS		3
346 #define	AR_TYPE_LDT			2
347 
348 #define	AR_UNUSABLE_MASK		(1 << 16)
349 #define	AR_S_MASK			(1 << 4)
350 #define	AR_P_MASK			(1 << 7)
351 #define	AR_L_MASK			(1 << 13)
352 #define	AR_DB_MASK			(1 << 14)
353 #define	AR_G_MASK			(1 << 15)
354 #define	AR_DPL_SHIFT			5
355 #define	AR_DPL(ar) 			(((ar) >> AR_DPL_SHIFT) & 3)
356 
357 #define	AR_RESERVD_MASK	0xfffe0f00
358 
359 #define	TSS_PRIVATE_MEMSLOT			(KVM_MEMORY_SLOTS + 0)
360 #define	APIC_ACCESS_PAGE_PRIVATE_MEMSLOT	(KVM_MEMORY_SLOTS + 1)
361 #define	IDENTITY_PAGETABLE_PRIVATE_MEMSLOT	(KVM_MEMORY_SLOTS + 2)
362 
363 #define	VMX_NR_VPIDS				(1 << 16)
364 #define	VMX_VPID_EXTENT_SINGLE_CONTEXT		1
365 #define	VMX_VPID_EXTENT_ALL_CONTEXT		2
366 
367 #define	VMX_EPT_EXTENT_INDIVIDUAL_ADDR		0
368 #define	VMX_EPT_EXTENT_CONTEXT			1
369 #define	VMX_EPT_EXTENT_GLOBAL			2
370 
371 #define	VMX_EPT_EXECUTE_ONLY_BIT		(1ull)
372 #define	VMX_EPT_PAGE_WALK_4_BIT			(1ull << 6)
373 #define	VMX_EPTP_UC_BIT				(1ull << 8)
374 #define	VMX_EPTP_WB_BIT				(1ull << 14)
375 #define	VMX_EPT_2MB_PAGE_BIT			(1ull << 16)
376 #define	VMX_EPT_1GB_PAGE_BIT			(1ull << 17)
377 #define	VMX_EPT_EXTENT_INDIVIDUAL_BIT		(1ull << 24)
378 #define	VMX_EPT_EXTENT_CONTEXT_BIT		(1ull << 25)
379 #define	VMX_EPT_EXTENT_GLOBAL_BIT		(1ull << 26)
380 
381 #define	VMX_EPT_DEFAULT_GAW			3
382 #define	VMX_EPT_MAX_GAW				0x4
383 #define	VMX_EPT_MT_EPTE_SHIFT			3
384 #define	VMX_EPT_GAW_EPTP_SHIFT			3
385 #define	VMX_EPT_DEFAULT_MT			0x6ull
386 #define	VMX_EPT_READABLE_MASK			0x1ull
387 #define	VMX_EPT_WRITABLE_MASK			0x2ull
388 #define	VMX_EPT_EXECUTABLE_MASK			0x4ull
389 #define	VMX_EPT_IPAT_BIT			(1ull << 6)
390 
391 #define	VMX_EPT_IDENTITY_PAGETABLE_ADDR		0xfffbc000ul
392 
393 
394 #define	ASM_VMX_VMCLEAR_RAX		".byte 0x66, 0x0f, 0xc7, 0x30"
395 #define	ASM_VMX_VMLAUNCH		".byte 0x0f, 0x01, 0xc2"
396 #define	ASM_VMX_VMRESUME		".byte 0x0f, 0x01, 0xc3"
397 #define	ASM_VMX_VMPTRLD_RAX		".byte 0x0f, 0xc7, 0x30"
398 #define	ASM_VMX_VMREAD_RDX_RAX		".byte 0x0f, 0x78, 0xd0"
399 #define	ASM_VMX_VMWRITE_RAX_RDX		".byte 0x0f, 0x79, 0xd0"
400 #define	ASM_VMX_VMWRITE_RSP_RDX		".byte 0x0f, 0x79, 0xd4"
401 #define	ASM_VMX_VMXOFF			".byte 0x0f, 0x01, 0xc4"
402 #define	ASM_VMX_VMXON_RAX		".byte 0xf3, 0x0f, 0xc7, 0x30"
403 #define	ASM_VMX_INVEPT			".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
404 #define	ASM_VMX_INVVPID			".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
405 
406 
407 
408 #endif
409