xref: /illumos-kvm/kvm_lapic.c (revision 9621d522)
1 /*
2  * Local APIC virtualization
3  *
4  * Copyright (C) 2006 Qumranet, Inc.
5  * Copyright (C) 2007 Novell
6  * Copyright (C) 2007 Intel
7  *
8  * Authors:
9  *   Dor Laor <dor.laor@qumranet.com>
10  *   Gregory Haskins <ghaskins@novell.com>
11  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
12  *
13  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
14  *
15  * This work is licensed under the terms of the GNU GPL, version 2.  See
16  * the COPYING file in the top-level directory.
17  *
18  * Copyright (c) 2012 Joyent, Inc. All rights reserved.
19  */
20 #include <sys/types.h>
21 #include <sys/atomic.h>
22 
23 #include "kvm_bitops.h"
24 #include "kvm_msr.h"
25 #include "kvm_apicdef.h"
26 #include "kvm_cpuid.h"
27 #include "kvm_x86host.h"
28 #include "kvm_x86impl.h"
29 #include "kvm_lapic.h"
30 #include "kvm_ioapic.h"
31 #include "kvm_irq.h"
32 
33 static int __apic_accept_irq(struct kvm_lapic *, int, int, int, int);
34 
35 #define	APIC_BUS_CYCLE_NS 1
36 #define	APIC_LDR	0xD0
37 
38 #define	LAPIC_MMIO_LENGTH		(1 << 12)
39 /* followed define is not in apicdef.h */
40 #define	APIC_SHORT_MASK			0xc0000
41 #define	APIC_DEST_NOSHORT		0x0
42 #define	APIC_DEST_MASK			0x800
43 #define	MAX_APIC_VECTOR			256
44 
45 
46 #define	LVT_MASK	\
47 	(APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
48 
49 #define	LINT_MASK	\
50 	(LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
51 	APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
52 
53 #define	VEC_POS(v) ((v) & (32 - 1))
54 #define	REG_POS(v) (((v) >> 5) << 4)
55 
56 
57 uint32_t
apic_get_reg(struct kvm_lapic * apic,int reg_off)58 apic_get_reg(struct kvm_lapic *apic, int reg_off)
59 {
60 	return (*((uint32_t *)((uintptr_t)apic->regs + reg_off)));
61 }
62 
63 void
apic_set_reg(struct kvm_lapic * apic,int reg_off,uint32_t val)64 apic_set_reg(struct kvm_lapic *apic, int reg_off, uint32_t val)
65 {
66 	*((uint32_t *)((uintptr_t)apic->regs + reg_off)) = val;
67 }
68 
69 static int
apic_test_and_set_vector(int vec,caddr_t bitmap)70 apic_test_and_set_vector(int vec, caddr_t bitmap)
71 {
72 	return (test_and_set_bit(VEC_POS(vec), (unsigned long *)(bitmap +
73 	    REG_POS(vec))));
74 }
75 
76 static int
apic_test_and_clear_vector(int vec,caddr_t bitmap)77 apic_test_and_clear_vector(int vec, caddr_t bitmap)
78 {
79 	return (test_and_clear_bit(VEC_POS(vec),
80 	    (unsigned long *)(bitmap + REG_POS(vec))));
81 }
82 
83 void
apic_set_vector(int vec,caddr_t bitmap)84 apic_set_vector(int vec, caddr_t bitmap)
85 {
86 	set_bit(VEC_POS(vec), (unsigned long *)(bitmap + REG_POS(vec)));
87 }
88 
89 void
apic_clear_vector(int vec,caddr_t bitmap)90 apic_clear_vector(int vec, caddr_t bitmap)
91 {
92 	clear_bit(VEC_POS(vec), (unsigned long *)(bitmap + REG_POS(vec)));
93 }
94 
95 int
apic_hw_enabled(struct kvm_lapic * apic)96 apic_hw_enabled(struct kvm_lapic *apic)
97 {
98 	return ((apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
99 }
100 
101 int
apic_sw_enabled(struct kvm_lapic * apic)102 apic_sw_enabled(struct kvm_lapic *apic)
103 {
104 	return (apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED);
105 }
106 
107 int
apic_enabled(struct kvm_lapic * apic)108 apic_enabled(struct kvm_lapic *apic)
109 {
110 	return (apic_sw_enabled(apic) && apic_hw_enabled(apic));
111 }
112 
113 int
kvm_apic_id(struct kvm_lapic * apic)114 kvm_apic_id(struct kvm_lapic *apic)
115 {
116 	return ((apic_get_reg(apic, APIC_ID) >> 24) & 0xff);
117 }
118 
119 static int
apic_lvt_enabled(struct kvm_lapic * apic,int lvt_type)120 apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
121 {
122 	return (!(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED));
123 }
124 
125 static int
apic_lvtt_period(struct kvm_lapic * apic)126 apic_lvtt_period(struct kvm_lapic *apic)
127 {
128 	return (apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC);
129 }
130 
131 static int
apic_lvt_nmi_mode(uint32_t lvt_val)132 apic_lvt_nmi_mode(uint32_t lvt_val)
133 {
134 	return ((lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI);
135 }
136 
137 void
kvm_apic_set_version(struct kvm_vcpu * vcpu)138 kvm_apic_set_version(struct kvm_vcpu *vcpu)
139 {
140 	struct kvm_lapic *apic = vcpu->arch.apic;
141 	struct kvm_cpuid_entry2 *feat;
142 	uint32_t v = APIC_VERSION;
143 
144 	if (!irqchip_in_kernel(vcpu->kvm))
145 		return;
146 
147 	feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
148 	if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
149 		v |= APIC_LVR_DIRECTED_EOI;
150 	apic_set_reg(apic, APIC_LVR, v);
151 }
152 
153 static int
apic_x2apic_mode(struct kvm_lapic * apic)154 apic_x2apic_mode(struct kvm_lapic *apic)
155 {
156 	return (apic->vcpu->arch.apic_base & X2APIC_ENABLE);
157 }
158 
159 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
160 	LVT_MASK | APIC_LVT_TIMER_PERIODIC,	/* LVTT */
161 	LVT_MASK | APIC_MODE_MASK,	/* LVTTHMR */
162 	LVT_MASK | APIC_MODE_MASK,	/* LVTPC */
163 	LINT_MASK, LINT_MASK,	/* LVT0-1 */
164 	LVT_MASK		/* LVTERR */
165 };
166 
167 static int
fls(int x)168 fls(int x)
169 {
170 	int r = 32;
171 
172 	if (!x)
173 		return (0);
174 
175 	if (!(x & 0xffff0000u)) {
176 		x <<= 16;
177 		r -= 16;
178 	}
179 	if (!(x & 0xff000000u)) {
180 		x <<= 8;
181 		r -= 8;
182 	}
183 	if (!(x & 0xf0000000u)) {
184 		x <<= 4;
185 		r -= 4;
186 	}
187 	if (!(x & 0xc0000000u)) {
188 		x <<= 2;
189 		r -= 2;
190 	}
191 	if (!(x & 0x80000000u)) {
192 		x <<= 1;
193 		r -= 1;
194 	}
195 
196 	return (r);
197 }
198 
199 static int
find_highest_vector(void * bitmap)200 find_highest_vector(void *bitmap)
201 {
202 	uint32_t *word = bitmap;
203 	int word_offset = MAX_APIC_VECTOR >> 5;
204 
205 	while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
206 		continue;
207 
208 	if (!word_offset && !word[0])
209 		return (-1);
210 	else
211 		return (fls(word[word_offset << 2]) - 1 + (word_offset << 5));
212 }
213 
214 static int
apic_test_and_set_irr(int vec,struct kvm_lapic * apic)215 apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
216 {
217 	apic->irr_pending = 1;
218 	return (apic_test_and_set_vector(vec, (void *)((uintptr_t)apic->regs +
219 	    APIC_IRR)));
220 }
221 
222 static int
apic_search_irr(struct kvm_lapic * apic)223 apic_search_irr(struct kvm_lapic *apic)
224 {
225 	return (find_highest_vector((void *)((uintptr_t)apic->regs +
226 	    APIC_IRR)));
227 }
228 
229 static int
apic_find_highest_irr(struct kvm_lapic * apic)230 apic_find_highest_irr(struct kvm_lapic *apic)
231 {
232 	int result;
233 
234 	if (!apic->irr_pending)
235 		return (-1);
236 
237 	result = apic_search_irr(apic);
238 	ASSERT(result == -1 || result >= 16);
239 
240 	return (result);
241 }
242 
243 static void
apic_clear_irr(int vec,struct kvm_lapic * apic)244 apic_clear_irr(int vec, struct kvm_lapic *apic)
245 {
246 	apic->irr_pending = 0;
247 	apic_clear_vector(vec, (void *)((uintptr_t)apic->regs + APIC_IRR));
248 	if (apic_search_irr(apic) != -1)
249 		apic->irr_pending = 1;
250 }
251 
252 int
kvm_lapic_find_highest_irr(struct kvm_vcpu * vcpu)253 kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
254 {
255 	struct kvm_lapic *apic = vcpu->arch.apic;
256 	int highest_irr;
257 
258 	/*
259 	 * This may race with setting of irr in __apic_accept_irq() and
260 	 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
261 	 * will cause vmexit immediately and the value will be recalculated
262 	 * on the next vmentry.
263 	 */
264 	if (!apic)
265 		return (0);
266 
267 	highest_irr = apic_find_highest_irr(apic);
268 
269 	return (highest_irr);
270 }
271 
272 int
kvm_apic_set_irq(struct kvm_vcpu * vcpu,struct kvm_lapic_irq * irq)273 kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
274 {
275 	struct kvm_lapic *apic = vcpu->arch.apic;
276 
277 	return (__apic_accept_irq(apic, irq->delivery_mode, irq->vector,
278 	    irq->level, irq->trig_mode));
279 }
280 
281 int
apic_find_highest_isr(struct kvm_lapic * apic)282 apic_find_highest_isr(struct kvm_lapic *apic)
283 {
284 	int ret;
285 
286 	ret = find_highest_vector((void *)((uintptr_t)apic->regs + APIC_ISR));
287 	ASSERT(ret == -1 || ret >= 16);
288 
289 	return (ret);
290 }
291 
292 void
apic_update_ppr(struct kvm_lapic * apic)293 apic_update_ppr(struct kvm_lapic *apic)
294 {
295 	uint32_t tpr, isrv, ppr;
296 	int isr;
297 
298 	tpr = apic_get_reg(apic, APIC_TASKPRI);
299 	isr = apic_find_highest_isr(apic);
300 	isrv = (isr != -1) ? isr : 0;
301 
302 	if ((tpr & 0xf0) >= (isrv & 0xf0))
303 		ppr = tpr & 0xff;
304 	else
305 		ppr = isrv & 0xf0;
306 
307 	apic_set_reg(apic, APIC_PROCPRI, ppr);
308 }
309 
310 void
apic_set_tpr(struct kvm_lapic * apic,uint32_t tpr)311 apic_set_tpr(struct kvm_lapic *apic, uint32_t tpr)
312 {
313 	apic_set_reg(apic, APIC_TASKPRI, tpr);
314 	apic_update_ppr(apic);
315 }
316 
317 int
kvm_apic_match_physical_addr(struct kvm_lapic * apic,uint16_t dest)318 kvm_apic_match_physical_addr(struct kvm_lapic *apic, uint16_t dest)
319 {
320 	return (dest == 0xff || kvm_apic_id(apic) == dest);
321 }
322 
323 int
kvm_apic_match_logical_addr(struct kvm_lapic * apic,uint8_t mda)324 kvm_apic_match_logical_addr(struct kvm_lapic *apic, uint8_t mda)
325 {
326 	int result = 0;
327 	uint32_t logical_id;
328 
329 	if (apic_x2apic_mode(apic)) {
330 		logical_id = apic_get_reg(apic, APIC_LDR);
331 		return (logical_id & mda);
332 	}
333 
334 	logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
335 
336 	switch (apic_get_reg(apic, APIC_DFR)) {
337 	case APIC_DFR_FLAT:
338 		if (logical_id & mda)
339 			result = 1;
340 		break;
341 	case APIC_DFR_CLUSTER:
342 		if (((logical_id >> 4) == (mda >> 0x4)) &&
343 		    (logical_id & mda & 0xf))
344 			result = 1;
345 		break;
346 	default:
347 		cmn_err(CE_WARN, "Bad DFR vcpu %d: %08x\n",
348 		    apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
349 		break;
350 	}
351 
352 	return (result);
353 }
354 
355 int
kvm_apic_match_dest(struct kvm_vcpu * vcpu,struct kvm_lapic * source,int short_hand,int dest,int dest_mode)356 kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
357     int short_hand, int dest, int dest_mode)
358 {
359 	int result = 0;
360 	struct kvm_lapic *target = vcpu->arch.apic;
361 
362 	ASSERT(target != NULL);
363 	switch (short_hand) {
364 	case APIC_DEST_NOSHORT:
365 		if (dest_mode == 0)
366 			/* Physical mode. */
367 			result = kvm_apic_match_physical_addr(target, dest);
368 		else
369 			/* Logical mode. */
370 			result = kvm_apic_match_logical_addr(target, dest);
371 		break;
372 	case APIC_DEST_SELF:
373 		result = (target == source);
374 		break;
375 	case APIC_DEST_ALLINC:
376 		result = 1;
377 		break;
378 	case APIC_DEST_ALLBUT:
379 		result = (target != source);
380 		break;
381 	default:
382 		cmn_err(CE_WARN, "Bad dest shorthand value %x\n", short_hand);
383 		break;
384 	}
385 
386 	return (result);
387 }
388 
389 /*
390  * Add a pending IRQ into lapic.
391  * Return 1 if successfully added and 0 if discarded.
392  */
393 static int
__apic_accept_irq(struct kvm_lapic * apic,int delivery_mode,int vector,int level,int trig_mode)394 __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
395     int vector, int level, int trig_mode)
396 {
397 	int result = 0;
398 	struct kvm_vcpu *vcpu = apic->vcpu;
399 
400 	switch (delivery_mode) {
401 	case APIC_DM_LOWEST:
402 		vcpu->arch.apic_arb_prio++;
403 	case APIC_DM_FIXED:
404 		/* FIXME add logic for vcpu on reset */
405 		if (!apic_enabled(apic))
406 			break;
407 
408 		if (trig_mode) {
409 			apic_set_vector(vector, (void *)((uintptr_t)apic->regs +
410 			    APIC_TMR));
411 		} else
412 			apic_clear_vector(vector,
413 			    (void *)((uintptr_t)apic->regs + APIC_TMR));
414 
415 		result = !apic_test_and_set_irr(vector, apic);
416 		if (!result) {
417 			break;
418 		}
419 
420 		kvm_vcpu_kick(vcpu);
421 		break;
422 
423 	case APIC_DM_REMRD:
424 		break;
425 
426 	case APIC_DM_SMI:
427 		break;
428 
429 	case APIC_DM_NMI:
430 		result = 1;
431 		kvm_inject_nmi(vcpu);
432 		kvm_vcpu_kick(vcpu);
433 		break;
434 
435 	case APIC_DM_INIT:
436 		if (level) {
437 			result = 1;
438 			vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
439 			kvm_vcpu_kick(vcpu);
440 		}
441 		break;
442 
443 	case APIC_DM_STARTUP:
444 		if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
445 			result = 1;
446 			vcpu->arch.sipi_vector = vector;
447 			vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
448 			kvm_vcpu_kick(vcpu);
449 		}
450 		break;
451 
452 	case APIC_DM_EXTINT:
453 		/*
454 		 * Should only be called by kvm_apic_local_deliver() with LVT0,
455 		 * before NMI watchdog was enabled. Already handled by
456 		 * kvm_apic_accept_pic_intr().
457 		 */
458 		break;
459 
460 	default:
461 		break;
462 	}
463 
464 	return (result);
465 }
466 
467 int
kvm_apic_compare_prio(struct kvm_vcpu * vcpu1,struct kvm_vcpu * vcpu2)468 kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
469 {
470 	return (vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio);
471 }
472 
473 static void
apic_set_eoi(struct kvm_lapic * apic)474 apic_set_eoi(struct kvm_lapic *apic)
475 {
476 	int vector = apic_find_highest_isr(apic);
477 	int trigger_mode;
478 	/*
479 	 * Not every write EOI will has corresponding ISR,
480 	 * one example is when Kernel check timer on setup_IO_APIC
481 	 */
482 	if (vector == -1)
483 		return;
484 
485 	apic_clear_vector(vector, (void *)((uintptr_t)apic->regs + APIC_ISR));
486 	apic_update_ppr(apic);
487 
488 	if (apic_test_and_clear_vector(vector, (void *)((uintptr_t)apic->regs +
489 	    APIC_TMR)))
490 		trigger_mode = IOAPIC_LEVEL_TRIG;
491 	else
492 		trigger_mode = IOAPIC_EDGE_TRIG;
493 	if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
494 		kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
495 }
496 
497 static void
apic_send_ipi(struct kvm_lapic * apic)498 apic_send_ipi(struct kvm_lapic *apic)
499 {
500 	uint32_t icr_low = apic_get_reg(apic, APIC_ICR);
501 	uint32_t icr_high = apic_get_reg(apic, APIC_ICR2);
502 	struct kvm_lapic_irq irq;
503 
504 	irq.vector = icr_low & APIC_VECTOR_MASK;
505 	irq.delivery_mode = icr_low & APIC_MODE_MASK;
506 	irq.dest_mode = icr_low & APIC_DEST_MASK;
507 	irq.level = icr_low & APIC_INT_ASSERT;
508 	irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
509 	irq.shorthand = icr_low & APIC_SHORT_MASK;
510 	if (apic_x2apic_mode(apic))
511 		irq.dest_id = icr_high;
512 	else
513 		irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
514 
515 	KVM_TRACE2(apic__ipi, uint32_t, icr_low, uint32_t, irq.dest_id);
516 	kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
517 }
518 
519 static uint32_t
apic_get_tmcct(struct kvm_lapic * apic)520 apic_get_tmcct(struct kvm_lapic *apic)
521 {
522 	hrtime_t now, remaining, elapsed;
523 	uint32_t tmcct;
524 
525 	VERIFY(apic != NULL);
526 
527 	/* if initial count is 0, current count should also be 0 */
528 	if (apic_get_reg(apic, APIC_TMICT) == 0)
529 		return (0);
530 
531 	now = gethrtime();
532 	elapsed = now - apic->lapic_timer.start -
533 	    apic->lapic_timer.period * apic->lapic_timer.intervals;
534 	remaining = apic->lapic_timer.period - elapsed;
535 
536 	if (remaining < 0)
537 		remaining = 0;
538 
539 	remaining = remaining % apic->lapic_timer.period;
540 	tmcct = remaining / (APIC_BUS_CYCLE_NS * apic->divide_count);
541 
542 	return (tmcct);
543 }
544 
545 static void
__report_tpr_access(struct kvm_lapic * apic,int write)546 __report_tpr_access(struct kvm_lapic *apic, int write)
547 {
548 	struct kvm_vcpu *vcpu = apic->vcpu;
549 	struct kvm_run *run = vcpu->run;
550 
551 	set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
552 	run->tpr_access.rip = kvm_rip_read(vcpu);
553 	run->tpr_access.is_write = write;
554 }
555 
556 static void
report_tpr_access(struct kvm_lapic * apic,int write)557 report_tpr_access(struct kvm_lapic *apic, int write)
558 {
559 	if (apic->vcpu->arch.tpr_access_reporting)
560 		__report_tpr_access(apic, write);
561 }
562 
563 static uint32_t
__apic_read(struct kvm_lapic * apic,unsigned int offset)564 __apic_read(struct kvm_lapic *apic, unsigned int offset)
565 {
566 	uint32_t val = 0;
567 
568 	if (offset >= LAPIC_MMIO_LENGTH)
569 		return (0);
570 
571 	switch (offset) {
572 	case APIC_ID:
573 		if (apic_x2apic_mode(apic))
574 			val = kvm_apic_id(apic);
575 		else
576 			val = kvm_apic_id(apic) << 24;
577 		break;
578 	case APIC_ARBPRI:
579 		cmn_err(CE_WARN, "Access APIC ARBPRI register "
580 		    "which is for P6\n");
581 		break;
582 
583 	case APIC_TMCCT:	/* Timer CCR */
584 		val = apic_get_tmcct(apic);
585 		break;
586 
587 	case APIC_TASKPRI:
588 		report_tpr_access(apic, 0);
589 		/* fall thru */
590 	default:
591 		apic_update_ppr(apic);
592 		val = apic_get_reg(apic, offset);
593 		break;
594 	}
595 
596 	return (val);
597 }
598 
599 static struct kvm_lapic *
to_lapic(struct kvm_io_device * dev)600 to_lapic(struct kvm_io_device *dev)
601 {
602 	return ((struct kvm_lapic *)((uintptr_t)dev -
603 	    offsetof(struct kvm_lapic, dev)));
604 }
605 
606 int
apic_reg_read(struct kvm_lapic * apic,uint32_t offset,int len,void * data)607 apic_reg_read(struct kvm_lapic *apic, uint32_t offset, int len, void *data)
608 {
609 	unsigned char alignment = offset & 0xf;
610 	uint32_t result;
611 	/* this bitmask has a bit cleared for each reserver register */
612 	static const uint64_t rmask = 0x43ff01ffffffe70cULL;
613 
614 	if ((alignment + len) > 4) {
615 		return (1);
616 	}
617 
618 	if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
619 		return (1);
620 	}
621 
622 	result = __apic_read(apic, offset & ~0xf);
623 	KVM_TRACE2(apic__read, uint32_t, offset, uint32_t, result);
624 
625 	switch (len) {
626 	case 1:
627 	case 2:
628 	case 4:
629 		memcpy(data, (char *)&result + alignment, len);
630 		break;
631 	default:
632 		cmn_err(CE_WARN, "Local APIC read with len = %x, "
633 		    "should be 1,2, or 4 instead\n", len);
634 		break;
635 	}
636 
637 	return (0);
638 }
639 
640 static int
apic_mmio_in_range(struct kvm_lapic * apic,gpa_t addr)641 apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
642 {
643 	return (apic_hw_enabled(apic) &&
644 	    addr >= apic->base_address &&
645 	    addr < apic->base_address + LAPIC_MMIO_LENGTH);
646 }
647 
648 static int
apic_mmio_read(struct kvm_io_device * this,gpa_t address,int len,void * data)649 apic_mmio_read(struct kvm_io_device *this, gpa_t address, int len, void *data)
650 {
651 	struct kvm_lapic *apic = to_lapic(this);
652 	uint32_t offset = address - apic->base_address;
653 
654 	if (!apic_mmio_in_range(apic, address))
655 		return (-EOPNOTSUPP);
656 
657 	apic_reg_read(apic, offset, len, data);
658 
659 	return (0);
660 }
661 
662 void
update_divide_count(struct kvm_lapic * apic)663 update_divide_count(struct kvm_lapic *apic)
664 {
665 	uint32_t tmp1, tmp2, tdcr;
666 
667 	tdcr = apic_get_reg(apic, APIC_TDCR);
668 	tmp1 = tdcr & 0xf;
669 	tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
670 	apic->divide_count = 0x1 << (tmp2 & 0x7);
671 }
672 
673 void
start_apic_timer(struct kvm_lapic * apic)674 start_apic_timer(struct kvm_lapic *apic)
675 {
676 	hrtime_t now = gethrtime(), when;
677 	struct kvm_timer *timer = &apic->lapic_timer;
678 
679 	timer->period = (uint64_t)apic_get_reg(apic, APIC_TMICT) *
680 	    APIC_BUS_CYCLE_NS * apic->divide_count;
681 
682 	if (timer->active) {
683 		if (timer->period != 0 && !apic_lvtt_period(apic) &&
684 		    timer->kvm_cyc_when.cyt_interval == CY_INFINITY) {
685 			/*
686 			 * If we were a one-shot timer and we remain a
687 			 * one-shot timer, we will cyclic_reprogram() instead
688 			 * of horsing around with removing and re-adding
689 			 * the cyclic.
690 			 */
691 			timer->start = gethrtime();
692 			timer->kvm_cyc_when.cyt_when = when =
693 			    timer->start + timer->period;
694 			timer->intervals = 0;
695 			cyclic_reprogram(timer->kvm_cyclic_id, when);
696 			return;
697 		}
698 
699 		mutex_enter(&cpu_lock);
700 		cyclic_remove(timer->kvm_cyclic_id);
701 		timer->active = 0;
702 		mutex_exit(&cpu_lock);
703 	}
704 
705 	if (!timer->period)
706 		return;
707 
708 	mutex_enter(&cpu_lock);
709 
710 	timer->start = gethrtime();
711 
712 	/*
713 	 * Do not allow the guest to program periodic timers with small
714 	 * interval, since the hrtimers are not throttled by the host
715 	 * scheduler.
716 	 *
717 	 * If it is a one shot, we want to program it differently.
718 	 */
719 	if (apic_lvtt_period(apic)) {
720 		if (timer->period < NSEC_PER_MSEC / 2)
721 			timer->period = NSEC_PER_MSEC / 2;
722 		timer->kvm_cyc_when.cyt_when = 0;
723 		timer->kvm_cyc_when.cyt_interval = timer->period;
724 	} else {
725 		timer->kvm_cyc_when.cyt_when = timer->start + timer->period;
726 		timer->kvm_cyc_when.cyt_interval = CY_INFINITY;
727 	}
728 
729 	timer->kvm_cyclic_id =
730 	    cyclic_add(&timer->kvm_cyc_handler, &timer->kvm_cyc_when);
731 	timer->active = 1;
732 	timer->intervals = 0;
733 	mutex_exit(&cpu_lock);
734 }
735 
736 static void
apic_manage_nmi_watchdog(struct kvm_lapic * apic,uint32_t lvt0_val)737 apic_manage_nmi_watchdog(struct kvm_lapic *apic, uint32_t lvt0_val)
738 {
739 	int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
740 
741 	if (apic_lvt_nmi_mode(lvt0_val)) {
742 		if (!nmi_wd_enabled)
743 			apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
744 	} else if (nmi_wd_enabled)
745 		apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
746 }
747 
748 int
apic_reg_write(struct kvm_lapic * apic,uint32_t reg,uint32_t val)749 apic_reg_write(struct kvm_lapic *apic, uint32_t reg, uint32_t val)
750 {
751 	int ret = 0;
752 
753 	KVM_TRACE2(apic__write, uint32_t, reg, uint32_t, val);
754 
755 	switch (reg) {
756 	case APIC_ID:		/* Local APIC ID */
757 		if (!apic_x2apic_mode(apic))
758 			apic_set_reg(apic, APIC_ID, val);
759 		else
760 			ret = 1;
761 		break;
762 
763 	case APIC_TASKPRI:
764 		report_tpr_access(apic, 1);
765 		apic_set_tpr(apic, val & 0xff);
766 		break;
767 
768 	case APIC_EOI:
769 		apic_set_eoi(apic);
770 		break;
771 
772 	case APIC_LDR:
773 		if (!apic_x2apic_mode(apic))
774 			apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
775 		else
776 			ret = 1;
777 		break;
778 
779 	case APIC_DFR:
780 		if (!apic_x2apic_mode(apic))
781 			apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
782 		else
783 			ret = 1;
784 		break;
785 
786 	case APIC_SPIV: {
787 		uint32_t mask = 0x3ff;
788 		if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
789 			mask |= APIC_SPIV_DIRECTED_EOI;
790 		apic_set_reg(apic, APIC_SPIV, val & mask);
791 		if (!(val & APIC_SPIV_APIC_ENABLED)) {
792 			int i;
793 			uint32_t lvt_val;
794 
795 			for (i = 0; i < APIC_LVT_NUM; i++) {
796 				lvt_val = apic_get_reg(apic,
797 				    APIC_LVTT + 0x10 * i);
798 				apic_set_reg(apic, APIC_LVTT + 0x10 * i,
799 				    lvt_val | APIC_LVT_MASKED);
800 			}
801 			apic->lapic_timer.pending = 0;
802 		}
803 		break;
804 	}
805 	case APIC_ICR:
806 		/* No delay here, so we always clear the pending bit */
807 		apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
808 		apic_send_ipi(apic);
809 		break;
810 
811 	case APIC_ICR2:
812 		if (!apic_x2apic_mode(apic))
813 			val &= 0xff000000;
814 		apic_set_reg(apic, APIC_ICR2, val);
815 		break;
816 
817 	case APIC_LVT0:
818 		apic_manage_nmi_watchdog(apic, val);
819 	case APIC_LVTT:
820 	case APIC_LVTTHMR:
821 	case APIC_LVTPC:
822 	case APIC_LVT1:
823 	case APIC_LVTERR:
824 		/* TODO: Check vector */
825 		if (!apic_sw_enabled(apic))
826 			val |= APIC_LVT_MASKED;
827 
828 		val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
829 		apic_set_reg(apic, reg, val);
830 
831 		break;
832 
833 	case APIC_TMICT:
834 		apic_set_reg(apic, APIC_TMICT, val);
835 		start_apic_timer(apic);
836 		break;
837 
838 	case APIC_TDCR:
839 		if (val & 4)
840 			cmn_err(CE_WARN, "KVM_WRITE:TDCR %x\n", val);
841 		apic_set_reg(apic, APIC_TDCR, val);
842 		update_divide_count(apic);
843 		break;
844 
845 	case APIC_ESR:
846 		if (apic_x2apic_mode(apic) && val != 0) {
847 			cmn_err(CE_WARN, "KVM_WRITE:ESR not zero %x\n", val);
848 			ret = 1;
849 		}
850 		break;
851 
852 	case APIC_SELF_IPI:
853 		if (apic_x2apic_mode(apic)) {
854 			apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
855 		} else
856 			ret = 1;
857 		break;
858 	default:
859 		ret = 1;
860 		break;
861 	}
862 
863 	return (ret);
864 }
865 
866 static int
apic_mmio_write(struct kvm_io_device * this,gpa_t address,int len,const void * data)867 apic_mmio_write(struct kvm_io_device *this,
868     gpa_t address, int len, const void *data)
869 {
870 	struct kvm_lapic *apic = to_lapic(this);
871 	unsigned int offset = address - apic->base_address;
872 	uint32_t val;
873 
874 	if (!apic_mmio_in_range(apic, address))
875 		return (-EOPNOTSUPP);
876 
877 	/*
878 	 * APIC register must be aligned on 128-bits boundary.
879 	 * 32/64/128 bits registers must be accessed thru 32 bits.
880 	 * Refer SDM 8.4.1
881 	 */
882 	if (len != 4 || (offset & 0xf)) {
883 		/* Don't shout loud, $infamous_os would cause only noise. */
884 		return (0);
885 	}
886 
887 	val = *(uint32_t *)data;
888 
889 	apic_reg_write(apic, offset & 0xff0, val);
890 
891 	return (0);
892 }
893 
894 void
kvm_free_lapic(struct kvm_vcpu * vcpu)895 kvm_free_lapic(struct kvm_vcpu *vcpu)
896 {
897 	struct kvm_lapic *apic = vcpu->arch.apic;
898 	if (apic == NULL)
899 		return;
900 
901 	mutex_enter(&cpu_lock);
902 	if (apic->lapic_timer.active)
903 		cyclic_remove(apic->lapic_timer.kvm_cyclic_id);
904 	mutex_exit(&cpu_lock);
905 
906 	if (apic->regs)
907 		kmem_free(apic->regs, PAGESIZE);
908 
909 	kmem_free(vcpu->arch.apic, sizeof (struct kvm_lapic));
910 }
911 
912 /*
913  * Local APIC interface.
914  */
915 void
kvm_lapic_set_tpr(struct kvm_vcpu * vcpu,unsigned long cr8)916 kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
917 {
918 	struct kvm_lapic *apic = vcpu->arch.apic;
919 
920 	if (!apic)
921 		return;
922 
923 	apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
924 	    (apic_get_reg(apic, APIC_TASKPRI) & 4));
925 }
926 
927 uint64_t
kvm_lapic_get_cr8(struct kvm_vcpu * vcpu)928 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
929 {
930 	struct kvm_lapic *apic = vcpu->arch.apic;
931 	uint64_t tpr;
932 
933 	if (apic == NULL)
934 		return (0);
935 
936 	tpr = (uint64_t)apic_get_reg(apic, APIC_TASKPRI);
937 
938 	return ((tpr & 0xf0) >> 4);
939 }
940 
941 void
kvm_lapic_set_base(struct kvm_vcpu * vcpu,uint64_t value)942 kvm_lapic_set_base(struct kvm_vcpu *vcpu, uint64_t value)
943 {
944 	struct kvm_lapic *apic = vcpu->arch.apic;
945 
946 	if (!apic) {
947 		value |= MSR_IA32_APICBASE_BSP;
948 		vcpu->arch.apic_base = value;
949 		return;
950 	}
951 
952 	if (!kvm_vcpu_is_bsp(apic->vcpu))
953 		value &= ~MSR_IA32_APICBASE_BSP;
954 
955 	vcpu->arch.apic_base = value;
956 	if (apic_x2apic_mode(apic)) {
957 		uint32_t id = kvm_apic_id(apic);
958 		uint32_t ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
959 		apic_set_reg(apic, APIC_LDR, ldr);
960 	}
961 
962 	apic->base_address = apic->vcpu->arch.apic_base &
963 	    MSR_IA32_APICBASE_BASE;
964 }
965 
966 void
kvm_lapic_reset(struct kvm_vcpu * vcpu)967 kvm_lapic_reset(struct kvm_vcpu *vcpu)
968 {
969 	struct kvm_lapic *apic;
970 	int i;
971 
972 	ASSERT(vcpu);
973 	apic = vcpu->arch.apic;
974 	ASSERT(apic != NULL);
975 
976 	/* Stop the timer in case it's a reset to an active apic */
977 	mutex_enter(&cpu_lock);
978 	if (apic->lapic_timer.active) {
979 		cyclic_remove(apic->lapic_timer.kvm_cyclic_id);
980 		apic->lapic_timer.active = 0;
981 	}
982 	mutex_exit(&cpu_lock);
983 
984 	apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
985 	kvm_apic_set_version(apic->vcpu);
986 
987 	for (i = 0; i < APIC_LVT_NUM; i++)
988 		apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
989 
990 	apic_set_reg(apic, APIC_LVT0,
991 	    SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
992 
993 	apic_set_reg(apic, APIC_DFR, 0xffffffffU);
994 	apic_set_reg(apic, APIC_SPIV, 0xff);
995 	apic_set_reg(apic, APIC_TASKPRI, 0);
996 	apic_set_reg(apic, APIC_LDR, 0);
997 	apic_set_reg(apic, APIC_ESR, 0);
998 	apic_set_reg(apic, APIC_ICR, 0);
999 	apic_set_reg(apic, APIC_ICR2, 0);
1000 	apic_set_reg(apic, APIC_TDCR, 0);
1001 	apic_set_reg(apic, APIC_TMICT, 0);
1002 	for (i = 0; i < 8; i++) {
1003 		apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1004 		apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1005 		apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1006 	}
1007 	apic->irr_pending = 0;
1008 	update_divide_count(apic);
1009 	apic->lapic_timer.pending = 0;
1010 
1011 	if (kvm_vcpu_is_bsp(vcpu))
1012 		vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1013 	apic_update_ppr(apic);
1014 
1015 	vcpu->arch.apic_arb_prio = 0;
1016 
1017 	cmn_err(CE_CONT, "!%s: vcpu=%p, id=%d, base_msr= %lx PRIx64 "
1018 	    "base_address=%lx\n", __func__, vcpu, kvm_apic_id(apic),
1019 	    vcpu->arch.apic_base, apic->base_address);
1020 }
1021 
1022 int
kvm_apic_present(struct kvm_vcpu * vcpu)1023 kvm_apic_present(struct kvm_vcpu *vcpu)
1024 {
1025 	return (vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic));
1026 }
1027 
1028 int
kvm_lapic_enabled(struct kvm_vcpu * vcpu)1029 kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1030 {
1031 	return (kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic));
1032 }
1033 
1034 /*
1035  * APIC timer interface
1036  */
1037 static int
lapic_is_periodic(struct kvm_timer * ktimer)1038 lapic_is_periodic(struct kvm_timer *ktimer)
1039 {
1040 	struct kvm_lapic *apic = (struct kvm_lapic *)((caddr_t)ktimer -
1041 	    offsetof(struct kvm_lapic, lapic_timer));
1042 
1043 	return (apic_lvtt_period(apic));
1044 }
1045 
1046 int
apic_has_pending_timer(struct kvm_vcpu * vcpu)1047 apic_has_pending_timer(struct kvm_vcpu *vcpu)
1048 {
1049 	struct kvm_lapic *lapic = vcpu->arch.apic;
1050 
1051 	if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1052 		return (lapic->lapic_timer.pending);
1053 
1054 	return (0);
1055 }
1056 
1057 static int
kvm_apic_local_deliver(struct kvm_lapic * apic,int lvt_type)1058 kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1059 {
1060 	uint32_t reg = apic_get_reg(apic, lvt_type);
1061 	int vector, mode, trig_mode;
1062 
1063 	if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1064 		vector = reg & APIC_VECTOR_MASK;
1065 		mode = reg & APIC_MODE_MASK;
1066 		trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1067 		return (__apic_accept_irq(apic, mode, vector, 1, trig_mode));
1068 	}
1069 	return (0);
1070 }
1071 
1072 void
kvm_apic_nmi_wd_deliver(struct kvm_vcpu * vcpu)1073 kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1074 {
1075 	struct kvm_lapic *apic = vcpu->arch.apic;
1076 
1077 	if (apic)
1078 		kvm_apic_local_deliver(apic, APIC_LVT0);
1079 }
1080 
1081 static struct kvm_timer_ops lapic_timer_ops = {
1082 	.is_periodic = lapic_is_periodic,
1083 };
1084 
1085 static const struct kvm_io_device_ops apic_mmio_ops = {
1086 	.read	= apic_mmio_read,
1087 	.write	= apic_mmio_write,
1088 };
1089 
1090 int
kvm_create_lapic(struct kvm_vcpu * vcpu)1091 kvm_create_lapic(struct kvm_vcpu *vcpu)
1092 {
1093 	struct kvm_lapic *apic;
1094 
1095 	ASSERT(vcpu != NULL);
1096 
1097 	apic = kmem_zalloc(sizeof (*apic), KM_SLEEP);
1098 	if (!apic)
1099 		goto nomem;
1100 
1101 	vcpu->arch.apic = apic;
1102 
1103 	apic->regs = kmem_zalloc(PAGESIZE, KM_SLEEP);
1104 	memset(apic->regs, 0, PAGESIZE);
1105 	apic->vcpu = vcpu;
1106 
1107 	apic->lapic_timer.kvm_cyc_handler.cyh_func = kvm_timer_fire;
1108 	apic->lapic_timer.kvm_cyc_handler.cyh_arg = &apic->lapic_timer;
1109 	apic->lapic_timer.kvm_cyc_handler.cyh_level = CY_LOW_LEVEL;
1110 	apic->lapic_timer.active = 0;
1111 
1112 	apic->lapic_timer.t_ops = &lapic_timer_ops;
1113 	apic->lapic_timer.kvm = vcpu->kvm;
1114 	apic->lapic_timer.vcpu = vcpu;
1115 
1116 	apic->base_address = APIC_DEFAULT_PHYS_BASE;
1117 	vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1118 
1119 	kvm_lapic_reset(vcpu);
1120 	kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1121 	apic->dev.lapic = apic;
1122 
1123 	return (0);
1124 nomem_free_apic:
1125 	if (apic)
1126 		kmem_free(apic, sizeof (struct kvm_lapic));
1127 nomem:
1128 	return (-ENOMEM);
1129 }
1130 
1131 int
kvm_apic_has_interrupt(struct kvm_vcpu * vcpu)1132 kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1133 {
1134 	struct kvm_lapic *apic = vcpu->arch.apic;
1135 	int highest_irr;
1136 
1137 	if (!apic || !apic_enabled(apic))
1138 		return (-1);
1139 
1140 	apic_update_ppr(apic);
1141 	highest_irr = apic_find_highest_irr(apic);
1142 	if ((highest_irr == -1) ||
1143 	    ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1144 		return (-1);
1145 
1146 	return (highest_irr);
1147 }
1148 
1149 int
kvm_apic_accept_pic_intr(struct kvm_vcpu * vcpu)1150 kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1151 {
1152 	uint32_t lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1153 	int r = 0;
1154 
1155 	if (kvm_vcpu_is_bsp(vcpu)) {
1156 		if (!apic_hw_enabled(vcpu->arch.apic))
1157 			r = 1;
1158 		if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1159 		    GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1160 			r = 1;
1161 	}
1162 
1163 	return (r);
1164 }
1165 
1166 void
kvm_inject_apic_timer_irqs(struct kvm_vcpu * vcpu)1167 kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1168 {
1169 	struct kvm_lapic *apic = vcpu->arch.apic;
1170 
1171 	if (apic && apic->lapic_timer.pending > 0) {
1172 		if (kvm_apic_local_deliver(apic, APIC_LVTT))
1173 			atomic_dec_32((volatile uint32_t *)&apic->
1174 			    lapic_timer.pending);
1175 	}
1176 }
1177 
1178 int
kvm_get_apic_interrupt(struct kvm_vcpu * vcpu)1179 kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1180 {
1181 	int vector = kvm_apic_has_interrupt(vcpu);
1182 	struct kvm_lapic *apic = vcpu->arch.apic;
1183 
1184 	if (vector == -1)
1185 		return (-1);
1186 
1187 	apic_set_vector(vector, (void *)((uintptr_t)apic->regs + APIC_ISR));
1188 	apic_update_ppr(apic);
1189 	apic_clear_irr(vector, apic);
1190 
1191 	return (vector);
1192 }
1193 
1194 void
kvm_apic_post_state_restore(struct kvm_vcpu * vcpu)1195 kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1196 {
1197 	struct kvm_lapic *apic = vcpu->arch.apic;
1198 
1199 	apic->base_address = vcpu->arch.apic_base &
1200 	    MSR_IA32_APICBASE_BASE;
1201 	kvm_apic_set_version(vcpu);
1202 
1203 	apic_update_ppr(apic);
1204 	update_divide_count(apic);
1205 	start_apic_timer(apic);
1206 
1207 	apic->irr_pending = 1;
1208 }
1209 
1210 void
kvm_lapic_sync_from_vapic(struct kvm_vcpu * vcpu)1211 kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1212 {
1213 	uint32_t data;
1214 	void *vapic;
1215 
1216 	if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1217 		return;
1218 
1219 	vapic = page_address(vcpu->arch.apic->vapic_page);
1220 
1221 	data = *(uint32_t *)((uintptr_t)vapic +
1222 	    offset_in_page(vcpu->arch.apic->vapic_addr));
1223 
1224 	apic_set_tpr(vcpu->arch.apic, data & 0xff);
1225 }
1226 
1227 void
kvm_lapic_sync_to_vapic(struct kvm_vcpu * vcpu)1228 kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1229 {
1230 	uint32_t data, tpr;
1231 	int max_irr, max_isr;
1232 	struct kvm_lapic *apic;
1233 	void *vapic;
1234 
1235 	if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1236 		return;
1237 
1238 	apic = vcpu->arch.apic;
1239 	tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1240 	max_irr = apic_find_highest_irr(apic);
1241 	if (max_irr < 0)
1242 		max_irr = 0;
1243 	max_isr = apic_find_highest_isr(apic);
1244 	if (max_isr < 0)
1245 		max_isr = 0;
1246 	data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1247 
1248 	vapic = page_address(vcpu->arch.apic->vapic_page);
1249 
1250 	*(uint32_t *)((uintptr_t)vapic +
1251 	    offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1252 }
1253 
1254 int
kvm_lapic_set_vapic_addr(struct kvm_vcpu * vcpu,struct kvm_vapic_addr * va)1255 kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, struct kvm_vapic_addr *va)
1256 {
1257 	if (!irqchip_in_kernel(vcpu->kvm))
1258 		return (EINVAL);
1259 
1260 	vcpu->arch.apic->vapic_addr = va->vapic_addr;
1261 
1262 	return (0);
1263 }
1264 
1265 int
kvm_x2apic_msr_write(struct kvm_vcpu * vcpu,uint32_t msr,uint64_t data)1266 kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, uint32_t msr, uint64_t data)
1267 {
1268 	struct kvm_lapic *apic = vcpu->arch.apic;
1269 	uint32_t reg = (msr - APIC_BASE_MSR) << 4;
1270 
1271 	if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1272 		return (1);
1273 
1274 	/* if this is ICR write vector before command */
1275 	if (msr == 0x830)
1276 		apic_reg_write(apic, APIC_ICR2, (uint32_t)(data >> 32));
1277 
1278 	return (apic_reg_write(apic, reg, (uint32_t)data));
1279 }
1280 
1281 int
kvm_x2apic_msr_read(struct kvm_vcpu * vcpu,uint32_t msr,uint64_t * data)1282 kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, uint32_t msr, uint64_t *data)
1283 {
1284 	struct kvm_lapic *apic = vcpu->arch.apic;
1285 	uint32_t reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1286 
1287 	if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1288 		return (1);
1289 
1290 	if (apic_reg_read(apic, reg, 4, &low))
1291 		return (1);
1292 
1293 	if (msr == 0x830)
1294 		apic_reg_read(apic, APIC_ICR2, 4, &high);
1295 
1296 	*data = (((uint64_t)high) << 32) | low;
1297 
1298 	return (0);
1299 }
1300 
1301 int
kvm_hv_vapic_msr_write(struct kvm_vcpu * vcpu,uint32_t reg,uint64_t data)1302 kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, uint32_t reg, uint64_t data)
1303 {
1304 	struct kvm_lapic *apic = vcpu->arch.apic;
1305 
1306 	if (!irqchip_in_kernel(vcpu->kvm))
1307 		return (1);
1308 
1309 	/* if this is ICR write vector before command */
1310 	if (reg == APIC_ICR)
1311 		apic_reg_write(apic, APIC_ICR2, (uint32_t)(data >> 32));
1312 
1313 	return (apic_reg_write(apic, reg, (uint32_t)data));
1314 }
1315 
1316 int
kvm_hv_vapic_msr_read(struct kvm_vcpu * vcpu,uint32_t reg,uint64_t * data)1317 kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, uint32_t reg, uint64_t *data)
1318 {
1319 	struct kvm_lapic *apic = vcpu->arch.apic;
1320 	uint32_t low, high = 0;
1321 
1322 	if (!irqchip_in_kernel(vcpu->kvm))
1323 		return (1);
1324 
1325 	if (apic_reg_read(apic, reg, 4, &low))
1326 		return (1);
1327 
1328 	if (reg == APIC_ICR)
1329 		apic_reg_read(apic, APIC_ICR2, 4, &high);
1330 
1331 	*data = (((uint64_t)high) << 32) | low;
1332 
1333 	return (0);
1334 }
1335