1Tiny Code Generator - Fabrice Bellard.
5TCG (Tiny Code Generator) began as a generic backend for a C
6compiler. It was simplified to be used in QEMU. It also has its roots
7in the QOP code generator written by Paul Brook.
11The TCG "target" is the architecture for which we generate the
12code. It is of course not the same as the "target" of QEMU which is
13the emulated architecture. As TCG started as a generic C backend used
14for cross compiling, it is assumed that the TCG target is different
15from the host, although it is never the case for QEMU.
17A TCG "function" corresponds to a QEMU Translated Block (TB).
19A TCG "temporary" is a variable only live in a basic
20block. Temporaries are allocated explicitly in each function.
22A TCG "local temporary" is a variable only live in a function. Local
23temporaries are allocated explicitly in each function.
25A TCG "global" is a variable which is live in all the functions
26(equivalent of a C global variable). They are defined before the
27functions defined. A TCG global can be a memory location (e.g. a QEMU
28CPU register), a fixed host register (e.g. the QEMU CPU state pointer)
29or a memory location which is stored in a register outside QEMU TBs
30(not implemented yet).
32A TCG "basic block" corresponds to a list of instructions terminated
33by a branch instruction.
353) Intermediate representation
39TCG instructions operate on variables which are temporaries, local
40temporaries or globals. TCG instructions and variables are strongly
41typed. Two types are supported: 32 bit integers and 64 bit
42integers. Pointers are defined as an alias to 32 bit or 64 bit
43integers depending on the TCG target word size.
45Each instruction has a fixed number of output variable operands, input
46variable operands and always constant operands.
48The notable exception is the call instruction which has a variable
49number of outputs and inputs.
51In the textual form, output operands usually come first, followed by
52input operands, followed by constant operands. The output type is
53included in the instruction name. Constants are prefixed with a '$'.
55add_i32 t0, t1, t2 (t0 <- t1 + t2)
59* Basic blocks
61- Basic blocks end after branches (e.g. brcond_i32 instruction),
62 goto_tb and exit_tb instructions.
63- Basic blocks start after the end of a previous basic block, or at a
64 set_label instruction.
66After the end of a basic block, the content of temporaries is
67destroyed, but local temporaries and globals are preserved.
69* Floating point types are not supported yet
71* Pointers: depending on the TCG target, pointer size is 32 bit or 64
72 bit. The type TCG_TYPE_PTR is an alias to TCG_TYPE_I32 or
77Using the tcg_gen_helper_x_y it is possible to call any function
78taking i32, i64 or pointer types. By default, before calling a helper,
79all globals are stored at their canonical location and it is assumed
80that the function can modify them. This can be overridden by the
81TCG_CALL_CONST function modifier. By default, the helper is allowed to
82modify the CPU state or raise an exception. This can be overridden by
83the TCG_CALL_PURE function modifier, in which case the call to the
84function is removed if the return value is not used.
86On some TCG targets (e.g. x86), several calling conventions are
91Use the instruction 'br' to jump to a label. Use 'jmp' to jump to an
92explicit address. Conditional branches can only jump to labels.
943.3) Code Optimizations
96When generating instructions, you can count on at least the following
99- Single instructions are simplified, e.g.
101 and_i32 t0, t0, $0xffffffff
103 is suppressed.
105- A liveness analysis is done at the basic block level. The
106 information is used to suppress moves from a dead variable to
107 another one. It is also used to remove instructions which compute
108 dead results. The later is especially useful for condition code
109 optimization in QEMU.
111 In the following example:
113 add_i32 t0, t1, t2
114 add_i32 t0, t0, $1
115 mov_i32 t0, $1
117 only the last instruction is kept.
1193.4) Instruction Reference
121********* Function call
123* call <ret> <params> ptr
125call function 'ptr' (pointer type)
127<ret> optional 32 bit or 64 bit return value
128<params> optional 32 bit or 64 bit parameters
132* jmp t0
134Absolute jump to address t0 (pointer type).
136* set_label $label
138Define label 'label' at the current program point.
140* br $label
142Jump to label.
144* brcond_i32/i64 cond, t0, t1, label
146Conditional jump if t0 cond t1 is true. cond can be:
149 TCG_COND_LT /* signed */
150 TCG_COND_GE /* signed */
151 TCG_COND_LE /* signed */
152 TCG_COND_GT /* signed */
153 TCG_COND_LTU /* unsigned */
154 TCG_COND_GEU /* unsigned */
155 TCG_COND_LEU /* unsigned */
156 TCG_COND_GTU /* unsigned */
160* add_i32/i64 t0, t1, t2
164* sub_i32/i64 t0, t1, t2
168* neg_i32/i64 t0, t1
170t0=-t1 (two's complement)
172* mul_i32/i64 t0, t1, t2
176* div_i32/i64 t0, t1, t2
178t0=t1/t2 (signed). Undefined behavior if division by zero or overflow.
180* divu_i32/i64 t0, t1, t2
182t0=t1/t2 (unsigned). Undefined behavior if division by zero.
184* rem_i32/i64 t0, t1, t2
186t0=t1%t2 (signed). Undefined behavior if division by zero or overflow.
188* remu_i32/i64 t0, t1, t2
190t0=t1%t2 (unsigned). Undefined behavior if division by zero.
194* and_i32/i64 t0, t1, t2
198* or_i32/i64 t0, t1, t2
202* xor_i32/i64 t0, t1, t2
206* not_i32/i64 t0, t1
210* andc_i32/i64 t0, t1, t2
214* eqv_i32/i64 t0, t1, t2
216t0=~(t1^t2), or equivalently, t0=t1^~t2
218* nand_i32/i64 t0, t1, t2
222* nor_i32/i64 t0, t1, t2
226* orc_i32/i64 t0, t1, t2
232* shl_i32/i64 t0, t1, t2
234t0=t1 << t2. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)
236* shr_i32/i64 t0, t1, t2
238t0=t1 >> t2 (unsigned). Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)
240* sar_i32/i64 t0, t1, t2
242t0=t1 >> t2 (signed). Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)
244* rotl_i32/i64 t0, t1, t2
246Rotation of t2 bits to the left. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)
248* rotr_i32/i64 t0, t1, t2
250Rotation of t2 bits to the right. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64)
254* mov_i32/i64 t0, t1
256t0 = t1
258Move t1 to t0 (both operands must have the same type).
260* ext8s_i32/i64 t0, t1
261ext8u_i32/i64 t0, t1
262ext16s_i32/i64 t0, t1
263ext16u_i32/i64 t0, t1
264ext32s_i64 t0, t1
265ext32u_i64 t0, t1
2678, 16 or 32 bit sign/zero extension (both operands must have the same type)
269* bswap16_i32/i64 t0, t1
27116 bit byte swap on a 32/64 bit value. It assumes that the two/six high order
272bytes are set to zero.
274* bswap32_i32/i64 t0, t1
27632 bit byte swap on a 32/64 bit value. With a 64 bit value, it assumes that
277the four high order bytes are set to zero.
279* bswap64_i64 t0, t1
28164 bit byte swap
283* discard_i32/i64 t0
285Indicate that the value of t0 won't be used later. It is useful to
286force dead code elimination.
288* deposit_i32/i64 dest, t1, t2, pos, len
290Deposit T2 as a bitfield into T1, placing the result in DEST.
291The bitfield is described by POS/LEN, which are immediate values:
293 LEN - the length of the bitfield
294 POS - the position of the first bit, counting from the LSB
296For example, pos=8, len=4 indicates a 4-bit field at bit 8.
297This operation would be equivalent to
299 dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
302********* Conditional moves
304* setcond_i32/i64 cond, dest, t1, t2
306dest = (t1 cond t2)
308Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
310********* Type conversions
312* ext_i32_i64 t0, t1
313Convert t1 (32 bit) to t0 (64 bit) and does sign extension
315* extu_i32_i64 t0, t1
316Convert t1 (32 bit) to t0 (64 bit) and does zero extension
318* trunc_i64_i32 t0, t1
319Truncate t1 (64 bit) to t0 (32 bit)
321* concat_i32_i64 t0, t1, t2
322Construct t0 (64-bit) taking the low half from t1 (32 bit) and the high half
323from t2 (32 bit).
325* concat32_i64 t0, t1, t2
326Construct t0 (64-bit) taking the low half from t1 (64 bit) and the high half
327from t2 (64 bit).
331* ld_i32/i64 t0, t1, offset
332ld8s_i32/i64 t0, t1, offset
333ld8u_i32/i64 t0, t1, offset
334ld16s_i32/i64 t0, t1, offset
335ld16u_i32/i64 t0, t1, offset
336ld32s_i64 t0, t1, offset
337ld32u_i64 t0, t1, offset
339t0 = read(t1 + offset)
340Load 8, 16, 32 or 64 bits with or without sign extension from host memory.
341offset must be a constant.
343* st_i32/i64 t0, t1, offset
344st8_i32/i64 t0, t1, offset
345st16_i32/i64 t0, t1, offset
346st32_i64 t0, t1, offset
348write(t0, t1 + offset)
349Write 8, 16, 32 or 64 bits to host memory.
351********* 64-bit target on 32-bit host support
353The following opcodes are internal to TCG. Thus they are to be implemented by
35432-bit host code generators, but are not to be emitted by guest translators.
355They are emitted as needed by inline functions within "tcg-op.h".
357* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label
359Similar to brcond, except that the 64-bit values T0 and T1
360are formed from two 32-bit arguments.
362* add2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
363* sub2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
365Similar to add/sub, except that the 64-bit inputs T1 and T2 are
366formed from two 32-bit arguments, and the 64-bit output T0
367is returned in two 32-bit outputs.
369* mulu2_i32 t0_low, t0_high, t1, t2
371Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding
372the full 64-bit product T0. The later is returned in two 32-bit outputs.
374* setcond2_i32 cond, dest, t1_low, t1_high, t2_low, t2_high
376Similar to setcond, except that the 64-bit values T1 and T2 are
377formed from two 32-bit arguments. The result is a 32-bit value.
379********* QEMU specific operations
381* exit_tb t0
383Exit the current TB and return the value t0 (word type).
385* goto_tb index
387Exit the current TB and jump to the TB index 'index' (constant) if the
388current TB was linked to this TB. Otherwise execute the next
391* qemu_ld8u t0, t1, flags
392qemu_ld8s t0, t1, flags
393qemu_ld16u t0, t1, flags
394qemu_ld16s t0, t1, flags
395qemu_ld32 t0, t1, flags
396qemu_ld32u t0, t1, flags
397qemu_ld32s t0, t1, flags
398qemu_ld64 t0, t1, flags
400Load data at the QEMU CPU address t1 into t0. t1 has the QEMU CPU address
401type. 'flags' contains the QEMU memory index (selects user or kernel access)
404Note that "qemu_ld32" implies a 32-bit result, while "qemu_ld32u" and
405"qemu_ld32s" imply a 64-bit result appropriately extended from 32 bits.
407* qemu_st8 t0, t1, flags
408qemu_st16 t0, t1, flags
409qemu_st32 t0, t1, flags
410qemu_st64 t0, t1, flags
412Store the data t0 at the QEMU CPU Address t1. t1 has the QEMU CPU
413address type. 'flags' contains the QEMU memory index (selects user or
414kernel access) for example.
416Note 1: Some shortcuts are defined when the last operand is known to be
417a constant (e.g. addi for add, movi for mov).
419Note 2: When using TCG, the opcodes must never be generated directly
420as some of them may not be available as "real" opcodes. Always use the
425tcg-target.h contains the target specific definitions. tcg-target.c
426contains the target specific code.
430The target word size (TCG_TARGET_REG_BITS) is expected to be 32 bit or
43164 bit. It is expected that the pointer has the same size as the word.
433On a 32 bit target, all 64 bit operations are converted to 32 bits. A
434few specific operations must be implemented to allow it (see add2_i32,
437Floating point operations are not supported in this version. A
438previous incarnation of the code generator had full support of them,
439but it is better to concentrate on integer operations first.
441On a 64 bit target, no assumption is made in TCG about the storage of
442the 32 bit values in 64 bit registers.
446GCC like constraints are used to define the constraints of every
447instruction. Memory constraints are not supported in this
448version. Aliases are specified in the input operands as for GCC.
450The same register may be used for both an input and an output, even when
451they are not explicitly aliased. If an op expands to multiple target
452instructions then care must be taken to avoid clobbering input values.
453GCC style "early clobber" outputs are not currently supported.
455A target can define specific register or constant constraints. If an
456operation uses a constant input constraint which does not allow all
457constants, it must also accept registers in order to have a fallback.
459The movi_i32 and movi_i64 operations must accept any constants.
461The mov_i32 and mov_i64 operations must accept any registers of the
464The ld/st instructions must accept signed 32 bit constant offsets. It
465can be implemented by reserving a specific register to compute the
466address if the offset is too big.
468The ld/st instructions must accept any destination (ld) or source (st)
4714.3) Function call assumptions
473- The only supported types for parameters and return value are: 32 and
474 64 bit integers and pointer.
475- The stack grows downwards.
476- The first N parameters are passed in registers.
477- The next parameters are passed on the stack by storing them as words.
478- Some registers are clobbered during the call.
479- The function can return 0 or 1 value in registers. On a 32 bit
480 target, functions must be able to return 2 values in registers for
481 64 bit return type.
4835) Recommended coding rules for best performance
485- Use globals to represent the parts of the QEMU CPU state which are
486 often modified, e.g. the integer registers and the condition
487 codes. TCG will be able to use host registers to store them.
489- Avoid globals stored in fixed registers. They must be used only to
490 store the pointer to the CPU state and possibly to store a pointer
491 to a register window.
493- Use temporaries. Use local temporaries only when really needed,
494 e.g. when you need to use a value after a jump. Local temporaries
495 introduce a performance hit in the current TCG implementation: their
496 content is saved to memory at end of each basic block.
498- Free temporaries and local temporaries when they are no longer used
499 (tcg_temp_free). Since tcg_const_x() also creates a temporary, you
500 should free it after it is used. Freeing temporaries does not yield
501 a better generated code, but it reduces the memory usage of TCG and
502 the speed of the translation.
504- Don't hesitate to use helpers for complicated or seldom used target
505 instructions. There is little performance advantage in using TCG to
506 implement target instructions taking more than about twenty TCG
509- Use the 'discard' instruction if you know that TCG won't be able to
510 prove that a given global is "dead" at a given program point. The
511 x86 target uses it to improve the condition codes optimisation.