1 /*
2  *  PowerPC CPU initialization for qemu.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 /* A lot of PowerPC definition have been included here.
21  * Most of them are not usable for now but have been kept
22  * inside "#if defined(TODO) ... #endif" statements to make tests easier.
23  */
24 
25 #include "dis-asm.h"
26 #include "gdbstub.h"
27 
28 //#define PPC_DUMP_CPU
29 //#define PPC_DEBUG_SPR
30 //#define PPC_DUMP_SPR_ACCESSES
31 #if defined(CONFIG_USER_ONLY)
32 #define TODO_USER_ONLY 1
33 #endif
34 
35 struct ppc_def_t {
36     const char *name;
37     uint32_t pvr;
38     uint32_t svr;
39     uint64_t insns_flags;
40     uint64_t msr_mask;
41     powerpc_mmu_t   mmu_model;
42     powerpc_excp_t  excp_model;
43     powerpc_input_t bus_model;
44     uint32_t flags;
45     int bfd_mach;
46     void (*init_proc)(CPUPPCState *env);
47     int  (*check_pow)(CPUPPCState *env);
48 };
49 
50 /* For user-mode emulation, we don't emulate any IRQ controller */
51 #if defined(CONFIG_USER_ONLY)
52 #define PPC_IRQ_INIT_FN(name)                                                 \
53 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
54 {                                                                             \
55 }
56 #else
57 #define PPC_IRQ_INIT_FN(name)                                                 \
58 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
59 #endif
60 
61 PPC_IRQ_INIT_FN(40x);
62 PPC_IRQ_INIT_FN(6xx);
63 PPC_IRQ_INIT_FN(970);
64 PPC_IRQ_INIT_FN(e500);
65 
66 /* Generic callbacks:
67  * do nothing but store/retrieve spr value
68  */
spr_read_generic(void * opaque,int gprn,int sprn)69 static void spr_read_generic (void *opaque, int gprn, int sprn)
70 {
71     gen_load_spr(cpu_gpr[gprn], sprn);
72 #ifdef PPC_DUMP_SPR_ACCESSES
73     {
74         TCGv t0 = tcg_const_i32(sprn);
75         gen_helper_load_dump_spr(t0);
76         tcg_temp_free_i32(t0);
77     }
78 #endif
79 }
80 
spr_write_generic(void * opaque,int sprn,int gprn)81 static void spr_write_generic (void *opaque, int sprn, int gprn)
82 {
83     gen_store_spr(sprn, cpu_gpr[gprn]);
84 #ifdef PPC_DUMP_SPR_ACCESSES
85     {
86         TCGv t0 = tcg_const_i32(sprn);
87         gen_helper_store_dump_spr(t0);
88         tcg_temp_free_i32(t0);
89     }
90 #endif
91 }
92 
93 #if !defined(CONFIG_USER_ONLY)
spr_write_clear(void * opaque,int sprn,int gprn)94 static void spr_write_clear (void *opaque, int sprn, int gprn)
95 {
96     TCGv t0 = tcg_temp_new();
97     TCGv t1 = tcg_temp_new();
98     gen_load_spr(t0, sprn);
99     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
100     tcg_gen_and_tl(t0, t0, t1);
101     gen_store_spr(sprn, t0);
102     tcg_temp_free(t0);
103     tcg_temp_free(t1);
104 }
105 #endif
106 
107 /* SPR common to all PowerPC */
108 /* XER */
spr_read_xer(void * opaque,int gprn,int sprn)109 static void spr_read_xer (void *opaque, int gprn, int sprn)
110 {
111     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
112 }
113 
spr_write_xer(void * opaque,int sprn,int gprn)114 static void spr_write_xer (void *opaque, int sprn, int gprn)
115 {
116     tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
117 }
118 
119 /* LR */
spr_read_lr(void * opaque,int gprn,int sprn)120 static void spr_read_lr (void *opaque, int gprn, int sprn)
121 {
122     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
123 }
124 
spr_write_lr(void * opaque,int sprn,int gprn)125 static void spr_write_lr (void *opaque, int sprn, int gprn)
126 {
127     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
128 }
129 
130 /* CTR */
spr_read_ctr(void * opaque,int gprn,int sprn)131 static void spr_read_ctr (void *opaque, int gprn, int sprn)
132 {
133     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
134 }
135 
spr_write_ctr(void * opaque,int sprn,int gprn)136 static void spr_write_ctr (void *opaque, int sprn, int gprn)
137 {
138     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
139 }
140 
141 /* User read access to SPR */
142 /* USPRx */
143 /* UMMCRx */
144 /* UPMCx */
145 /* USIA */
146 /* UDECR */
spr_read_ureg(void * opaque,int gprn,int sprn)147 static void spr_read_ureg (void *opaque, int gprn, int sprn)
148 {
149     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
150 }
151 
152 /* SPR common to all non-embedded PowerPC */
153 /* DECR */
154 #if !defined(CONFIG_USER_ONLY)
spr_read_decr(void * opaque,int gprn,int sprn)155 static void spr_read_decr (void *opaque, int gprn, int sprn)
156 {
157     gen_helper_load_decr(cpu_gpr[gprn]);
158 }
159 
spr_write_decr(void * opaque,int sprn,int gprn)160 static void spr_write_decr (void *opaque, int sprn, int gprn)
161 {
162     gen_helper_store_decr(cpu_gpr[gprn]);
163 }
164 #endif
165 
166 /* SPR common to all non-embedded PowerPC, except 601 */
167 /* Time base */
spr_read_tbl(void * opaque,int gprn,int sprn)168 static void spr_read_tbl (void *opaque, int gprn, int sprn)
169 {
170     gen_helper_load_tbl(cpu_gpr[gprn]);
171 }
172 
spr_read_tbu(void * opaque,int gprn,int sprn)173 static void spr_read_tbu (void *opaque, int gprn, int sprn)
174 {
175     gen_helper_load_tbu(cpu_gpr[gprn]);
176 }
177 
178 __attribute__ (( unused ))
spr_read_atbl(void * opaque,int gprn,int sprn)179 static void spr_read_atbl (void *opaque, int gprn, int sprn)
180 {
181     gen_helper_load_atbl(cpu_gpr[gprn]);
182 }
183 
184 __attribute__ (( unused ))
spr_read_atbu(void * opaque,int gprn,int sprn)185 static void spr_read_atbu (void *opaque, int gprn, int sprn)
186 {
187     gen_helper_load_atbu(cpu_gpr[gprn]);
188 }
189 
190 #if !defined(CONFIG_USER_ONLY)
spr_write_tbl(void * opaque,int sprn,int gprn)191 static void spr_write_tbl (void *opaque, int sprn, int gprn)
192 {
193     gen_helper_store_tbl(cpu_gpr[gprn]);
194 }
195 
spr_write_tbu(void * opaque,int sprn,int gprn)196 static void spr_write_tbu (void *opaque, int sprn, int gprn)
197 {
198     gen_helper_store_tbu(cpu_gpr[gprn]);
199 }
200 
201 __attribute__ (( unused ))
spr_write_atbl(void * opaque,int sprn,int gprn)202 static void spr_write_atbl (void *opaque, int sprn, int gprn)
203 {
204     gen_helper_store_atbl(cpu_gpr[gprn]);
205 }
206 
207 __attribute__ (( unused ))
spr_write_atbu(void * opaque,int sprn,int gprn)208 static void spr_write_atbu (void *opaque, int sprn, int gprn)
209 {
210     gen_helper_store_atbu(cpu_gpr[gprn]);
211 }
212 #endif
213 
214 #if !defined(CONFIG_USER_ONLY)
215 /* IBAT0U...IBAT0U */
216 /* IBAT0L...IBAT7L */
spr_read_ibat(void * opaque,int gprn,int sprn)217 static void spr_read_ibat (void *opaque, int gprn, int sprn)
218 {
219     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
220 }
221 
spr_read_ibat_h(void * opaque,int gprn,int sprn)222 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
223 {
224     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
225 }
226 
spr_write_ibatu(void * opaque,int sprn,int gprn)227 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
228 {
229     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
230     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
231     tcg_temp_free_i32(t0);
232 }
233 
spr_write_ibatu_h(void * opaque,int sprn,int gprn)234 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
235 {
236     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
237     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
238     tcg_temp_free_i32(t0);
239 }
240 
spr_write_ibatl(void * opaque,int sprn,int gprn)241 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
242 {
243     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
244     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
245     tcg_temp_free_i32(t0);
246 }
247 
spr_write_ibatl_h(void * opaque,int sprn,int gprn)248 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
249 {
250     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
251     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
252     tcg_temp_free_i32(t0);
253 }
254 
255 /* DBAT0U...DBAT7U */
256 /* DBAT0L...DBAT7L */
spr_read_dbat(void * opaque,int gprn,int sprn)257 static void spr_read_dbat (void *opaque, int gprn, int sprn)
258 {
259     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
260 }
261 
spr_read_dbat_h(void * opaque,int gprn,int sprn)262 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
263 {
264     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
265 }
266 
spr_write_dbatu(void * opaque,int sprn,int gprn)267 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
268 {
269     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
270     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
271     tcg_temp_free_i32(t0);
272 }
273 
spr_write_dbatu_h(void * opaque,int sprn,int gprn)274 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
275 {
276     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
277     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
278     tcg_temp_free_i32(t0);
279 }
280 
spr_write_dbatl(void * opaque,int sprn,int gprn)281 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
282 {
283     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
284     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
285     tcg_temp_free_i32(t0);
286 }
287 
spr_write_dbatl_h(void * opaque,int sprn,int gprn)288 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
289 {
290     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
291     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
292     tcg_temp_free_i32(t0);
293 }
294 
295 /* SDR1 */
spr_read_sdr1(void * opaque,int gprn,int sprn)296 static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
297 {
298     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
299 }
300 
spr_write_sdr1(void * opaque,int sprn,int gprn)301 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
302 {
303     gen_helper_store_sdr1(cpu_gpr[gprn]);
304 }
305 
306 /* 64 bits PowerPC specific SPRs */
307 /* ASR */
308 #if defined(TARGET_PPC64)
spr_read_hior(void * opaque,int gprn,int sprn)309 static void spr_read_hior (void *opaque, int gprn, int sprn)
310 {
311     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
312 }
313 
spr_write_hior(void * opaque,int sprn,int gprn)314 static void spr_write_hior (void *opaque, int sprn, int gprn)
315 {
316     TCGv t0 = tcg_temp_new();
317     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
318     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
319     tcg_temp_free(t0);
320 }
321 
spr_read_asr(void * opaque,int gprn,int sprn)322 static void spr_read_asr (void *opaque, int gprn, int sprn)
323 {
324     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
325 }
326 
spr_write_asr(void * opaque,int sprn,int gprn)327 static void spr_write_asr (void *opaque, int sprn, int gprn)
328 {
329     gen_helper_store_asr(cpu_gpr[gprn]);
330 }
331 #endif
332 #endif
333 
334 /* PowerPC 601 specific registers */
335 /* RTC */
spr_read_601_rtcl(void * opaque,int gprn,int sprn)336 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
337 {
338     gen_helper_load_601_rtcl(cpu_gpr[gprn]);
339 }
340 
spr_read_601_rtcu(void * opaque,int gprn,int sprn)341 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
342 {
343     gen_helper_load_601_rtcu(cpu_gpr[gprn]);
344 }
345 
346 #if !defined(CONFIG_USER_ONLY)
spr_write_601_rtcu(void * opaque,int sprn,int gprn)347 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
348 {
349     gen_helper_store_601_rtcu(cpu_gpr[gprn]);
350 }
351 
spr_write_601_rtcl(void * opaque,int sprn,int gprn)352 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
353 {
354     gen_helper_store_601_rtcl(cpu_gpr[gprn]);
355 }
356 
spr_write_hid0_601(void * opaque,int sprn,int gprn)357 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
358 {
359     DisasContext *ctx = opaque;
360 
361     gen_helper_store_hid0_601(cpu_gpr[gprn]);
362     /* Must stop the translation as endianness may have changed */
363     gen_stop_exception(ctx);
364 }
365 #endif
366 
367 /* Unified bats */
368 #if !defined(CONFIG_USER_ONLY)
spr_read_601_ubat(void * opaque,int gprn,int sprn)369 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
370 {
371     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
372 }
373 
spr_write_601_ubatu(void * opaque,int sprn,int gprn)374 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
375 {
376     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
377     gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
378     tcg_temp_free_i32(t0);
379 }
380 
spr_write_601_ubatl(void * opaque,int sprn,int gprn)381 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
382 {
383     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
384     gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
385     tcg_temp_free_i32(t0);
386 }
387 #endif
388 
389 /* PowerPC 40x specific registers */
390 #if !defined(CONFIG_USER_ONLY)
spr_read_40x_pit(void * opaque,int gprn,int sprn)391 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
392 {
393     gen_helper_load_40x_pit(cpu_gpr[gprn]);
394 }
395 
spr_write_40x_pit(void * opaque,int sprn,int gprn)396 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
397 {
398     gen_helper_store_40x_pit(cpu_gpr[gprn]);
399 }
400 
spr_write_40x_dbcr0(void * opaque,int sprn,int gprn)401 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
402 {
403     DisasContext *ctx = opaque;
404 
405     gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
406     /* We must stop translation as we may have rebooted */
407     gen_stop_exception(ctx);
408 }
409 
spr_write_40x_sler(void * opaque,int sprn,int gprn)410 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
411 {
412     gen_helper_store_40x_sler(cpu_gpr[gprn]);
413 }
414 
spr_write_booke_tcr(void * opaque,int sprn,int gprn)415 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
416 {
417     gen_helper_store_booke_tcr(cpu_gpr[gprn]);
418 }
419 
spr_write_booke_tsr(void * opaque,int sprn,int gprn)420 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
421 {
422     gen_helper_store_booke_tsr(cpu_gpr[gprn]);
423 }
424 #endif
425 
426 /* PowerPC 403 specific registers */
427 /* PBL1 / PBU1 / PBL2 / PBU2 */
428 #if !defined(CONFIG_USER_ONLY)
spr_read_403_pbr(void * opaque,int gprn,int sprn)429 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
430 {
431     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
432 }
433 
spr_write_403_pbr(void * opaque,int sprn,int gprn)434 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
435 {
436     TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
437     gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
438     tcg_temp_free_i32(t0);
439 }
440 
spr_write_pir(void * opaque,int sprn,int gprn)441 static void spr_write_pir (void *opaque, int sprn, int gprn)
442 {
443     TCGv t0 = tcg_temp_new();
444     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
445     gen_store_spr(SPR_PIR, t0);
446     tcg_temp_free(t0);
447 }
448 #endif
449 
450 /* SPE specific registers */
spr_read_spefscr(void * opaque,int gprn,int sprn)451 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
452 {
453     TCGv_i32 t0 = tcg_temp_new_i32();
454     tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
455     tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
456     tcg_temp_free_i32(t0);
457 }
458 
spr_write_spefscr(void * opaque,int sprn,int gprn)459 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
460 {
461     TCGv_i32 t0 = tcg_temp_new_i32();
462     tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
463     tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
464     tcg_temp_free_i32(t0);
465 }
466 
467 #if !defined(CONFIG_USER_ONLY)
468 /* Callback used to write the exception vector base */
spr_write_excp_prefix(void * opaque,int sprn,int gprn)469 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
470 {
471     TCGv t0 = tcg_temp_new();
472     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
473     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
474     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
475     gen_store_spr(sprn, t0);
476     tcg_temp_free(t0);
477 }
478 
spr_write_excp_vector(void * opaque,int sprn,int gprn)479 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
480 {
481     DisasContext *ctx = opaque;
482 
483     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
484         TCGv t0 = tcg_temp_new();
485         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
486         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
487         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
488         gen_store_spr(sprn, t0);
489         tcg_temp_free(t0);
490     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
491         TCGv t0 = tcg_temp_new();
492         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
493         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
494         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
495         gen_store_spr(sprn, t0);
496         tcg_temp_free(t0);
497     } else {
498         printf("Trying to write an unknown exception vector %d %03x\n",
499                sprn, sprn);
500         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
501     }
502 }
503 #endif
504 
vscr_init(CPUPPCState * env,uint32_t val)505 static inline void vscr_init (CPUPPCState *env, uint32_t val)
506 {
507     env->vscr = val;
508     /* Altivec always uses round-to-nearest */
509     set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
510     set_flush_to_zero(vscr_nj, &env->vec_status);
511 }
512 
513 #if defined(CONFIG_USER_ONLY)
514 #define spr_register(env, num, name, uea_read, uea_write,                     \
515                      oea_read, oea_write, initial_value)                      \
516 do {                                                                          \
517      _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
518 } while (0)
_spr_register(CPUPPCState * env,int num,const char * name,void (* uea_read)(void * opaque,int gprn,int sprn),void (* uea_write)(void * opaque,int sprn,int gprn),target_ulong initial_value)519 static inline void _spr_register (CPUPPCState *env, int num,
520                                   const char *name,
521                                   void (*uea_read)(void *opaque, int gprn, int sprn),
522                                   void (*uea_write)(void *opaque, int sprn, int gprn),
523                                   target_ulong initial_value)
524 #else
525 static inline void spr_register (CPUPPCState *env, int num,
526                                  const char *name,
527                                  void (*uea_read)(void *opaque, int gprn, int sprn),
528                                  void (*uea_write)(void *opaque, int sprn, int gprn),
529                                  void (*oea_read)(void *opaque, int gprn, int sprn),
530                                  void (*oea_write)(void *opaque, int sprn, int gprn),
531                                  target_ulong initial_value)
532 #endif
533 {
534     ppc_spr_t *spr;
535 
536     spr = &env->spr_cb[num];
537     if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
538 #if !defined(CONFIG_USER_ONLY)
539         spr->oea_read != NULL || spr->oea_write != NULL ||
540 #endif
541         spr->uea_read != NULL || spr->uea_write != NULL) {
542         printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
543         exit(1);
544     }
545 #if defined(PPC_DEBUG_SPR)
546     printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
547            name, initial_value);
548 #endif
549     spr->name = name;
550     spr->uea_read = uea_read;
551     spr->uea_write = uea_write;
552 #if !defined(CONFIG_USER_ONLY)
553     spr->oea_read = oea_read;
554     spr->oea_write = oea_write;
555 #endif
556     env->spr[num] = initial_value;
557 }
558 
559 /* Generic PowerPC SPRs */
gen_spr_generic(CPUPPCState * env)560 static void gen_spr_generic (CPUPPCState *env)
561 {
562     /* Integer processing */
563     spr_register(env, SPR_XER, "XER",
564                  &spr_read_xer, &spr_write_xer,
565                  &spr_read_xer, &spr_write_xer,
566                  0x00000000);
567     /* Branch contol */
568     spr_register(env, SPR_LR, "LR",
569                  &spr_read_lr, &spr_write_lr,
570                  &spr_read_lr, &spr_write_lr,
571                  0x00000000);
572     spr_register(env, SPR_CTR, "CTR",
573                  &spr_read_ctr, &spr_write_ctr,
574                  &spr_read_ctr, &spr_write_ctr,
575                  0x00000000);
576     /* Interrupt processing */
577     spr_register(env, SPR_SRR0, "SRR0",
578                  SPR_NOACCESS, SPR_NOACCESS,
579                  &spr_read_generic, &spr_write_generic,
580                  0x00000000);
581     spr_register(env, SPR_SRR1, "SRR1",
582                  SPR_NOACCESS, SPR_NOACCESS,
583                  &spr_read_generic, &spr_write_generic,
584                  0x00000000);
585     /* Processor control */
586     spr_register(env, SPR_SPRG0, "SPRG0",
587                  SPR_NOACCESS, SPR_NOACCESS,
588                  &spr_read_generic, &spr_write_generic,
589                  0x00000000);
590     spr_register(env, SPR_SPRG1, "SPRG1",
591                  SPR_NOACCESS, SPR_NOACCESS,
592                  &spr_read_generic, &spr_write_generic,
593                  0x00000000);
594     spr_register(env, SPR_SPRG2, "SPRG2",
595                  SPR_NOACCESS, SPR_NOACCESS,
596                  &spr_read_generic, &spr_write_generic,
597                  0x00000000);
598     spr_register(env, SPR_SPRG3, "SPRG3",
599                  SPR_NOACCESS, SPR_NOACCESS,
600                  &spr_read_generic, &spr_write_generic,
601                  0x00000000);
602 }
603 
604 /* SPR common to all non-embedded PowerPC, including 601 */
gen_spr_ne_601(CPUPPCState * env)605 static void gen_spr_ne_601 (CPUPPCState *env)
606 {
607     /* Exception processing */
608     spr_register(env, SPR_DSISR, "DSISR",
609                  SPR_NOACCESS, SPR_NOACCESS,
610                  &spr_read_generic, &spr_write_generic,
611                  0x00000000);
612     spr_register(env, SPR_DAR, "DAR",
613                  SPR_NOACCESS, SPR_NOACCESS,
614                  &spr_read_generic, &spr_write_generic,
615                  0x00000000);
616     /* Timer */
617     spr_register(env, SPR_DECR, "DECR",
618                  SPR_NOACCESS, SPR_NOACCESS,
619                  &spr_read_decr, &spr_write_decr,
620                  0x00000000);
621     /* Memory management */
622     spr_register(env, SPR_SDR1, "SDR1",
623                  SPR_NOACCESS, SPR_NOACCESS,
624                  &spr_read_sdr1, &spr_write_sdr1,
625                  0x00000000);
626 }
627 
628 /* BATs 0-3 */
gen_low_BATs(CPUPPCState * env)629 static void gen_low_BATs (CPUPPCState *env)
630 {
631 #if !defined(CONFIG_USER_ONLY)
632     spr_register(env, SPR_IBAT0U, "IBAT0U",
633                  SPR_NOACCESS, SPR_NOACCESS,
634                  &spr_read_ibat, &spr_write_ibatu,
635                  0x00000000);
636     spr_register(env, SPR_IBAT0L, "IBAT0L",
637                  SPR_NOACCESS, SPR_NOACCESS,
638                  &spr_read_ibat, &spr_write_ibatl,
639                  0x00000000);
640     spr_register(env, SPR_IBAT1U, "IBAT1U",
641                  SPR_NOACCESS, SPR_NOACCESS,
642                  &spr_read_ibat, &spr_write_ibatu,
643                  0x00000000);
644     spr_register(env, SPR_IBAT1L, "IBAT1L",
645                  SPR_NOACCESS, SPR_NOACCESS,
646                  &spr_read_ibat, &spr_write_ibatl,
647                  0x00000000);
648     spr_register(env, SPR_IBAT2U, "IBAT2U",
649                  SPR_NOACCESS, SPR_NOACCESS,
650                  &spr_read_ibat, &spr_write_ibatu,
651                  0x00000000);
652     spr_register(env, SPR_IBAT2L, "IBAT2L",
653                  SPR_NOACCESS, SPR_NOACCESS,
654                  &spr_read_ibat, &spr_write_ibatl,
655                  0x00000000);
656     spr_register(env, SPR_IBAT3U, "IBAT3U",
657                  SPR_NOACCESS, SPR_NOACCESS,
658                  &spr_read_ibat, &spr_write_ibatu,
659                  0x00000000);
660     spr_register(env, SPR_IBAT3L, "IBAT3L",
661                  SPR_NOACCESS, SPR_NOACCESS,
662                  &spr_read_ibat, &spr_write_ibatl,
663                  0x00000000);
664     spr_register(env, SPR_DBAT0U, "DBAT0U",
665                  SPR_NOACCESS, SPR_NOACCESS,
666                  &spr_read_dbat, &spr_write_dbatu,
667                  0x00000000);
668     spr_register(env, SPR_DBAT0L, "DBAT0L",
669                  SPR_NOACCESS, SPR_NOACCESS,
670                  &spr_read_dbat, &spr_write_dbatl,
671                  0x00000000);
672     spr_register(env, SPR_DBAT1U, "DBAT1U",
673                  SPR_NOACCESS, SPR_NOACCESS,
674                  &spr_read_dbat, &spr_write_dbatu,
675                  0x00000000);
676     spr_register(env, SPR_DBAT1L, "DBAT1L",
677                  SPR_NOACCESS, SPR_NOACCESS,
678                  &spr_read_dbat, &spr_write_dbatl,
679                  0x00000000);
680     spr_register(env, SPR_DBAT2U, "DBAT2U",
681                  SPR_NOACCESS, SPR_NOACCESS,
682                  &spr_read_dbat, &spr_write_dbatu,
683                  0x00000000);
684     spr_register(env, SPR_DBAT2L, "DBAT2L",
685                  SPR_NOACCESS, SPR_NOACCESS,
686                  &spr_read_dbat, &spr_write_dbatl,
687                  0x00000000);
688     spr_register(env, SPR_DBAT3U, "DBAT3U",
689                  SPR_NOACCESS, SPR_NOACCESS,
690                  &spr_read_dbat, &spr_write_dbatu,
691                  0x00000000);
692     spr_register(env, SPR_DBAT3L, "DBAT3L",
693                  SPR_NOACCESS, SPR_NOACCESS,
694                  &spr_read_dbat, &spr_write_dbatl,
695                  0x00000000);
696     env->nb_BATs += 4;
697 #endif
698 }
699 
700 /* BATs 4-7 */
gen_high_BATs(CPUPPCState * env)701 static void gen_high_BATs (CPUPPCState *env)
702 {
703 #if !defined(CONFIG_USER_ONLY)
704     spr_register(env, SPR_IBAT4U, "IBAT4U",
705                  SPR_NOACCESS, SPR_NOACCESS,
706                  &spr_read_ibat_h, &spr_write_ibatu_h,
707                  0x00000000);
708     spr_register(env, SPR_IBAT4L, "IBAT4L",
709                  SPR_NOACCESS, SPR_NOACCESS,
710                  &spr_read_ibat_h, &spr_write_ibatl_h,
711                  0x00000000);
712     spr_register(env, SPR_IBAT5U, "IBAT5U",
713                  SPR_NOACCESS, SPR_NOACCESS,
714                  &spr_read_ibat_h, &spr_write_ibatu_h,
715                  0x00000000);
716     spr_register(env, SPR_IBAT5L, "IBAT5L",
717                  SPR_NOACCESS, SPR_NOACCESS,
718                  &spr_read_ibat_h, &spr_write_ibatl_h,
719                  0x00000000);
720     spr_register(env, SPR_IBAT6U, "IBAT6U",
721                  SPR_NOACCESS, SPR_NOACCESS,
722                  &spr_read_ibat_h, &spr_write_ibatu_h,
723                  0x00000000);
724     spr_register(env, SPR_IBAT6L, "IBAT6L",
725                  SPR_NOACCESS, SPR_NOACCESS,
726                  &spr_read_ibat_h, &spr_write_ibatl_h,
727                  0x00000000);
728     spr_register(env, SPR_IBAT7U, "IBAT7U",
729                  SPR_NOACCESS, SPR_NOACCESS,
730                  &spr_read_ibat_h, &spr_write_ibatu_h,
731                  0x00000000);
732     spr_register(env, SPR_IBAT7L, "IBAT7L",
733                  SPR_NOACCESS, SPR_NOACCESS,
734                  &spr_read_ibat_h, &spr_write_ibatl_h,
735                  0x00000000);
736     spr_register(env, SPR_DBAT4U, "DBAT4U",
737                  SPR_NOACCESS, SPR_NOACCESS,
738                  &spr_read_dbat_h, &spr_write_dbatu_h,
739                  0x00000000);
740     spr_register(env, SPR_DBAT4L, "DBAT4L",
741                  SPR_NOACCESS, SPR_NOACCESS,
742                  &spr_read_dbat_h, &spr_write_dbatl_h,
743                  0x00000000);
744     spr_register(env, SPR_DBAT5U, "DBAT5U",
745                  SPR_NOACCESS, SPR_NOACCESS,
746                  &spr_read_dbat_h, &spr_write_dbatu_h,
747                  0x00000000);
748     spr_register(env, SPR_DBAT5L, "DBAT5L",
749                  SPR_NOACCESS, SPR_NOACCESS,
750                  &spr_read_dbat_h, &spr_write_dbatl_h,
751                  0x00000000);
752     spr_register(env, SPR_DBAT6U, "DBAT6U",
753                  SPR_NOACCESS, SPR_NOACCESS,
754                  &spr_read_dbat_h, &spr_write_dbatu_h,
755                  0x00000000);
756     spr_register(env, SPR_DBAT6L, "DBAT6L",
757                  SPR_NOACCESS, SPR_NOACCESS,
758                  &spr_read_dbat_h, &spr_write_dbatl_h,
759                  0x00000000);
760     spr_register(env, SPR_DBAT7U, "DBAT7U",
761                  SPR_NOACCESS, SPR_NOACCESS,
762                  &spr_read_dbat_h, &spr_write_dbatu_h,
763                  0x00000000);
764     spr_register(env, SPR_DBAT7L, "DBAT7L",
765                  SPR_NOACCESS, SPR_NOACCESS,
766                  &spr_read_dbat_h, &spr_write_dbatl_h,
767                  0x00000000);
768     env->nb_BATs += 4;
769 #endif
770 }
771 
772 /* Generic PowerPC time base */
gen_tbl(CPUPPCState * env)773 static void gen_tbl (CPUPPCState *env)
774 {
775     spr_register(env, SPR_VTBL,  "TBL",
776                  &spr_read_tbl, SPR_NOACCESS,
777                  &spr_read_tbl, SPR_NOACCESS,
778                  0x00000000);
779     spr_register(env, SPR_TBL,   "TBL",
780                  &spr_read_tbl, SPR_NOACCESS,
781                  &spr_read_tbl, &spr_write_tbl,
782                  0x00000000);
783     spr_register(env, SPR_VTBU,  "TBU",
784                  &spr_read_tbu, SPR_NOACCESS,
785                  &spr_read_tbu, SPR_NOACCESS,
786                  0x00000000);
787     spr_register(env, SPR_TBU,   "TBU",
788                  &spr_read_tbu, SPR_NOACCESS,
789                  &spr_read_tbu, &spr_write_tbu,
790                  0x00000000);
791 }
792 
793 /* Softare table search registers */
gen_6xx_7xx_soft_tlb(CPUPPCState * env,int nb_tlbs,int nb_ways)794 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
795 {
796 #if !defined(CONFIG_USER_ONLY)
797     env->nb_tlb = nb_tlbs;
798     env->nb_ways = nb_ways;
799     env->id_tlbs = 1;
800     spr_register(env, SPR_DMISS, "DMISS",
801                  SPR_NOACCESS, SPR_NOACCESS,
802                  &spr_read_generic, SPR_NOACCESS,
803                  0x00000000);
804     spr_register(env, SPR_DCMP, "DCMP",
805                  SPR_NOACCESS, SPR_NOACCESS,
806                  &spr_read_generic, SPR_NOACCESS,
807                  0x00000000);
808     spr_register(env, SPR_HASH1, "HASH1",
809                  SPR_NOACCESS, SPR_NOACCESS,
810                  &spr_read_generic, SPR_NOACCESS,
811                  0x00000000);
812     spr_register(env, SPR_HASH2, "HASH2",
813                  SPR_NOACCESS, SPR_NOACCESS,
814                  &spr_read_generic, SPR_NOACCESS,
815                  0x00000000);
816     spr_register(env, SPR_IMISS, "IMISS",
817                  SPR_NOACCESS, SPR_NOACCESS,
818                  &spr_read_generic, SPR_NOACCESS,
819                  0x00000000);
820     spr_register(env, SPR_ICMP, "ICMP",
821                  SPR_NOACCESS, SPR_NOACCESS,
822                  &spr_read_generic, SPR_NOACCESS,
823                  0x00000000);
824     spr_register(env, SPR_RPA, "RPA",
825                  SPR_NOACCESS, SPR_NOACCESS,
826                  &spr_read_generic, &spr_write_generic,
827                  0x00000000);
828 #endif
829 }
830 
831 /* SPR common to MPC755 and G2 */
gen_spr_G2_755(CPUPPCState * env)832 static void gen_spr_G2_755 (CPUPPCState *env)
833 {
834     /* SGPRs */
835     spr_register(env, SPR_SPRG4, "SPRG4",
836                  SPR_NOACCESS, SPR_NOACCESS,
837                  &spr_read_generic, &spr_write_generic,
838                  0x00000000);
839     spr_register(env, SPR_SPRG5, "SPRG5",
840                  SPR_NOACCESS, SPR_NOACCESS,
841                  &spr_read_generic, &spr_write_generic,
842                  0x00000000);
843     spr_register(env, SPR_SPRG6, "SPRG6",
844                  SPR_NOACCESS, SPR_NOACCESS,
845                  &spr_read_generic, &spr_write_generic,
846                  0x00000000);
847     spr_register(env, SPR_SPRG7, "SPRG7",
848                  SPR_NOACCESS, SPR_NOACCESS,
849                  &spr_read_generic, &spr_write_generic,
850                  0x00000000);
851 }
852 
853 /* SPR common to all 7xx PowerPC implementations */
gen_spr_7xx(CPUPPCState * env)854 static void gen_spr_7xx (CPUPPCState *env)
855 {
856     /* Breakpoints */
857     /* XXX : not implemented */
858     spr_register(env, SPR_DABR, "DABR",
859                  SPR_NOACCESS, SPR_NOACCESS,
860                  &spr_read_generic, &spr_write_generic,
861                  0x00000000);
862     /* XXX : not implemented */
863     spr_register(env, SPR_IABR, "IABR",
864                  SPR_NOACCESS, SPR_NOACCESS,
865                  &spr_read_generic, &spr_write_generic,
866                  0x00000000);
867     /* Cache management */
868     /* XXX : not implemented */
869     spr_register(env, SPR_ICTC, "ICTC",
870                  SPR_NOACCESS, SPR_NOACCESS,
871                  &spr_read_generic, &spr_write_generic,
872                  0x00000000);
873     /* Performance monitors */
874     /* XXX : not implemented */
875     spr_register(env, SPR_MMCR0, "MMCR0",
876                  SPR_NOACCESS, SPR_NOACCESS,
877                  &spr_read_generic, &spr_write_generic,
878                  0x00000000);
879     /* XXX : not implemented */
880     spr_register(env, SPR_MMCR1, "MMCR1",
881                  SPR_NOACCESS, SPR_NOACCESS,
882                  &spr_read_generic, &spr_write_generic,
883                  0x00000000);
884     /* XXX : not implemented */
885     spr_register(env, SPR_PMC1, "PMC1",
886                  SPR_NOACCESS, SPR_NOACCESS,
887                  &spr_read_generic, &spr_write_generic,
888                  0x00000000);
889     /* XXX : not implemented */
890     spr_register(env, SPR_PMC2, "PMC2",
891                  SPR_NOACCESS, SPR_NOACCESS,
892                  &spr_read_generic, &spr_write_generic,
893                  0x00000000);
894     /* XXX : not implemented */
895     spr_register(env, SPR_PMC3, "PMC3",
896                  SPR_NOACCESS, SPR_NOACCESS,
897                  &spr_read_generic, &spr_write_generic,
898                  0x00000000);
899     /* XXX : not implemented */
900     spr_register(env, SPR_PMC4, "PMC4",
901                  SPR_NOACCESS, SPR_NOACCESS,
902                  &spr_read_generic, &spr_write_generic,
903                  0x00000000);
904     /* XXX : not implemented */
905     spr_register(env, SPR_SIAR, "SIAR",
906                  SPR_NOACCESS, SPR_NOACCESS,
907                  &spr_read_generic, SPR_NOACCESS,
908                  0x00000000);
909     /* XXX : not implemented */
910     spr_register(env, SPR_UMMCR0, "UMMCR0",
911                  &spr_read_ureg, SPR_NOACCESS,
912                  &spr_read_ureg, SPR_NOACCESS,
913                  0x00000000);
914     /* XXX : not implemented */
915     spr_register(env, SPR_UMMCR1, "UMMCR1",
916                  &spr_read_ureg, SPR_NOACCESS,
917                  &spr_read_ureg, SPR_NOACCESS,
918                  0x00000000);
919     /* XXX : not implemented */
920     spr_register(env, SPR_UPMC1, "UPMC1",
921                  &spr_read_ureg, SPR_NOACCESS,
922                  &spr_read_ureg, SPR_NOACCESS,
923                  0x00000000);
924     /* XXX : not implemented */
925     spr_register(env, SPR_UPMC2, "UPMC2",
926                  &spr_read_ureg, SPR_NOACCESS,
927                  &spr_read_ureg, SPR_NOACCESS,
928                  0x00000000);
929     /* XXX : not implemented */
930     spr_register(env, SPR_UPMC3, "UPMC3",
931                  &spr_read_ureg, SPR_NOACCESS,
932                  &spr_read_ureg, SPR_NOACCESS,
933                  0x00000000);
934     /* XXX : not implemented */
935     spr_register(env, SPR_UPMC4, "UPMC4",
936                  &spr_read_ureg, SPR_NOACCESS,
937                  &spr_read_ureg, SPR_NOACCESS,
938                  0x00000000);
939     /* XXX : not implemented */
940     spr_register(env, SPR_USIAR, "USIAR",
941                  &spr_read_ureg, SPR_NOACCESS,
942                  &spr_read_ureg, SPR_NOACCESS,
943                  0x00000000);
944     /* External access control */
945     /* XXX : not implemented */
946     spr_register(env, SPR_EAR, "EAR",
947                  SPR_NOACCESS, SPR_NOACCESS,
948                  &spr_read_generic, &spr_write_generic,
949                  0x00000000);
950 }
951 
gen_spr_thrm(CPUPPCState * env)952 static void gen_spr_thrm (CPUPPCState *env)
953 {
954     /* Thermal management */
955     /* XXX : not implemented */
956     spr_register(env, SPR_THRM1, "THRM1",
957                  SPR_NOACCESS, SPR_NOACCESS,
958                  &spr_read_generic, &spr_write_generic,
959                  0x00000000);
960     /* XXX : not implemented */
961     spr_register(env, SPR_THRM2, "THRM2",
962                  SPR_NOACCESS, SPR_NOACCESS,
963                  &spr_read_generic, &spr_write_generic,
964                  0x00000000);
965     /* XXX : not implemented */
966     spr_register(env, SPR_THRM3, "THRM3",
967                  SPR_NOACCESS, SPR_NOACCESS,
968                  &spr_read_generic, &spr_write_generic,
969                  0x00000000);
970 }
971 
972 /* SPR specific to PowerPC 604 implementation */
gen_spr_604(CPUPPCState * env)973 static void gen_spr_604 (CPUPPCState *env)
974 {
975     /* Processor identification */
976     spr_register(env, SPR_PIR, "PIR",
977                  SPR_NOACCESS, SPR_NOACCESS,
978                  &spr_read_generic, &spr_write_pir,
979                  0x00000000);
980     /* Breakpoints */
981     /* XXX : not implemented */
982     spr_register(env, SPR_IABR, "IABR",
983                  SPR_NOACCESS, SPR_NOACCESS,
984                  &spr_read_generic, &spr_write_generic,
985                  0x00000000);
986     /* XXX : not implemented */
987     spr_register(env, SPR_DABR, "DABR",
988                  SPR_NOACCESS, SPR_NOACCESS,
989                  &spr_read_generic, &spr_write_generic,
990                  0x00000000);
991     /* Performance counters */
992     /* XXX : not implemented */
993     spr_register(env, SPR_MMCR0, "MMCR0",
994                  SPR_NOACCESS, SPR_NOACCESS,
995                  &spr_read_generic, &spr_write_generic,
996                  0x00000000);
997     /* XXX : not implemented */
998     spr_register(env, SPR_PMC1, "PMC1",
999                  SPR_NOACCESS, SPR_NOACCESS,
1000                  &spr_read_generic, &spr_write_generic,
1001                  0x00000000);
1002     /* XXX : not implemented */
1003     spr_register(env, SPR_PMC2, "PMC2",
1004                  SPR_NOACCESS, SPR_NOACCESS,
1005                  &spr_read_generic, &spr_write_generic,
1006                  0x00000000);
1007     /* XXX : not implemented */
1008     spr_register(env, SPR_SIAR, "SIAR",
1009                  SPR_NOACCESS, SPR_NOACCESS,
1010                  &spr_read_generic, SPR_NOACCESS,
1011                  0x00000000);
1012     /* XXX : not implemented */
1013     spr_register(env, SPR_SDA, "SDA",
1014                  SPR_NOACCESS, SPR_NOACCESS,
1015                  &spr_read_generic, SPR_NOACCESS,
1016                  0x00000000);
1017     /* External access control */
1018     /* XXX : not implemented */
1019     spr_register(env, SPR_EAR, "EAR",
1020                  SPR_NOACCESS, SPR_NOACCESS,
1021                  &spr_read_generic, &spr_write_generic,
1022                  0x00000000);
1023 }
1024 
1025 /* SPR specific to PowerPC 603 implementation */
gen_spr_603(CPUPPCState * env)1026 static void gen_spr_603 (CPUPPCState *env)
1027 {
1028     /* External access control */
1029     /* XXX : not implemented */
1030     spr_register(env, SPR_EAR, "EAR",
1031                  SPR_NOACCESS, SPR_NOACCESS,
1032                  &spr_read_generic, &spr_write_generic,
1033                  0x00000000);
1034 }
1035 
1036 /* SPR specific to PowerPC G2 implementation */
gen_spr_G2(CPUPPCState * env)1037 static void gen_spr_G2 (CPUPPCState *env)
1038 {
1039     /* Memory base address */
1040     /* MBAR */
1041     /* XXX : not implemented */
1042     spr_register(env, SPR_MBAR, "MBAR",
1043                  SPR_NOACCESS, SPR_NOACCESS,
1044                  &spr_read_generic, &spr_write_generic,
1045                  0x00000000);
1046     /* Exception processing */
1047     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1048                  SPR_NOACCESS, SPR_NOACCESS,
1049                  &spr_read_generic, &spr_write_generic,
1050                  0x00000000);
1051     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1052                  SPR_NOACCESS, SPR_NOACCESS,
1053                  &spr_read_generic, &spr_write_generic,
1054                  0x00000000);
1055     /* Breakpoints */
1056     /* XXX : not implemented */
1057     spr_register(env, SPR_DABR, "DABR",
1058                  SPR_NOACCESS, SPR_NOACCESS,
1059                  &spr_read_generic, &spr_write_generic,
1060                  0x00000000);
1061     /* XXX : not implemented */
1062     spr_register(env, SPR_DABR2, "DABR2",
1063                  SPR_NOACCESS, SPR_NOACCESS,
1064                  &spr_read_generic, &spr_write_generic,
1065                  0x00000000);
1066     /* XXX : not implemented */
1067     spr_register(env, SPR_IABR, "IABR",
1068                  SPR_NOACCESS, SPR_NOACCESS,
1069                  &spr_read_generic, &spr_write_generic,
1070                  0x00000000);
1071     /* XXX : not implemented */
1072     spr_register(env, SPR_IABR2, "IABR2",
1073                  SPR_NOACCESS, SPR_NOACCESS,
1074                  &spr_read_generic, &spr_write_generic,
1075                  0x00000000);
1076     /* XXX : not implemented */
1077     spr_register(env, SPR_IBCR, "IBCR",
1078                  SPR_NOACCESS, SPR_NOACCESS,
1079                  &spr_read_generic, &spr_write_generic,
1080                  0x00000000);
1081     /* XXX : not implemented */
1082     spr_register(env, SPR_DBCR, "DBCR",
1083                  SPR_NOACCESS, SPR_NOACCESS,
1084                  &spr_read_generic, &spr_write_generic,
1085                  0x00000000);
1086 }
1087 
1088 /* SPR specific to PowerPC 602 implementation */
gen_spr_602(CPUPPCState * env)1089 static void gen_spr_602 (CPUPPCState *env)
1090 {
1091     /* ESA registers */
1092     /* XXX : not implemented */
1093     spr_register(env, SPR_SER, "SER",
1094                  SPR_NOACCESS, SPR_NOACCESS,
1095                  &spr_read_generic, &spr_write_generic,
1096                  0x00000000);
1097     /* XXX : not implemented */
1098     spr_register(env, SPR_SEBR, "SEBR",
1099                  SPR_NOACCESS, SPR_NOACCESS,
1100                  &spr_read_generic, &spr_write_generic,
1101                  0x00000000);
1102     /* XXX : not implemented */
1103     spr_register(env, SPR_ESASRR, "ESASRR",
1104                  SPR_NOACCESS, SPR_NOACCESS,
1105                  &spr_read_generic, &spr_write_generic,
1106                  0x00000000);
1107     /* Floating point status */
1108     /* XXX : not implemented */
1109     spr_register(env, SPR_SP, "SP",
1110                  SPR_NOACCESS, SPR_NOACCESS,
1111                  &spr_read_generic, &spr_write_generic,
1112                  0x00000000);
1113     /* XXX : not implemented */
1114     spr_register(env, SPR_LT, "LT",
1115                  SPR_NOACCESS, SPR_NOACCESS,
1116                  &spr_read_generic, &spr_write_generic,
1117                  0x00000000);
1118     /* Watchdog timer */
1119     /* XXX : not implemented */
1120     spr_register(env, SPR_TCR, "TCR",
1121                  SPR_NOACCESS, SPR_NOACCESS,
1122                  &spr_read_generic, &spr_write_generic,
1123                  0x00000000);
1124     /* Interrupt base */
1125     spr_register(env, SPR_IBR, "IBR",
1126                  SPR_NOACCESS, SPR_NOACCESS,
1127                  &spr_read_generic, &spr_write_generic,
1128                  0x00000000);
1129     /* XXX : not implemented */
1130     spr_register(env, SPR_IABR, "IABR",
1131                  SPR_NOACCESS, SPR_NOACCESS,
1132                  &spr_read_generic, &spr_write_generic,
1133                  0x00000000);
1134 }
1135 
1136 /* SPR specific to PowerPC 601 implementation */
gen_spr_601(CPUPPCState * env)1137 static void gen_spr_601 (CPUPPCState *env)
1138 {
1139     /* Multiplication/division register */
1140     /* MQ */
1141     spr_register(env, SPR_MQ, "MQ",
1142                  &spr_read_generic, &spr_write_generic,
1143                  &spr_read_generic, &spr_write_generic,
1144                  0x00000000);
1145     /* RTC registers */
1146     spr_register(env, SPR_601_RTCU, "RTCU",
1147                  SPR_NOACCESS, SPR_NOACCESS,
1148                  SPR_NOACCESS, &spr_write_601_rtcu,
1149                  0x00000000);
1150     spr_register(env, SPR_601_VRTCU, "RTCU",
1151                  &spr_read_601_rtcu, SPR_NOACCESS,
1152                  &spr_read_601_rtcu, SPR_NOACCESS,
1153                  0x00000000);
1154     spr_register(env, SPR_601_RTCL, "RTCL",
1155                  SPR_NOACCESS, SPR_NOACCESS,
1156                  SPR_NOACCESS, &spr_write_601_rtcl,
1157                  0x00000000);
1158     spr_register(env, SPR_601_VRTCL, "RTCL",
1159                  &spr_read_601_rtcl, SPR_NOACCESS,
1160                  &spr_read_601_rtcl, SPR_NOACCESS,
1161                  0x00000000);
1162     /* Timer */
1163 #if 0 /* ? */
1164     spr_register(env, SPR_601_UDECR, "UDECR",
1165                  &spr_read_decr, SPR_NOACCESS,
1166                  &spr_read_decr, SPR_NOACCESS,
1167                  0x00000000);
1168 #endif
1169     /* External access control */
1170     /* XXX : not implemented */
1171     spr_register(env, SPR_EAR, "EAR",
1172                  SPR_NOACCESS, SPR_NOACCESS,
1173                  &spr_read_generic, &spr_write_generic,
1174                  0x00000000);
1175     /* Memory management */
1176 #if !defined(CONFIG_USER_ONLY)
1177     spr_register(env, SPR_IBAT0U, "IBAT0U",
1178                  SPR_NOACCESS, SPR_NOACCESS,
1179                  &spr_read_601_ubat, &spr_write_601_ubatu,
1180                  0x00000000);
1181     spr_register(env, SPR_IBAT0L, "IBAT0L",
1182                  SPR_NOACCESS, SPR_NOACCESS,
1183                  &spr_read_601_ubat, &spr_write_601_ubatl,
1184                  0x00000000);
1185     spr_register(env, SPR_IBAT1U, "IBAT1U",
1186                  SPR_NOACCESS, SPR_NOACCESS,
1187                  &spr_read_601_ubat, &spr_write_601_ubatu,
1188                  0x00000000);
1189     spr_register(env, SPR_IBAT1L, "IBAT1L",
1190                  SPR_NOACCESS, SPR_NOACCESS,
1191                  &spr_read_601_ubat, &spr_write_601_ubatl,
1192                  0x00000000);
1193     spr_register(env, SPR_IBAT2U, "IBAT2U",
1194                  SPR_NOACCESS, SPR_NOACCESS,
1195                  &spr_read_601_ubat, &spr_write_601_ubatu,
1196                  0x00000000);
1197     spr_register(env, SPR_IBAT2L, "IBAT2L",
1198                  SPR_NOACCESS, SPR_NOACCESS,
1199                  &spr_read_601_ubat, &spr_write_601_ubatl,
1200                  0x00000000);
1201     spr_register(env, SPR_IBAT3U, "IBAT3U",
1202                  SPR_NOACCESS, SPR_NOACCESS,
1203                  &spr_read_601_ubat, &spr_write_601_ubatu,
1204                  0x00000000);
1205     spr_register(env, SPR_IBAT3L, "IBAT3L",
1206                  SPR_NOACCESS, SPR_NOACCESS,
1207                  &spr_read_601_ubat, &spr_write_601_ubatl,
1208                  0x00000000);
1209     env->nb_BATs = 4;
1210 #endif
1211 }
1212 
gen_spr_74xx(CPUPPCState * env)1213 static void gen_spr_74xx (CPUPPCState *env)
1214 {
1215     /* Processor identification */
1216     spr_register(env, SPR_PIR, "PIR",
1217                  SPR_NOACCESS, SPR_NOACCESS,
1218                  &spr_read_generic, &spr_write_pir,
1219                  0x00000000);
1220     /* XXX : not implemented */
1221     spr_register(env, SPR_MMCR2, "MMCR2",
1222                  SPR_NOACCESS, SPR_NOACCESS,
1223                  &spr_read_generic, &spr_write_generic,
1224                  0x00000000);
1225     /* XXX : not implemented */
1226     spr_register(env, SPR_UMMCR2, "UMMCR2",
1227                  &spr_read_ureg, SPR_NOACCESS,
1228                  &spr_read_ureg, SPR_NOACCESS,
1229                  0x00000000);
1230     /* XXX: not implemented */
1231     spr_register(env, SPR_BAMR, "BAMR",
1232                  SPR_NOACCESS, SPR_NOACCESS,
1233                  &spr_read_generic, &spr_write_generic,
1234                  0x00000000);
1235     /* XXX : not implemented */
1236     spr_register(env, SPR_MSSCR0, "MSSCR0",
1237                  SPR_NOACCESS, SPR_NOACCESS,
1238                  &spr_read_generic, &spr_write_generic,
1239                  0x00000000);
1240     /* Hardware implementation registers */
1241     /* XXX : not implemented */
1242     spr_register(env, SPR_HID0, "HID0",
1243                  SPR_NOACCESS, SPR_NOACCESS,
1244                  &spr_read_generic, &spr_write_generic,
1245                  0x00000000);
1246     /* XXX : not implemented */
1247     spr_register(env, SPR_HID1, "HID1",
1248                  SPR_NOACCESS, SPR_NOACCESS,
1249                  &spr_read_generic, &spr_write_generic,
1250                  0x00000000);
1251     /* Altivec */
1252     spr_register(env, SPR_VRSAVE, "VRSAVE",
1253                  &spr_read_generic, &spr_write_generic,
1254                  &spr_read_generic, &spr_write_generic,
1255                  0x00000000);
1256     /* XXX : not implemented */
1257     spr_register(env, SPR_L2CR, "L2CR",
1258                  SPR_NOACCESS, SPR_NOACCESS,
1259                  &spr_read_generic, &spr_write_generic,
1260                  0x00000000);
1261     /* Not strictly an SPR */
1262     vscr_init(env, 0x00010000);
1263 }
1264 
gen_l3_ctrl(CPUPPCState * env)1265 static void gen_l3_ctrl (CPUPPCState *env)
1266 {
1267     /* L3CR */
1268     /* XXX : not implemented */
1269     spr_register(env, SPR_L3CR, "L3CR",
1270                  SPR_NOACCESS, SPR_NOACCESS,
1271                  &spr_read_generic, &spr_write_generic,
1272                  0x00000000);
1273     /* L3ITCR0 */
1274     /* XXX : not implemented */
1275     spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1276                  SPR_NOACCESS, SPR_NOACCESS,
1277                  &spr_read_generic, &spr_write_generic,
1278                  0x00000000);
1279     /* L3PM */
1280     /* XXX : not implemented */
1281     spr_register(env, SPR_L3PM, "L3PM",
1282                  SPR_NOACCESS, SPR_NOACCESS,
1283                  &spr_read_generic, &spr_write_generic,
1284                  0x00000000);
1285 }
1286 
gen_74xx_soft_tlb(CPUPPCState * env,int nb_tlbs,int nb_ways)1287 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1288 {
1289 #if !defined(CONFIG_USER_ONLY)
1290     env->nb_tlb = nb_tlbs;
1291     env->nb_ways = nb_ways;
1292     env->id_tlbs = 1;
1293     /* XXX : not implemented */
1294     spr_register(env, SPR_PTEHI, "PTEHI",
1295                  SPR_NOACCESS, SPR_NOACCESS,
1296                  &spr_read_generic, &spr_write_generic,
1297                  0x00000000);
1298     /* XXX : not implemented */
1299     spr_register(env, SPR_PTELO, "PTELO",
1300                  SPR_NOACCESS, SPR_NOACCESS,
1301                  &spr_read_generic, &spr_write_generic,
1302                  0x00000000);
1303     /* XXX : not implemented */
1304     spr_register(env, SPR_TLBMISS, "TLBMISS",
1305                  SPR_NOACCESS, SPR_NOACCESS,
1306                  &spr_read_generic, &spr_write_generic,
1307                  0x00000000);
1308 #endif
1309 }
1310 
gen_spr_usprgh(CPUPPCState * env)1311 static void gen_spr_usprgh (CPUPPCState *env)
1312 {
1313     spr_register(env, SPR_USPRG4, "USPRG4",
1314                  &spr_read_ureg, SPR_NOACCESS,
1315                  &spr_read_ureg, SPR_NOACCESS,
1316                  0x00000000);
1317     spr_register(env, SPR_USPRG5, "USPRG5",
1318                  &spr_read_ureg, SPR_NOACCESS,
1319                  &spr_read_ureg, SPR_NOACCESS,
1320                  0x00000000);
1321     spr_register(env, SPR_USPRG6, "USPRG6",
1322                  &spr_read_ureg, SPR_NOACCESS,
1323                  &spr_read_ureg, SPR_NOACCESS,
1324                  0x00000000);
1325     spr_register(env, SPR_USPRG7, "USPRG7",
1326                  &spr_read_ureg, SPR_NOACCESS,
1327                  &spr_read_ureg, SPR_NOACCESS,
1328                  0x00000000);
1329 }
1330 
1331 /* PowerPC BookE SPR */
gen_spr_BookE(CPUPPCState * env,uint64_t ivor_mask)1332 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1333 {
1334     const char *ivor_names[64] = {
1335         "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1336         "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1337         "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1338         "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1339         "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1340         "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1341         "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1342         "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1343         "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1344         "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1345         "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1346         "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1347         "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1348         "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1349         "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1350         "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1351     };
1352 #define SPR_BOOKE_IVORxx (-1)
1353     int ivor_sprn[64] = {
1354         SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1355         SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1356         SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1357         SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1358         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1359         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1360         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1361         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1362         SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1363         SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1364         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1365         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1366         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1367         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1368         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1369         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1370     };
1371     int i;
1372 
1373     /* Interrupt processing */
1374     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1375                  SPR_NOACCESS, SPR_NOACCESS,
1376                  &spr_read_generic, &spr_write_generic,
1377                  0x00000000);
1378     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1379                  SPR_NOACCESS, SPR_NOACCESS,
1380                  &spr_read_generic, &spr_write_generic,
1381                  0x00000000);
1382     /* Debug */
1383     /* XXX : not implemented */
1384     spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1385                  SPR_NOACCESS, SPR_NOACCESS,
1386                  &spr_read_generic, &spr_write_generic,
1387                  0x00000000);
1388     /* XXX : not implemented */
1389     spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1390                  SPR_NOACCESS, SPR_NOACCESS,
1391                  &spr_read_generic, &spr_write_generic,
1392                  0x00000000);
1393     /* XXX : not implemented */
1394     spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1395                  SPR_NOACCESS, SPR_NOACCESS,
1396                  &spr_read_generic, &spr_write_generic,
1397                  0x00000000);
1398     /* XXX : not implemented */
1399     spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1400                  SPR_NOACCESS, SPR_NOACCESS,
1401                  &spr_read_generic, &spr_write_generic,
1402                  0x00000000);
1403     /* XXX : not implemented */
1404     spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1405                  SPR_NOACCESS, SPR_NOACCESS,
1406                  &spr_read_generic, &spr_write_generic,
1407                  0x00000000);
1408     /* XXX : not implemented */
1409     spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1410                  SPR_NOACCESS, SPR_NOACCESS,
1411                  &spr_read_generic, &spr_write_generic,
1412                  0x00000000);
1413     /* XXX : not implemented */
1414     spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1415                  SPR_NOACCESS, SPR_NOACCESS,
1416                  &spr_read_generic, &spr_write_generic,
1417                  0x00000000);
1418     /* XXX : not implemented */
1419     spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1420                  SPR_NOACCESS, SPR_NOACCESS,
1421                  &spr_read_generic, &spr_write_clear,
1422                  0x00000000);
1423     spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1424                  SPR_NOACCESS, SPR_NOACCESS,
1425                  &spr_read_generic, &spr_write_generic,
1426                  0x00000000);
1427     spr_register(env, SPR_BOOKE_ESR, "ESR",
1428                  SPR_NOACCESS, SPR_NOACCESS,
1429                  &spr_read_generic, &spr_write_generic,
1430                  0x00000000);
1431     spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1432                  SPR_NOACCESS, SPR_NOACCESS,
1433                  &spr_read_generic, &spr_write_excp_prefix,
1434                  0x00000000);
1435     /* Exception vectors */
1436     for (i = 0; i < 64; i++) {
1437         if (ivor_mask & (1ULL << i)) {
1438             if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1439                 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1440                 exit(1);
1441             }
1442             spr_register(env, ivor_sprn[i], ivor_names[i],
1443                          SPR_NOACCESS, SPR_NOACCESS,
1444                          &spr_read_generic, &spr_write_excp_vector,
1445                          0x00000000);
1446         }
1447     }
1448     spr_register(env, SPR_BOOKE_PID, "PID",
1449                  SPR_NOACCESS, SPR_NOACCESS,
1450                  &spr_read_generic, &spr_write_generic,
1451                  0x00000000);
1452     spr_register(env, SPR_BOOKE_TCR, "TCR",
1453                  SPR_NOACCESS, SPR_NOACCESS,
1454                  &spr_read_generic, &spr_write_booke_tcr,
1455                  0x00000000);
1456     spr_register(env, SPR_BOOKE_TSR, "TSR",
1457                  SPR_NOACCESS, SPR_NOACCESS,
1458                  &spr_read_generic, &spr_write_booke_tsr,
1459                  0x00000000);
1460     /* Timer */
1461     spr_register(env, SPR_DECR, "DECR",
1462                  SPR_NOACCESS, SPR_NOACCESS,
1463                  &spr_read_decr, &spr_write_decr,
1464                  0x00000000);
1465     spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1466                  SPR_NOACCESS, SPR_NOACCESS,
1467                  SPR_NOACCESS, &spr_write_generic,
1468                  0x00000000);
1469     /* SPRGs */
1470     spr_register(env, SPR_USPRG0, "USPRG0",
1471                  &spr_read_generic, &spr_write_generic,
1472                  &spr_read_generic, &spr_write_generic,
1473                  0x00000000);
1474     spr_register(env, SPR_SPRG4, "SPRG4",
1475                  SPR_NOACCESS, SPR_NOACCESS,
1476                  &spr_read_generic, &spr_write_generic,
1477                  0x00000000);
1478     spr_register(env, SPR_SPRG5, "SPRG5",
1479                  SPR_NOACCESS, SPR_NOACCESS,
1480                  &spr_read_generic, &spr_write_generic,
1481                  0x00000000);
1482     spr_register(env, SPR_SPRG6, "SPRG6",
1483                  SPR_NOACCESS, SPR_NOACCESS,
1484                  &spr_read_generic, &spr_write_generic,
1485                  0x00000000);
1486     spr_register(env, SPR_SPRG7, "SPRG7",
1487                  SPR_NOACCESS, SPR_NOACCESS,
1488                  &spr_read_generic, &spr_write_generic,
1489                  0x00000000);
1490 }
1491 
1492 /* FSL storage control registers */
gen_spr_BookE_FSL(CPUPPCState * env,uint32_t mas_mask)1493 static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1494 {
1495 #if !defined(CONFIG_USER_ONLY)
1496     const char *mas_names[8] = {
1497         "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1498     };
1499     int mas_sprn[8] = {
1500         SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1501         SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1502     };
1503     int i;
1504 
1505     /* TLB assist registers */
1506     /* XXX : not implemented */
1507     for (i = 0; i < 8; i++) {
1508         if (mas_mask & (1 << i)) {
1509             spr_register(env, mas_sprn[i], mas_names[i],
1510                          SPR_NOACCESS, SPR_NOACCESS,
1511                          &spr_read_generic, &spr_write_generic,
1512                          0x00000000);
1513         }
1514     }
1515     if (env->nb_pids > 1) {
1516         /* XXX : not implemented */
1517         spr_register(env, SPR_BOOKE_PID1, "PID1",
1518                      SPR_NOACCESS, SPR_NOACCESS,
1519                      &spr_read_generic, &spr_write_generic,
1520                      0x00000000);
1521     }
1522     if (env->nb_pids > 2) {
1523         /* XXX : not implemented */
1524         spr_register(env, SPR_BOOKE_PID2, "PID2",
1525                      SPR_NOACCESS, SPR_NOACCESS,
1526                      &spr_read_generic, &spr_write_generic,
1527                      0x00000000);
1528     }
1529     /* XXX : not implemented */
1530     spr_register(env, SPR_MMUCFG, "MMUCFG",
1531                  SPR_NOACCESS, SPR_NOACCESS,
1532                  &spr_read_generic, SPR_NOACCESS,
1533                  0x00000000); /* TOFIX */
1534     /* XXX : not implemented */
1535     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1536                  SPR_NOACCESS, SPR_NOACCESS,
1537                  &spr_read_generic, &spr_write_generic,
1538                  0x00000000); /* TOFIX */
1539     switch (env->nb_ways) {
1540     case 4:
1541         /* XXX : not implemented */
1542         spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1543                      SPR_NOACCESS, SPR_NOACCESS,
1544                      &spr_read_generic, SPR_NOACCESS,
1545                      0x00000000); /* TOFIX */
1546         /* Fallthru */
1547     case 3:
1548         /* XXX : not implemented */
1549         spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1550                      SPR_NOACCESS, SPR_NOACCESS,
1551                      &spr_read_generic, SPR_NOACCESS,
1552                      0x00000000); /* TOFIX */
1553         /* Fallthru */
1554     case 2:
1555         /* XXX : not implemented */
1556         spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1557                      SPR_NOACCESS, SPR_NOACCESS,
1558                      &spr_read_generic, SPR_NOACCESS,
1559                      0x00000000); /* TOFIX */
1560         /* Fallthru */
1561     case 1:
1562         /* XXX : not implemented */
1563         spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1564                      SPR_NOACCESS, SPR_NOACCESS,
1565                      &spr_read_generic, SPR_NOACCESS,
1566                      0x00000000); /* TOFIX */
1567         /* Fallthru */
1568     case 0:
1569     default:
1570         break;
1571     }
1572 #endif
1573 }
1574 
1575 /* SPR specific to PowerPC 440 implementation */
gen_spr_440(CPUPPCState * env)1576 static void gen_spr_440 (CPUPPCState *env)
1577 {
1578     /* Cache control */
1579     /* XXX : not implemented */
1580     spr_register(env, SPR_440_DNV0, "DNV0",
1581                  SPR_NOACCESS, SPR_NOACCESS,
1582                  &spr_read_generic, &spr_write_generic,
1583                  0x00000000);
1584     /* XXX : not implemented */
1585     spr_register(env, SPR_440_DNV1, "DNV1",
1586                  SPR_NOACCESS, SPR_NOACCESS,
1587                  &spr_read_generic, &spr_write_generic,
1588                  0x00000000);
1589     /* XXX : not implemented */
1590     spr_register(env, SPR_440_DNV2, "DNV2",
1591                  SPR_NOACCESS, SPR_NOACCESS,
1592                  &spr_read_generic, &spr_write_generic,
1593                  0x00000000);
1594     /* XXX : not implemented */
1595     spr_register(env, SPR_440_DNV3, "DNV3",
1596                  SPR_NOACCESS, SPR_NOACCESS,
1597                  &spr_read_generic, &spr_write_generic,
1598                  0x00000000);
1599     /* XXX : not implemented */
1600     spr_register(env, SPR_440_DTV0, "DTV0",
1601                  SPR_NOACCESS, SPR_NOACCESS,
1602                  &spr_read_generic, &spr_write_generic,
1603                  0x00000000);
1604     /* XXX : not implemented */
1605     spr_register(env, SPR_440_DTV1, "DTV1",
1606                  SPR_NOACCESS, SPR_NOACCESS,
1607                  &spr_read_generic, &spr_write_generic,
1608                  0x00000000);
1609     /* XXX : not implemented */
1610     spr_register(env, SPR_440_DTV2, "DTV2",
1611                  SPR_NOACCESS, SPR_NOACCESS,
1612                  &spr_read_generic, &spr_write_generic,
1613                  0x00000000);
1614     /* XXX : not implemented */
1615     spr_register(env, SPR_440_DTV3, "DTV3",
1616                  SPR_NOACCESS, SPR_NOACCESS,
1617                  &spr_read_generic, &spr_write_generic,
1618                  0x00000000);
1619     /* XXX : not implemented */
1620     spr_register(env, SPR_440_DVLIM, "DVLIM",
1621                  SPR_NOACCESS, SPR_NOACCESS,
1622                  &spr_read_generic, &spr_write_generic,
1623                  0x00000000);
1624     /* XXX : not implemented */
1625     spr_register(env, SPR_440_INV0, "INV0",
1626                  SPR_NOACCESS, SPR_NOACCESS,
1627                  &spr_read_generic, &spr_write_generic,
1628                  0x00000000);
1629     /* XXX : not implemented */
1630     spr_register(env, SPR_440_INV1, "INV1",
1631                  SPR_NOACCESS, SPR_NOACCESS,
1632                  &spr_read_generic, &spr_write_generic,
1633                  0x00000000);
1634     /* XXX : not implemented */
1635     spr_register(env, SPR_440_INV2, "INV2",
1636                  SPR_NOACCESS, SPR_NOACCESS,
1637                  &spr_read_generic, &spr_write_generic,
1638                  0x00000000);
1639     /* XXX : not implemented */
1640     spr_register(env, SPR_440_INV3, "INV3",
1641                  SPR_NOACCESS, SPR_NOACCESS,
1642                  &spr_read_generic, &spr_write_generic,
1643                  0x00000000);
1644     /* XXX : not implemented */
1645     spr_register(env, SPR_440_ITV0, "ITV0",
1646                  SPR_NOACCESS, SPR_NOACCESS,
1647                  &spr_read_generic, &spr_write_generic,
1648                  0x00000000);
1649     /* XXX : not implemented */
1650     spr_register(env, SPR_440_ITV1, "ITV1",
1651                  SPR_NOACCESS, SPR_NOACCESS,
1652                  &spr_read_generic, &spr_write_generic,
1653                  0x00000000);
1654     /* XXX : not implemented */
1655     spr_register(env, SPR_440_ITV2, "ITV2",
1656                  SPR_NOACCESS, SPR_NOACCESS,
1657                  &spr_read_generic, &spr_write_generic,
1658                  0x00000000);
1659     /* XXX : not implemented */
1660     spr_register(env, SPR_440_ITV3, "ITV3",
1661                  SPR_NOACCESS, SPR_NOACCESS,
1662                  &spr_read_generic, &spr_write_generic,
1663                  0x00000000);
1664     /* XXX : not implemented */
1665     spr_register(env, SPR_440_IVLIM, "IVLIM",
1666                  SPR_NOACCESS, SPR_NOACCESS,
1667                  &spr_read_generic, &spr_write_generic,
1668                  0x00000000);
1669     /* Cache debug */
1670     /* XXX : not implemented */
1671     spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1672                  SPR_NOACCESS, SPR_NOACCESS,
1673                  &spr_read_generic, SPR_NOACCESS,
1674                  0x00000000);
1675     /* XXX : not implemented */
1676     spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1677                  SPR_NOACCESS, SPR_NOACCESS,
1678                  &spr_read_generic, SPR_NOACCESS,
1679                  0x00000000);
1680     /* XXX : not implemented */
1681     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1682                  SPR_NOACCESS, SPR_NOACCESS,
1683                  &spr_read_generic, SPR_NOACCESS,
1684                  0x00000000);
1685     /* XXX : not implemented */
1686     spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1687                  SPR_NOACCESS, SPR_NOACCESS,
1688                  &spr_read_generic, SPR_NOACCESS,
1689                  0x00000000);
1690     /* XXX : not implemented */
1691     spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1692                  SPR_NOACCESS, SPR_NOACCESS,
1693                  &spr_read_generic, SPR_NOACCESS,
1694                  0x00000000);
1695     /* XXX : not implemented */
1696     spr_register(env, SPR_440_DBDR, "DBDR",
1697                  SPR_NOACCESS, SPR_NOACCESS,
1698                  &spr_read_generic, &spr_write_generic,
1699                  0x00000000);
1700     /* Processor control */
1701     spr_register(env, SPR_4xx_CCR0, "CCR0",
1702                  SPR_NOACCESS, SPR_NOACCESS,
1703                  &spr_read_generic, &spr_write_generic,
1704                  0x00000000);
1705     spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1706                  SPR_NOACCESS, SPR_NOACCESS,
1707                  &spr_read_generic, SPR_NOACCESS,
1708                  0x00000000);
1709     /* Storage control */
1710     spr_register(env, SPR_440_MMUCR, "MMUCR",
1711                  SPR_NOACCESS, SPR_NOACCESS,
1712                  &spr_read_generic, &spr_write_generic,
1713                  0x00000000);
1714 }
1715 
1716 /* SPR shared between PowerPC 40x implementations */
gen_spr_40x(CPUPPCState * env)1717 static void gen_spr_40x (CPUPPCState *env)
1718 {
1719     /* Cache */
1720     /* not emulated, as Qemu do not emulate caches */
1721     spr_register(env, SPR_40x_DCCR, "DCCR",
1722                  SPR_NOACCESS, SPR_NOACCESS,
1723                  &spr_read_generic, &spr_write_generic,
1724                  0x00000000);
1725     /* not emulated, as Qemu do not emulate caches */
1726     spr_register(env, SPR_40x_ICCR, "ICCR",
1727                  SPR_NOACCESS, SPR_NOACCESS,
1728                  &spr_read_generic, &spr_write_generic,
1729                  0x00000000);
1730     /* not emulated, as Qemu do not emulate caches */
1731     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1732                  SPR_NOACCESS, SPR_NOACCESS,
1733                  &spr_read_generic, SPR_NOACCESS,
1734                  0x00000000);
1735     /* Exception */
1736     spr_register(env, SPR_40x_DEAR, "DEAR",
1737                  SPR_NOACCESS, SPR_NOACCESS,
1738                  &spr_read_generic, &spr_write_generic,
1739                  0x00000000);
1740     spr_register(env, SPR_40x_ESR, "ESR",
1741                  SPR_NOACCESS, SPR_NOACCESS,
1742                  &spr_read_generic, &spr_write_generic,
1743                  0x00000000);
1744     spr_register(env, SPR_40x_EVPR, "EVPR",
1745                  SPR_NOACCESS, SPR_NOACCESS,
1746                  &spr_read_generic, &spr_write_excp_prefix,
1747                  0x00000000);
1748     spr_register(env, SPR_40x_SRR2, "SRR2",
1749                  &spr_read_generic, &spr_write_generic,
1750                  &spr_read_generic, &spr_write_generic,
1751                  0x00000000);
1752     spr_register(env, SPR_40x_SRR3, "SRR3",
1753                  &spr_read_generic, &spr_write_generic,
1754                  &spr_read_generic, &spr_write_generic,
1755                  0x00000000);
1756     /* Timers */
1757     spr_register(env, SPR_40x_PIT, "PIT",
1758                  SPR_NOACCESS, SPR_NOACCESS,
1759                  &spr_read_40x_pit, &spr_write_40x_pit,
1760                  0x00000000);
1761     spr_register(env, SPR_40x_TCR, "TCR",
1762                  SPR_NOACCESS, SPR_NOACCESS,
1763                  &spr_read_generic, &spr_write_booke_tcr,
1764                  0x00000000);
1765     spr_register(env, SPR_40x_TSR, "TSR",
1766                  SPR_NOACCESS, SPR_NOACCESS,
1767                  &spr_read_generic, &spr_write_booke_tsr,
1768                  0x00000000);
1769 }
1770 
1771 /* SPR specific to PowerPC 405 implementation */
gen_spr_405(CPUPPCState * env)1772 static void gen_spr_405 (CPUPPCState *env)
1773 {
1774     /* MMU */
1775     spr_register(env, SPR_40x_PID, "PID",
1776                  SPR_NOACCESS, SPR_NOACCESS,
1777                  &spr_read_generic, &spr_write_generic,
1778                  0x00000000);
1779     spr_register(env, SPR_4xx_CCR0, "CCR0",
1780                  SPR_NOACCESS, SPR_NOACCESS,
1781                  &spr_read_generic, &spr_write_generic,
1782                  0x00700000);
1783     /* Debug interface */
1784     /* XXX : not implemented */
1785     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1786                  SPR_NOACCESS, SPR_NOACCESS,
1787                  &spr_read_generic, &spr_write_40x_dbcr0,
1788                  0x00000000);
1789     /* XXX : not implemented */
1790     spr_register(env, SPR_405_DBCR1, "DBCR1",
1791                  SPR_NOACCESS, SPR_NOACCESS,
1792                  &spr_read_generic, &spr_write_generic,
1793                  0x00000000);
1794     /* XXX : not implemented */
1795     spr_register(env, SPR_40x_DBSR, "DBSR",
1796                  SPR_NOACCESS, SPR_NOACCESS,
1797                  &spr_read_generic, &spr_write_clear,
1798                  /* Last reset was system reset */
1799                  0x00000300);
1800     /* XXX : not implemented */
1801     spr_register(env, SPR_40x_DAC1, "DAC1",
1802                  SPR_NOACCESS, SPR_NOACCESS,
1803                  &spr_read_generic, &spr_write_generic,
1804                  0x00000000);
1805     spr_register(env, SPR_40x_DAC2, "DAC2",
1806                  SPR_NOACCESS, SPR_NOACCESS,
1807                  &spr_read_generic, &spr_write_generic,
1808                  0x00000000);
1809     /* XXX : not implemented */
1810     spr_register(env, SPR_405_DVC1, "DVC1",
1811                  SPR_NOACCESS, SPR_NOACCESS,
1812                  &spr_read_generic, &spr_write_generic,
1813                  0x00000000);
1814     /* XXX : not implemented */
1815     spr_register(env, SPR_405_DVC2, "DVC2",
1816                  SPR_NOACCESS, SPR_NOACCESS,
1817                  &spr_read_generic, &spr_write_generic,
1818                  0x00000000);
1819     /* XXX : not implemented */
1820     spr_register(env, SPR_40x_IAC1, "IAC1",
1821                  SPR_NOACCESS, SPR_NOACCESS,
1822                  &spr_read_generic, &spr_write_generic,
1823                  0x00000000);
1824     spr_register(env, SPR_40x_IAC2, "IAC2",
1825                  SPR_NOACCESS, SPR_NOACCESS,
1826                  &spr_read_generic, &spr_write_generic,
1827                  0x00000000);
1828     /* XXX : not implemented */
1829     spr_register(env, SPR_405_IAC3, "IAC3",
1830                  SPR_NOACCESS, SPR_NOACCESS,
1831                  &spr_read_generic, &spr_write_generic,
1832                  0x00000000);
1833     /* XXX : not implemented */
1834     spr_register(env, SPR_405_IAC4, "IAC4",
1835                  SPR_NOACCESS, SPR_NOACCESS,
1836                  &spr_read_generic, &spr_write_generic,
1837                  0x00000000);
1838     /* Storage control */
1839     /* XXX: TODO: not implemented */
1840     spr_register(env, SPR_405_SLER, "SLER",
1841                  SPR_NOACCESS, SPR_NOACCESS,
1842                  &spr_read_generic, &spr_write_40x_sler,
1843                  0x00000000);
1844     spr_register(env, SPR_40x_ZPR, "ZPR",
1845                  SPR_NOACCESS, SPR_NOACCESS,
1846                  &spr_read_generic, &spr_write_generic,
1847                  0x00000000);
1848     /* XXX : not implemented */
1849     spr_register(env, SPR_405_SU0R, "SU0R",
1850                  SPR_NOACCESS, SPR_NOACCESS,
1851                  &spr_read_generic, &spr_write_generic,
1852                  0x00000000);
1853     /* SPRG */
1854     spr_register(env, SPR_USPRG0, "USPRG0",
1855                  &spr_read_ureg, SPR_NOACCESS,
1856                  &spr_read_ureg, SPR_NOACCESS,
1857                  0x00000000);
1858     spr_register(env, SPR_SPRG4, "SPRG4",
1859                  SPR_NOACCESS, SPR_NOACCESS,
1860                  &spr_read_generic, &spr_write_generic,
1861                  0x00000000);
1862     spr_register(env, SPR_SPRG5, "SPRG5",
1863                  SPR_NOACCESS, SPR_NOACCESS,
1864                  spr_read_generic, &spr_write_generic,
1865                  0x00000000);
1866     spr_register(env, SPR_SPRG6, "SPRG6",
1867                  SPR_NOACCESS, SPR_NOACCESS,
1868                  spr_read_generic, &spr_write_generic,
1869                  0x00000000);
1870     spr_register(env, SPR_SPRG7, "SPRG7",
1871                  SPR_NOACCESS, SPR_NOACCESS,
1872                  spr_read_generic, &spr_write_generic,
1873                  0x00000000);
1874     gen_spr_usprgh(env);
1875 }
1876 
1877 /* SPR shared between PowerPC 401 & 403 implementations */
gen_spr_401_403(CPUPPCState * env)1878 static void gen_spr_401_403 (CPUPPCState *env)
1879 {
1880     /* Time base */
1881     spr_register(env, SPR_403_VTBL,  "TBL",
1882                  &spr_read_tbl, SPR_NOACCESS,
1883                  &spr_read_tbl, SPR_NOACCESS,
1884                  0x00000000);
1885     spr_register(env, SPR_403_TBL,   "TBL",
1886                  SPR_NOACCESS, SPR_NOACCESS,
1887                  SPR_NOACCESS, &spr_write_tbl,
1888                  0x00000000);
1889     spr_register(env, SPR_403_VTBU,  "TBU",
1890                  &spr_read_tbu, SPR_NOACCESS,
1891                  &spr_read_tbu, SPR_NOACCESS,
1892                  0x00000000);
1893     spr_register(env, SPR_403_TBU,   "TBU",
1894                  SPR_NOACCESS, SPR_NOACCESS,
1895                  SPR_NOACCESS, &spr_write_tbu,
1896                  0x00000000);
1897     /* Debug */
1898     /* not emulated, as Qemu do not emulate caches */
1899     spr_register(env, SPR_403_CDBCR, "CDBCR",
1900                  SPR_NOACCESS, SPR_NOACCESS,
1901                  &spr_read_generic, &spr_write_generic,
1902                  0x00000000);
1903 }
1904 
1905 /* SPR specific to PowerPC 401 implementation */
gen_spr_401(CPUPPCState * env)1906 static void gen_spr_401 (CPUPPCState *env)
1907 {
1908     /* Debug interface */
1909     /* XXX : not implemented */
1910     spr_register(env, SPR_40x_DBCR0, "DBCR",
1911                  SPR_NOACCESS, SPR_NOACCESS,
1912                  &spr_read_generic, &spr_write_40x_dbcr0,
1913                  0x00000000);
1914     /* XXX : not implemented */
1915     spr_register(env, SPR_40x_DBSR, "DBSR",
1916                  SPR_NOACCESS, SPR_NOACCESS,
1917                  &spr_read_generic, &spr_write_clear,
1918                  /* Last reset was system reset */
1919                  0x00000300);
1920     /* XXX : not implemented */
1921     spr_register(env, SPR_40x_DAC1, "DAC",
1922                  SPR_NOACCESS, SPR_NOACCESS,
1923                  &spr_read_generic, &spr_write_generic,
1924                  0x00000000);
1925     /* XXX : not implemented */
1926     spr_register(env, SPR_40x_IAC1, "IAC",
1927                  SPR_NOACCESS, SPR_NOACCESS,
1928                  &spr_read_generic, &spr_write_generic,
1929                  0x00000000);
1930     /* Storage control */
1931     /* XXX: TODO: not implemented */
1932     spr_register(env, SPR_405_SLER, "SLER",
1933                  SPR_NOACCESS, SPR_NOACCESS,
1934                  &spr_read_generic, &spr_write_40x_sler,
1935                  0x00000000);
1936     /* not emulated, as Qemu never does speculative access */
1937     spr_register(env, SPR_40x_SGR, "SGR",
1938                  SPR_NOACCESS, SPR_NOACCESS,
1939                  &spr_read_generic, &spr_write_generic,
1940                  0xFFFFFFFF);
1941     /* not emulated, as Qemu do not emulate caches */
1942     spr_register(env, SPR_40x_DCWR, "DCWR",
1943                  SPR_NOACCESS, SPR_NOACCESS,
1944                  &spr_read_generic, &spr_write_generic,
1945                  0x00000000);
1946 }
1947 
gen_spr_401x2(CPUPPCState * env)1948 static void gen_spr_401x2 (CPUPPCState *env)
1949 {
1950     gen_spr_401(env);
1951     spr_register(env, SPR_40x_PID, "PID",
1952                  SPR_NOACCESS, SPR_NOACCESS,
1953                  &spr_read_generic, &spr_write_generic,
1954                  0x00000000);
1955     spr_register(env, SPR_40x_ZPR, "ZPR",
1956                  SPR_NOACCESS, SPR_NOACCESS,
1957                  &spr_read_generic, &spr_write_generic,
1958                  0x00000000);
1959 }
1960 
1961 /* SPR specific to PowerPC 403 implementation */
gen_spr_403(CPUPPCState * env)1962 static void gen_spr_403 (CPUPPCState *env)
1963 {
1964     /* Debug interface */
1965     /* XXX : not implemented */
1966     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1967                  SPR_NOACCESS, SPR_NOACCESS,
1968                  &spr_read_generic, &spr_write_40x_dbcr0,
1969                  0x00000000);
1970     /* XXX : not implemented */
1971     spr_register(env, SPR_40x_DBSR, "DBSR",
1972                  SPR_NOACCESS, SPR_NOACCESS,
1973                  &spr_read_generic, &spr_write_clear,
1974                  /* Last reset was system reset */
1975                  0x00000300);
1976     /* XXX : not implemented */
1977     spr_register(env, SPR_40x_DAC1, "DAC1",
1978                  SPR_NOACCESS, SPR_NOACCESS,
1979                  &spr_read_generic, &spr_write_generic,
1980                  0x00000000);
1981     /* XXX : not implemented */
1982     spr_register(env, SPR_40x_DAC2, "DAC2",
1983                  SPR_NOACCESS, SPR_NOACCESS,
1984                  &spr_read_generic, &spr_write_generic,
1985                  0x00000000);
1986     /* XXX : not implemented */
1987     spr_register(env, SPR_40x_IAC1, "IAC1",
1988                  SPR_NOACCESS, SPR_NOACCESS,
1989                  &spr_read_generic, &spr_write_generic,
1990                  0x00000000);
1991     /* XXX : not implemented */
1992     spr_register(env, SPR_40x_IAC2, "IAC2",
1993                  SPR_NOACCESS, SPR_NOACCESS,
1994                  &spr_read_generic, &spr_write_generic,
1995                  0x00000000);
1996 }
1997 
gen_spr_403_real(CPUPPCState * env)1998 static void gen_spr_403_real (CPUPPCState *env)
1999 {
2000     spr_register(env, SPR_403_PBL1,  "PBL1",
2001                  SPR_NOACCESS, SPR_NOACCESS,
2002                  &spr_read_403_pbr, &spr_write_403_pbr,
2003                  0x00000000);
2004     spr_register(env, SPR_403_PBU1,  "PBU1",
2005                  SPR_NOACCESS, SPR_NOACCESS,
2006                  &spr_read_403_pbr, &spr_write_403_pbr,
2007                  0x00000000);
2008     spr_register(env, SPR_403_PBL2,  "PBL2",
2009                  SPR_NOACCESS, SPR_NOACCESS,
2010                  &spr_read_403_pbr, &spr_write_403_pbr,
2011                  0x00000000);
2012     spr_register(env, SPR_403_PBU2,  "PBU2",
2013                  SPR_NOACCESS, SPR_NOACCESS,
2014                  &spr_read_403_pbr, &spr_write_403_pbr,
2015                  0x00000000);
2016 }
2017 
gen_spr_403_mmu(CPUPPCState * env)2018 static void gen_spr_403_mmu (CPUPPCState *env)
2019 {
2020     /* MMU */
2021     spr_register(env, SPR_40x_PID, "PID",
2022                  SPR_NOACCESS, SPR_NOACCESS,
2023                  &spr_read_generic, &spr_write_generic,
2024                  0x00000000);
2025     spr_register(env, SPR_40x_ZPR, "ZPR",
2026                  SPR_NOACCESS, SPR_NOACCESS,
2027                  &spr_read_generic, &spr_write_generic,
2028                  0x00000000);
2029 }
2030 
2031 /* SPR specific to PowerPC compression coprocessor extension */
gen_spr_compress(CPUPPCState * env)2032 static void gen_spr_compress (CPUPPCState *env)
2033 {
2034     /* XXX : not implemented */
2035     spr_register(env, SPR_401_SKR, "SKR",
2036                  SPR_NOACCESS, SPR_NOACCESS,
2037                  &spr_read_generic, &spr_write_generic,
2038                  0x00000000);
2039 }
2040 
2041 #if defined (TARGET_PPC64)
2042 /* SPR specific to PowerPC 620 */
gen_spr_620(CPUPPCState * env)2043 static void gen_spr_620 (CPUPPCState *env)
2044 {
2045     /* Processor identification */
2046     spr_register(env, SPR_PIR, "PIR",
2047                  SPR_NOACCESS, SPR_NOACCESS,
2048                  &spr_read_generic, &spr_write_pir,
2049                  0x00000000);
2050     spr_register(env, SPR_ASR, "ASR",
2051                  SPR_NOACCESS, SPR_NOACCESS,
2052                  &spr_read_asr, &spr_write_asr,
2053                  0x00000000);
2054     /* Breakpoints */
2055     /* XXX : not implemented */
2056     spr_register(env, SPR_IABR, "IABR",
2057                  SPR_NOACCESS, SPR_NOACCESS,
2058                  &spr_read_generic, &spr_write_generic,
2059                  0x00000000);
2060     /* XXX : not implemented */
2061     spr_register(env, SPR_DABR, "DABR",
2062                  SPR_NOACCESS, SPR_NOACCESS,
2063                  &spr_read_generic, &spr_write_generic,
2064                  0x00000000);
2065     /* XXX : not implemented */
2066     spr_register(env, SPR_SIAR, "SIAR",
2067                  SPR_NOACCESS, SPR_NOACCESS,
2068                  &spr_read_generic, SPR_NOACCESS,
2069                  0x00000000);
2070     /* XXX : not implemented */
2071     spr_register(env, SPR_SDA, "SDA",
2072                  SPR_NOACCESS, SPR_NOACCESS,
2073                  &spr_read_generic, SPR_NOACCESS,
2074                  0x00000000);
2075     /* XXX : not implemented */
2076     spr_register(env, SPR_620_PMC1R, "PMC1",
2077                  SPR_NOACCESS, SPR_NOACCESS,
2078                  &spr_read_generic, SPR_NOACCESS,
2079                  0x00000000);
2080     spr_register(env, SPR_620_PMC1W, "PMC1",
2081                  SPR_NOACCESS, SPR_NOACCESS,
2082                   SPR_NOACCESS, &spr_write_generic,
2083                  0x00000000);
2084     /* XXX : not implemented */
2085     spr_register(env, SPR_620_PMC2R, "PMC2",
2086                  SPR_NOACCESS, SPR_NOACCESS,
2087                  &spr_read_generic, SPR_NOACCESS,
2088                  0x00000000);
2089     spr_register(env, SPR_620_PMC2W, "PMC2",
2090                  SPR_NOACCESS, SPR_NOACCESS,
2091                   SPR_NOACCESS, &spr_write_generic,
2092                  0x00000000);
2093     /* XXX : not implemented */
2094     spr_register(env, SPR_620_MMCR0R, "MMCR0",
2095                  SPR_NOACCESS, SPR_NOACCESS,
2096                  &spr_read_generic, SPR_NOACCESS,
2097                  0x00000000);
2098     spr_register(env, SPR_620_MMCR0W, "MMCR0",
2099                  SPR_NOACCESS, SPR_NOACCESS,
2100                   SPR_NOACCESS, &spr_write_generic,
2101                  0x00000000);
2102     /* External access control */
2103     /* XXX : not implemented */
2104     spr_register(env, SPR_EAR, "EAR",
2105                  SPR_NOACCESS, SPR_NOACCESS,
2106                  &spr_read_generic, &spr_write_generic,
2107                  0x00000000);
2108 #if 0 // XXX: check this
2109     /* XXX : not implemented */
2110     spr_register(env, SPR_620_PMR0, "PMR0",
2111                  SPR_NOACCESS, SPR_NOACCESS,
2112                  &spr_read_generic, &spr_write_generic,
2113                  0x00000000);
2114     /* XXX : not implemented */
2115     spr_register(env, SPR_620_PMR1, "PMR1",
2116                  SPR_NOACCESS, SPR_NOACCESS,
2117                  &spr_read_generic, &spr_write_generic,
2118                  0x00000000);
2119     /* XXX : not implemented */
2120     spr_register(env, SPR_620_PMR2, "PMR2",
2121                  SPR_NOACCESS, SPR_NOACCESS,
2122                  &spr_read_generic, &spr_write_generic,
2123                  0x00000000);
2124     /* XXX : not implemented */
2125     spr_register(env, SPR_620_PMR3, "PMR3",
2126                  SPR_NOACCESS, SPR_NOACCESS,
2127                  &spr_read_generic, &spr_write_generic,
2128                  0x00000000);
2129     /* XXX : not implemented */
2130     spr_register(env, SPR_620_PMR4, "PMR4",
2131                  SPR_NOACCESS, SPR_NOACCESS,
2132                  &spr_read_generic, &spr_write_generic,
2133                  0x00000000);
2134     /* XXX : not implemented */
2135     spr_register(env, SPR_620_PMR5, "PMR5",
2136                  SPR_NOACCESS, SPR_NOACCESS,
2137                  &spr_read_generic, &spr_write_generic,
2138                  0x00000000);
2139     /* XXX : not implemented */
2140     spr_register(env, SPR_620_PMR6, "PMR6",
2141                  SPR_NOACCESS, SPR_NOACCESS,
2142                  &spr_read_generic, &spr_write_generic,
2143                  0x00000000);
2144     /* XXX : not implemented */
2145     spr_register(env, SPR_620_PMR7, "PMR7",
2146                  SPR_NOACCESS, SPR_NOACCESS,
2147                  &spr_read_generic, &spr_write_generic,
2148                  0x00000000);
2149     /* XXX : not implemented */
2150     spr_register(env, SPR_620_PMR8, "PMR8",
2151                  SPR_NOACCESS, SPR_NOACCESS,
2152                  &spr_read_generic, &spr_write_generic,
2153                  0x00000000);
2154     /* XXX : not implemented */
2155     spr_register(env, SPR_620_PMR9, "PMR9",
2156                  SPR_NOACCESS, SPR_NOACCESS,
2157                  &spr_read_generic, &spr_write_generic,
2158                  0x00000000);
2159     /* XXX : not implemented */
2160     spr_register(env, SPR_620_PMRA, "PMR10",
2161                  SPR_NOACCESS, SPR_NOACCESS,
2162                  &spr_read_generic, &spr_write_generic,
2163                  0x00000000);
2164     /* XXX : not implemented */
2165     spr_register(env, SPR_620_PMRB, "PMR11",
2166                  SPR_NOACCESS, SPR_NOACCESS,
2167                  &spr_read_generic, &spr_write_generic,
2168                  0x00000000);
2169     /* XXX : not implemented */
2170     spr_register(env, SPR_620_PMRC, "PMR12",
2171                  SPR_NOACCESS, SPR_NOACCESS,
2172                  &spr_read_generic, &spr_write_generic,
2173                  0x00000000);
2174     /* XXX : not implemented */
2175     spr_register(env, SPR_620_PMRD, "PMR13",
2176                  SPR_NOACCESS, SPR_NOACCESS,
2177                  &spr_read_generic, &spr_write_generic,
2178                  0x00000000);
2179     /* XXX : not implemented */
2180     spr_register(env, SPR_620_PMRE, "PMR14",
2181                  SPR_NOACCESS, SPR_NOACCESS,
2182                  &spr_read_generic, &spr_write_generic,
2183                  0x00000000);
2184     /* XXX : not implemented */
2185     spr_register(env, SPR_620_PMRF, "PMR15",
2186                  SPR_NOACCESS, SPR_NOACCESS,
2187                  &spr_read_generic, &spr_write_generic,
2188                  0x00000000);
2189 #endif
2190     /* XXX : not implemented */
2191     spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2192                  SPR_NOACCESS, SPR_NOACCESS,
2193                  &spr_read_generic, &spr_write_generic,
2194                  0x00000000);
2195     /* XXX : not implemented */
2196     spr_register(env, SPR_620_L2CR, "L2CR",
2197                  SPR_NOACCESS, SPR_NOACCESS,
2198                  &spr_read_generic, &spr_write_generic,
2199                  0x00000000);
2200     /* XXX : not implemented */
2201     spr_register(env, SPR_620_L2SR, "L2SR",
2202                  SPR_NOACCESS, SPR_NOACCESS,
2203                  &spr_read_generic, &spr_write_generic,
2204                  0x00000000);
2205 }
2206 #endif /* defined (TARGET_PPC64) */
2207 
gen_spr_5xx_8xx(CPUPPCState * env)2208 static void gen_spr_5xx_8xx (CPUPPCState *env)
2209 {
2210     /* Exception processing */
2211     spr_register(env, SPR_DSISR, "DSISR",
2212                  SPR_NOACCESS, SPR_NOACCESS,
2213                  &spr_read_generic, &spr_write_generic,
2214                  0x00000000);
2215     spr_register(env, SPR_DAR, "DAR",
2216                  SPR_NOACCESS, SPR_NOACCESS,
2217                  &spr_read_generic, &spr_write_generic,
2218                  0x00000000);
2219     /* Timer */
2220     spr_register(env, SPR_DECR, "DECR",
2221                  SPR_NOACCESS, SPR_NOACCESS,
2222                  &spr_read_decr, &spr_write_decr,
2223                  0x00000000);
2224     /* XXX : not implemented */
2225     spr_register(env, SPR_MPC_EIE, "EIE",
2226                  SPR_NOACCESS, SPR_NOACCESS,
2227                  &spr_read_generic, &spr_write_generic,
2228                  0x00000000);
2229     /* XXX : not implemented */
2230     spr_register(env, SPR_MPC_EID, "EID",
2231                  SPR_NOACCESS, SPR_NOACCESS,
2232                  &spr_read_generic, &spr_write_generic,
2233                  0x00000000);
2234     /* XXX : not implemented */
2235     spr_register(env, SPR_MPC_NRI, "NRI",
2236                  SPR_NOACCESS, SPR_NOACCESS,
2237                  &spr_read_generic, &spr_write_generic,
2238                  0x00000000);
2239     /* XXX : not implemented */
2240     spr_register(env, SPR_MPC_CMPA, "CMPA",
2241                  SPR_NOACCESS, SPR_NOACCESS,
2242                  &spr_read_generic, &spr_write_generic,
2243                  0x00000000);
2244     /* XXX : not implemented */
2245     spr_register(env, SPR_MPC_CMPB, "CMPB",
2246                  SPR_NOACCESS, SPR_NOACCESS,
2247                  &spr_read_generic, &spr_write_generic,
2248                  0x00000000);
2249     /* XXX : not implemented */
2250     spr_register(env, SPR_MPC_CMPC, "CMPC",
2251                  SPR_NOACCESS, SPR_NOACCESS,
2252                  &spr_read_generic, &spr_write_generic,
2253                  0x00000000);
2254     /* XXX : not implemented */
2255     spr_register(env, SPR_MPC_CMPD, "CMPD",
2256                  SPR_NOACCESS, SPR_NOACCESS,
2257                  &spr_read_generic, &spr_write_generic,
2258                  0x00000000);
2259     /* XXX : not implemented */
2260     spr_register(env, SPR_MPC_ECR, "ECR",
2261                  SPR_NOACCESS, SPR_NOACCESS,
2262                  &spr_read_generic, &spr_write_generic,
2263                  0x00000000);
2264     /* XXX : not implemented */
2265     spr_register(env, SPR_MPC_DER, "DER",
2266                  SPR_NOACCESS, SPR_NOACCESS,
2267                  &spr_read_generic, &spr_write_generic,
2268                  0x00000000);
2269     /* XXX : not implemented */
2270     spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2271                  SPR_NOACCESS, SPR_NOACCESS,
2272                  &spr_read_generic, &spr_write_generic,
2273                  0x00000000);
2274     /* XXX : not implemented */
2275     spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2276                  SPR_NOACCESS, SPR_NOACCESS,
2277                  &spr_read_generic, &spr_write_generic,
2278                  0x00000000);
2279     /* XXX : not implemented */
2280     spr_register(env, SPR_MPC_CMPE, "CMPE",
2281                  SPR_NOACCESS, SPR_NOACCESS,
2282                  &spr_read_generic, &spr_write_generic,
2283                  0x00000000);
2284     /* XXX : not implemented */
2285     spr_register(env, SPR_MPC_CMPF, "CMPF",
2286                  SPR_NOACCESS, SPR_NOACCESS,
2287                  &spr_read_generic, &spr_write_generic,
2288                  0x00000000);
2289     /* XXX : not implemented */
2290     spr_register(env, SPR_MPC_CMPG, "CMPG",
2291                  SPR_NOACCESS, SPR_NOACCESS,
2292                  &spr_read_generic, &spr_write_generic,
2293                  0x00000000);
2294     /* XXX : not implemented */
2295     spr_register(env, SPR_MPC_CMPH, "CMPH",
2296                  SPR_NOACCESS, SPR_NOACCESS,
2297                  &spr_read_generic, &spr_write_generic,
2298                  0x00000000);
2299     /* XXX : not implemented */
2300     spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2301                  SPR_NOACCESS, SPR_NOACCESS,
2302                  &spr_read_generic, &spr_write_generic,
2303                  0x00000000);
2304     /* XXX : not implemented */
2305     spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2306                  SPR_NOACCESS, SPR_NOACCESS,
2307                  &spr_read_generic, &spr_write_generic,
2308                  0x00000000);
2309     /* XXX : not implemented */
2310     spr_register(env, SPR_MPC_BAR, "BAR",
2311                  SPR_NOACCESS, SPR_NOACCESS,
2312                  &spr_read_generic, &spr_write_generic,
2313                  0x00000000);
2314     /* XXX : not implemented */
2315     spr_register(env, SPR_MPC_DPDR, "DPDR",
2316                  SPR_NOACCESS, SPR_NOACCESS,
2317                  &spr_read_generic, &spr_write_generic,
2318                  0x00000000);
2319     /* XXX : not implemented */
2320     spr_register(env, SPR_MPC_IMMR, "IMMR",
2321                  SPR_NOACCESS, SPR_NOACCESS,
2322                  &spr_read_generic, &spr_write_generic,
2323                  0x00000000);
2324 }
2325 
gen_spr_5xx(CPUPPCState * env)2326 static void gen_spr_5xx (CPUPPCState *env)
2327 {
2328     /* XXX : not implemented */
2329     spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2330                  SPR_NOACCESS, SPR_NOACCESS,
2331                  &spr_read_generic, &spr_write_generic,
2332                  0x00000000);
2333     /* XXX : not implemented */
2334     spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2335                  SPR_NOACCESS, SPR_NOACCESS,
2336                  &spr_read_generic, &spr_write_generic,
2337                  0x00000000);
2338     /* XXX : not implemented */
2339     spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2340                  SPR_NOACCESS, SPR_NOACCESS,
2341                  &spr_read_generic, &spr_write_generic,
2342                  0x00000000);
2343     /* XXX : not implemented */
2344     spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2345                  SPR_NOACCESS, SPR_NOACCESS,
2346                  &spr_read_generic, &spr_write_generic,
2347                  0x00000000);
2348     /* XXX : not implemented */
2349     spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2350                  SPR_NOACCESS, SPR_NOACCESS,
2351                  &spr_read_generic, &spr_write_generic,
2352                  0x00000000);
2353     /* XXX : not implemented */
2354     spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2355                  SPR_NOACCESS, SPR_NOACCESS,
2356                  &spr_read_generic, &spr_write_generic,
2357                  0x00000000);
2358     /* XXX : not implemented */
2359     spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2360                  SPR_NOACCESS, SPR_NOACCESS,
2361                  &spr_read_generic, &spr_write_generic,
2362                  0x00000000);
2363     /* XXX : not implemented */
2364     spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2365                  SPR_NOACCESS, SPR_NOACCESS,
2366                  &spr_read_generic, &spr_write_generic,
2367                  0x00000000);
2368     /* XXX : not implemented */
2369     spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2370                  SPR_NOACCESS, SPR_NOACCESS,
2371                  &spr_read_generic, &spr_write_generic,
2372                  0x00000000);
2373     /* XXX : not implemented */
2374     spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2375                  SPR_NOACCESS, SPR_NOACCESS,
2376                  &spr_read_generic, &spr_write_generic,
2377                  0x00000000);
2378     /* XXX : not implemented */
2379     spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2380                  SPR_NOACCESS, SPR_NOACCESS,
2381                  &spr_read_generic, &spr_write_generic,
2382                  0x00000000);
2383     /* XXX : not implemented */
2384     spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2385                  SPR_NOACCESS, SPR_NOACCESS,
2386                  &spr_read_generic, &spr_write_generic,
2387                  0x00000000);
2388     /* XXX : not implemented */
2389     spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2390                  SPR_NOACCESS, SPR_NOACCESS,
2391                  &spr_read_generic, &spr_write_generic,
2392                  0x00000000);
2393     /* XXX : not implemented */
2394     spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2395                  SPR_NOACCESS, SPR_NOACCESS,
2396                  &spr_read_generic, &spr_write_generic,
2397                  0x00000000);
2398     /* XXX : not implemented */
2399     spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2400                  SPR_NOACCESS, SPR_NOACCESS,
2401                  &spr_read_generic, &spr_write_generic,
2402                  0x00000000);
2403     /* XXX : not implemented */
2404     spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2405                  SPR_NOACCESS, SPR_NOACCESS,
2406                  &spr_read_generic, &spr_write_generic,
2407                  0x00000000);
2408     /* XXX : not implemented */
2409     spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2410                  SPR_NOACCESS, SPR_NOACCESS,
2411                  &spr_read_generic, &spr_write_generic,
2412                  0x00000000);
2413     /* XXX : not implemented */
2414     spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2415                  SPR_NOACCESS, SPR_NOACCESS,
2416                  &spr_read_generic, &spr_write_generic,
2417                  0x00000000);
2418     /* XXX : not implemented */
2419     spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2420                  SPR_NOACCESS, SPR_NOACCESS,
2421                  &spr_read_generic, &spr_write_generic,
2422                  0x00000000);
2423     /* XXX : not implemented */
2424     spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2425                  SPR_NOACCESS, SPR_NOACCESS,
2426                  &spr_read_generic, &spr_write_generic,
2427                  0x00000000);
2428     /* XXX : not implemented */
2429     spr_register(env, SPR_RCPU_FPECR, "FPECR",
2430                  SPR_NOACCESS, SPR_NOACCESS,
2431                  &spr_read_generic, &spr_write_generic,
2432                  0x00000000);
2433 }
2434 
gen_spr_8xx(CPUPPCState * env)2435 static void gen_spr_8xx (CPUPPCState *env)
2436 {
2437     /* XXX : not implemented */
2438     spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2439                  SPR_NOACCESS, SPR_NOACCESS,
2440                  &spr_read_generic, &spr_write_generic,
2441                  0x00000000);
2442     /* XXX : not implemented */
2443     spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2444                  SPR_NOACCESS, SPR_NOACCESS,
2445                  &spr_read_generic, &spr_write_generic,
2446                  0x00000000);
2447     /* XXX : not implemented */
2448     spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2449                  SPR_NOACCESS, SPR_NOACCESS,
2450                  &spr_read_generic, &spr_write_generic,
2451                  0x00000000);
2452     /* XXX : not implemented */
2453     spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2454                  SPR_NOACCESS, SPR_NOACCESS,
2455                  &spr_read_generic, &spr_write_generic,
2456                  0x00000000);
2457     /* XXX : not implemented */
2458     spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2459                  SPR_NOACCESS, SPR_NOACCESS,
2460                  &spr_read_generic, &spr_write_generic,
2461                  0x00000000);
2462     /* XXX : not implemented */
2463     spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2464                  SPR_NOACCESS, SPR_NOACCESS,
2465                  &spr_read_generic, &spr_write_generic,
2466                  0x00000000);
2467     /* XXX : not implemented */
2468     spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2469                  SPR_NOACCESS, SPR_NOACCESS,
2470                  &spr_read_generic, &spr_write_generic,
2471                  0x00000000);
2472     /* XXX : not implemented */
2473     spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2474                  SPR_NOACCESS, SPR_NOACCESS,
2475                  &spr_read_generic, &spr_write_generic,
2476                  0x00000000);
2477     /* XXX : not implemented */
2478     spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2479                  SPR_NOACCESS, SPR_NOACCESS,
2480                  &spr_read_generic, &spr_write_generic,
2481                  0x00000000);
2482     /* XXX : not implemented */
2483     spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2484                  SPR_NOACCESS, SPR_NOACCESS,
2485                  &spr_read_generic, &spr_write_generic,
2486                  0x00000000);
2487     /* XXX : not implemented */
2488     spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2489                  SPR_NOACCESS, SPR_NOACCESS,
2490                  &spr_read_generic, &spr_write_generic,
2491                  0x00000000);
2492     /* XXX : not implemented */
2493     spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2494                  SPR_NOACCESS, SPR_NOACCESS,
2495                  &spr_read_generic, &spr_write_generic,
2496                  0x00000000);
2497     /* XXX : not implemented */
2498     spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2499                  SPR_NOACCESS, SPR_NOACCESS,
2500                  &spr_read_generic, &spr_write_generic,
2501                  0x00000000);
2502     /* XXX : not implemented */
2503     spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2504                  SPR_NOACCESS, SPR_NOACCESS,
2505                  &spr_read_generic, &spr_write_generic,
2506                  0x00000000);
2507     /* XXX : not implemented */
2508     spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2509                  SPR_NOACCESS, SPR_NOACCESS,
2510                  &spr_read_generic, &spr_write_generic,
2511                  0x00000000);
2512     /* XXX : not implemented */
2513     spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2514                  SPR_NOACCESS, SPR_NOACCESS,
2515                  &spr_read_generic, &spr_write_generic,
2516                  0x00000000);
2517     /* XXX : not implemented */
2518     spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2519                  SPR_NOACCESS, SPR_NOACCESS,
2520                  &spr_read_generic, &spr_write_generic,
2521                  0x00000000);
2522     /* XXX : not implemented */
2523     spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2524                  SPR_NOACCESS, SPR_NOACCESS,
2525                  &spr_read_generic, &spr_write_generic,
2526                  0x00000000);
2527     /* XXX : not implemented */
2528     spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2529                  SPR_NOACCESS, SPR_NOACCESS,
2530                  &spr_read_generic, &spr_write_generic,
2531                  0x00000000);
2532     /* XXX : not implemented */
2533     spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2534                  SPR_NOACCESS, SPR_NOACCESS,
2535                  &spr_read_generic, &spr_write_generic,
2536                  0x00000000);
2537     /* XXX : not implemented */
2538     spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2539                  SPR_NOACCESS, SPR_NOACCESS,
2540                  &spr_read_generic, &spr_write_generic,
2541                  0x00000000);
2542     /* XXX : not implemented */
2543     spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2544                  SPR_NOACCESS, SPR_NOACCESS,
2545                  &spr_read_generic, &spr_write_generic,
2546                  0x00000000);
2547     /* XXX : not implemented */
2548     spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2549                  SPR_NOACCESS, SPR_NOACCESS,
2550                  &spr_read_generic, &spr_write_generic,
2551                  0x00000000);
2552     /* XXX : not implemented */
2553     spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2554                  SPR_NOACCESS, SPR_NOACCESS,
2555                  &spr_read_generic, &spr_write_generic,
2556                  0x00000000);
2557     /* XXX : not implemented */
2558     spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2559                  SPR_NOACCESS, SPR_NOACCESS,
2560                  &spr_read_generic, &spr_write_generic,
2561                  0x00000000);
2562 }
2563 
2564 // XXX: TODO
2565 /*
2566  * AMR     => SPR 29 (Power 2.04)
2567  * CTRL    => SPR 136 (Power 2.04)
2568  * CTRL    => SPR 152 (Power 2.04)
2569  * SCOMC   => SPR 276 (64 bits ?)
2570  * SCOMD   => SPR 277 (64 bits ?)
2571  * TBU40   => SPR 286 (Power 2.04 hypv)
2572  * HSPRG0  => SPR 304 (Power 2.04 hypv)
2573  * HSPRG1  => SPR 305 (Power 2.04 hypv)
2574  * HDSISR  => SPR 306 (Power 2.04 hypv)
2575  * HDAR    => SPR 307 (Power 2.04 hypv)
2576  * PURR    => SPR 309 (Power 2.04 hypv)
2577  * HDEC    => SPR 310 (Power 2.04 hypv)
2578  * HIOR    => SPR 311 (hypv)
2579  * RMOR    => SPR 312 (970)
2580  * HRMOR   => SPR 313 (Power 2.04 hypv)
2581  * HSRR0   => SPR 314 (Power 2.04 hypv)
2582  * HSRR1   => SPR 315 (Power 2.04 hypv)
2583  * LPCR    => SPR 316 (970)
2584  * LPIDR   => SPR 317 (970)
2585  * EPR     => SPR 702 (Power 2.04 emb)
2586  * perf    => 768-783 (Power 2.04)
2587  * perf    => 784-799 (Power 2.04)
2588  * PPR     => SPR 896 (Power 2.04)
2589  * EPLC    => SPR 947 (Power 2.04 emb)
2590  * EPSC    => SPR 948 (Power 2.04 emb)
2591  * DABRX   => 1015    (Power 2.04 hypv)
2592  * FPECR   => SPR 1022 (?)
2593  * ... and more (thermal management, performance counters, ...)
2594  */
2595 
2596 /*****************************************************************************/
2597 /* Exception vectors models                                                  */
init_excp_4xx_real(CPUPPCState * env)2598 static void init_excp_4xx_real (CPUPPCState *env)
2599 {
2600 #if !defined(CONFIG_USER_ONLY)
2601     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2602     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2603     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2604     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2605     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2606     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2607     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2608     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2609     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2610     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2611     env->hreset_excp_prefix = 0x00000000UL;
2612     env->ivor_mask = 0x0000FFF0UL;
2613     env->ivpr_mask = 0xFFFF0000UL;
2614     /* Hardware reset vector */
2615     env->hreset_vector = 0xFFFFFFFCUL;
2616 #endif
2617 }
2618 
init_excp_4xx_softmmu(CPUPPCState * env)2619 static void init_excp_4xx_softmmu (CPUPPCState *env)
2620 {
2621 #if !defined(CONFIG_USER_ONLY)
2622     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2623     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2624     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2625     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2626     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2627     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2628     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2629     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2630     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2631     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2632     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2633     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2634     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2635     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2636     env->hreset_excp_prefix = 0x00000000UL;
2637     env->ivor_mask = 0x0000FFF0UL;
2638     env->ivpr_mask = 0xFFFF0000UL;
2639     /* Hardware reset vector */
2640     env->hreset_vector = 0xFFFFFFFCUL;
2641 #endif
2642 }
2643 
init_excp_MPC5xx(CPUPPCState * env)2644 static void init_excp_MPC5xx (CPUPPCState *env)
2645 {
2646 #if !defined(CONFIG_USER_ONLY)
2647     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2648     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2649     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2650     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2651     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2652     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2653     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2654     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2655     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2656     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2657     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2658     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2659     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2660     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2661     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2662     env->hreset_excp_prefix = 0x00000000UL;
2663     env->ivor_mask = 0x0000FFF0UL;
2664     env->ivpr_mask = 0xFFFF0000UL;
2665     /* Hardware reset vector */
2666     env->hreset_vector = 0xFFFFFFFCUL;
2667 #endif
2668 }
2669 
init_excp_MPC8xx(CPUPPCState * env)2670 static void init_excp_MPC8xx (CPUPPCState *env)
2671 {
2672 #if !defined(CONFIG_USER_ONLY)
2673     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2674     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2675     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2676     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2677     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2678     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2679     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2680     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2681     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2682     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2683     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2684     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2685     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2686     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2687     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2688     env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2689     env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2690     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2691     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2692     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2693     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2694     env->hreset_excp_prefix = 0x00000000UL;
2695     env->ivor_mask = 0x0000FFF0UL;
2696     env->ivpr_mask = 0xFFFF0000UL;
2697     /* Hardware reset vector */
2698     env->hreset_vector = 0xFFFFFFFCUL;
2699 #endif
2700 }
2701 
init_excp_G2(CPUPPCState * env)2702 static void init_excp_G2 (CPUPPCState *env)
2703 {
2704 #if !defined(CONFIG_USER_ONLY)
2705     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2706     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2707     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2708     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2709     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2710     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2711     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2712     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2713     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2714     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2715     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2716     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2717     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2718     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2719     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2720     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2721     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2722     env->hreset_excp_prefix = 0x00000000UL;
2723     /* Hardware reset vector */
2724     env->hreset_vector = 0xFFFFFFFCUL;
2725 #endif
2726 }
2727 
init_excp_e200(CPUPPCState * env)2728 static void init_excp_e200 (CPUPPCState *env)
2729 {
2730 #if !defined(CONFIG_USER_ONLY)
2731     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2732     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2733     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2734     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2735     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2736     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2737     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2738     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2739     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2740     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2741     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2742     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2743     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2744     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2745     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2746     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2747     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2748     env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2749     env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2750     env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2751     env->hreset_excp_prefix = 0x00000000UL;
2752     env->ivor_mask = 0x0000FFF7UL;
2753     env->ivpr_mask = 0xFFFF0000UL;
2754     /* Hardware reset vector */
2755     env->hreset_vector = 0xFFFFFFFCUL;
2756 #endif
2757 }
2758 
init_excp_BookE(CPUPPCState * env)2759 static void init_excp_BookE (CPUPPCState *env)
2760 {
2761 #if !defined(CONFIG_USER_ONLY)
2762     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2763     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2764     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2765     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2766     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2767     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2768     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2769     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2770     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2771     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2772     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2773     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2774     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2775     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2776     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2777     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2778     env->hreset_excp_prefix = 0x00000000UL;
2779     env->ivor_mask = 0x0000FFE0UL;
2780     env->ivpr_mask = 0xFFFF0000UL;
2781     /* Hardware reset vector */
2782     env->hreset_vector = 0xFFFFFFFCUL;
2783 #endif
2784 }
2785 
init_excp_601(CPUPPCState * env)2786 static void init_excp_601 (CPUPPCState *env)
2787 {
2788 #if !defined(CONFIG_USER_ONLY)
2789     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2790     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2791     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2792     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2793     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2794     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2795     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2796     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2797     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2798     env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2799     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2800     env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2801     env->hreset_excp_prefix = 0xFFF00000UL;
2802     /* Hardware reset vector */
2803     env->hreset_vector = 0x00000100UL;
2804 #endif
2805 }
2806 
init_excp_602(CPUPPCState * env)2807 static void init_excp_602 (CPUPPCState *env)
2808 {
2809 #if !defined(CONFIG_USER_ONLY)
2810     /* XXX: exception prefix has a special behavior on 602 */
2811     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2812     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2813     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2814     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2815     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2816     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2817     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2818     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2819     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2820     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2821     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2822     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2823     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2824     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2825     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2826     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2827     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2828     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2829     env->hreset_excp_prefix = 0xFFF00000UL;
2830     /* Hardware reset vector */
2831     env->hreset_vector = 0xFFFFFFFCUL;
2832 #endif
2833 }
2834 
init_excp_603(CPUPPCState * env)2835 static void init_excp_603 (CPUPPCState *env)
2836 {
2837 #if !defined(CONFIG_USER_ONLY)
2838     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2839     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2840     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2841     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2842     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2843     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2844     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2845     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2846     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2847     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2848     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2849     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2850     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2851     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2852     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2853     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2854     env->hreset_excp_prefix = 0x00000000UL;
2855     /* Hardware reset vector */
2856     env->hreset_vector = 0xFFFFFFFCUL;
2857 #endif
2858 }
2859 
init_excp_604(CPUPPCState * env)2860 static void init_excp_604 (CPUPPCState *env)
2861 {
2862 #if !defined(CONFIG_USER_ONLY)
2863     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2864     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2865     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2866     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2867     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2868     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2869     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2870     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2871     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2872     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2873     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2874     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2875     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2876     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2877     env->hreset_excp_prefix = 0xFFF00000UL;
2878     /* Hardware reset vector */
2879     env->hreset_vector = 0x00000100UL;
2880 #endif
2881 }
2882 
2883 #if defined(TARGET_PPC64)
init_excp_620(CPUPPCState * env)2884 static void init_excp_620 (CPUPPCState *env)
2885 {
2886 #if !defined(CONFIG_USER_ONLY)
2887     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2888     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2889     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2890     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2891     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2892     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2893     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2894     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2895     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2896     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2897     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2898     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2899     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2900     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2901     env->hreset_excp_prefix = 0xFFF00000UL;
2902     /* Hardware reset vector */
2903     env->hreset_vector = 0x0000000000000100ULL;
2904 #endif
2905 }
2906 #endif /* defined(TARGET_PPC64) */
2907 
init_excp_7x0(CPUPPCState * env)2908 static void init_excp_7x0 (CPUPPCState *env)
2909 {
2910 #if !defined(CONFIG_USER_ONLY)
2911     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2912     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2913     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2914     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2915     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2916     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2917     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2918     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2919     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2920     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2921     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2922     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2923     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2924     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2925     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2926     env->hreset_excp_prefix = 0x00000000UL;
2927     /* Hardware reset vector */
2928     env->hreset_vector = 0xFFFFFFFCUL