xref: /illumos-kvm-cmd/ppc-dis.c (revision 68396ea9)
1 /* ppc-dis.c -- Disassemble PowerPC instructions
2    Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
3    Free Software Foundation, Inc.
4    Written by Ian Lance Taylor, Cygnus Support
5 
6 This file is part of GDB, GAS, and the GNU binutils.
7 
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12 
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
16 the GNU General Public License for more details.
17 
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING.  If not,
20 see <http://www.gnu.org/licenses/>.  */
21 #include "dis-asm.h"
22 #define BFD_DEFAULT_TARGET_SIZE 64
23 
24 /* ppc.h -- Header file for PowerPC opcode table
25    Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
26    2007 Free Software Foundation, Inc.
27    Written by Ian Lance Taylor, Cygnus Support
28 
29 This file is part of GDB, GAS, and the GNU binutils.
30 
31 GDB, GAS, and the GNU binutils are free software; you can redistribute
32 them and/or modify them under the terms of the GNU General Public
33 License as published by the Free Software Foundation; either version
34 1, or (at your option) any later version.
35 
36 GDB, GAS, and the GNU binutils are distributed in the hope that they
37 will be useful, but WITHOUT ANY WARRANTY; without even the implied
38 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
39 the GNU General Public License for more details.
40 
41 You should have received a copy of the GNU General Public License
42 along with this file; see the file COPYING.  If not,
43 see <http://www.gnu.org/licenses/>.  */
44 
45 /* The opcode table is an array of struct powerpc_opcode.  */
46 
47 struct powerpc_opcode
48 {
49   /* The opcode name.  */
50   const char *name;
51 
52   /* The opcode itself.  Those bits which will be filled in with
53      operands are zeroes.  */
54   unsigned long opcode;
55 
56   /* The opcode mask.  This is used by the disassembler.  This is a
57      mask containing ones indicating those bits which must match the
58      opcode field, and zeroes indicating those bits which need not
59      match (and are presumably filled in by operands).  */
60   unsigned long mask;
61 
62   /* One bit flags for the opcode.  These are used to indicate which
63      specific processors support the instructions.  The defined values
64      are listed below.  */
65   unsigned long flags;
66 
67   /* An array of operand codes.  Each code is an index into the
68      operand table.  They appear in the order which the operands must
69      appear in assembly code, and are terminated by a zero.  */
70   unsigned char operands[8];
71 };
72 
73 /* The table itself is sorted by major opcode number, and is otherwise
74    in the order in which the disassembler should consider
75    instructions.  */
76 extern const struct powerpc_opcode powerpc_opcodes[];
77 extern const int powerpc_num_opcodes;
78 
79 /* Values defined for the flags field of a struct powerpc_opcode.  */
80 
81 /* Opcode is defined for the PowerPC architecture.  */
82 #define PPC_OPCODE_PPC			 1
83 
84 /* Opcode is defined for the POWER (RS/6000) architecture.  */
85 #define PPC_OPCODE_POWER		 2
86 
87 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
88 #define PPC_OPCODE_POWER2		 4
89 
90 /* Opcode is only defined on 32 bit architectures.  */
91 #define PPC_OPCODE_32			 8
92 
93 /* Opcode is only defined on 64 bit architectures.  */
94 #define PPC_OPCODE_64		      0x10
95 
96 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
97    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
98    but it also supports many additional POWER instructions.  */
99 #define PPC_OPCODE_601		      0x20
100 
101 /* Opcode is supported in both the Power and PowerPC architectures
102    (ie, compiler's -mcpu=common or assembler's -mcom).  */
103 #define PPC_OPCODE_COMMON	      0x40
104 
105 /* Opcode is supported for any Power or PowerPC platform (this is
106    for the assembler's -many option, and it eliminates duplicates).  */
107 #define PPC_OPCODE_ANY		      0x80
108 
109 /* Opcode is supported as part of the 64-bit bridge.  */
110 #define PPC_OPCODE_64_BRIDGE	     0x100
111 
112 /* Opcode is supported by Altivec Vector Unit */
113 #define PPC_OPCODE_ALTIVEC	     0x200
114 
115 /* Opcode is supported by PowerPC 403 processor.  */
116 #define PPC_OPCODE_403		     0x400
117 
118 /* Opcode is supported by PowerPC BookE processor.  */
119 #define PPC_OPCODE_BOOKE	     0x800
120 
121 /* Opcode is only supported by 64-bit PowerPC BookE processor.  */
122 #define PPC_OPCODE_BOOKE64	    0x1000
123 
124 /* Opcode is supported by PowerPC 440 processor.  */
125 #define PPC_OPCODE_440		    0x2000
126 
127 /* Opcode is only supported by Power4 architecture.  */
128 #define PPC_OPCODE_POWER4	    0x4000
129 
130 /* Opcode isn't supported by Power4 architecture.  */
131 #define PPC_OPCODE_NOPOWER4	    0x8000
132 
133 /* Opcode is only supported by POWERPC Classic architecture.  */
134 #define PPC_OPCODE_CLASSIC	   0x10000
135 
136 /* Opcode is only supported by e500x2 Core.  */
137 #define PPC_OPCODE_SPE		   0x20000
138 
139 /* Opcode is supported by e500x2 Integer select APU.  */
140 #define PPC_OPCODE_ISEL		   0x40000
141 
142 /* Opcode is an e500 SPE floating point instruction.  */
143 #define PPC_OPCODE_EFS		   0x80000
144 
145 /* Opcode is supported by branch locking APU.  */
146 #define PPC_OPCODE_BRLOCK	  0x100000
147 
148 /* Opcode is supported by performance monitor APU.  */
149 #define PPC_OPCODE_PMR		  0x200000
150 
151 /* Opcode is supported by cache locking APU.  */
152 #define PPC_OPCODE_CACHELCK	  0x400000
153 
154 /* Opcode is supported by machine check APU.  */
155 #define PPC_OPCODE_RFMCI	  0x800000
156 
157 /* Opcode is only supported by Power5 architecture.  */
158 #define PPC_OPCODE_POWER5	 0x1000000
159 
160 /* Opcode is supported by PowerPC e300 family.  */
161 #define PPC_OPCODE_E300          0x2000000
162 
163 /* Opcode is only supported by Power6 architecture.  */
164 #define PPC_OPCODE_POWER6	 0x4000000
165 
166 /* Opcode is only supported by PowerPC Cell family.  */
167 #define PPC_OPCODE_CELL		 0x8000000
168 
169 /* A macro to extract the major opcode from an instruction.  */
170 #define PPC_OP(i) (((i) >> 26) & 0x3f)
171 
172 /* The operands table is an array of struct powerpc_operand.  */
173 
174 struct powerpc_operand
175 {
176   /* A bitmask of bits in the operand.  */
177   unsigned int bitm;
178 
179   /* How far the operand is left shifted in the instruction.
180      -1 to indicate that BITM and SHIFT cannot be used to determine
181      where the operand goes in the insn.  */
182   int shift;
183 
184   /* Insertion function.  This is used by the assembler.  To insert an
185      operand value into an instruction, check this field.
186 
187      If it is NULL, execute
188 	 i |= (op & o->bitm) << o->shift;
189      (i is the instruction which we are filling in, o is a pointer to
190      this structure, and op is the operand value).
191 
192      If this field is not NULL, then simply call it with the
193      instruction and the operand value.  It will return the new value
194      of the instruction.  If the ERRMSG argument is not NULL, then if
195      the operand value is illegal, *ERRMSG will be set to a warning
196      string (the operand will be inserted in any case).  If the
197      operand value is legal, *ERRMSG will be unchanged (most operands
198      can accept any value).  */
199   unsigned long (*insert)
200     (unsigned long instruction, long op, int dialect, const char **errmsg);
201 
202   /* Extraction function.  This is used by the disassembler.  To
203      extract this operand type from an instruction, check this field.
204 
205      If it is NULL, compute
206 	 op = (i >> o->shift) & o->bitm;
207 	 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
208 	   sign_extend (op);
209      (i is the instruction, o is a pointer to this structure, and op
210      is the result).
211 
212      If this field is not NULL, then simply call it with the
213      instruction value.  It will return the value of the operand.  If
214      the INVALID argument is not NULL, *INVALID will be set to
215      non-zero if this operand type can not actually be extracted from
216      this operand (i.e., the instruction does not match).  If the
217      operand is valid, *INVALID will not be changed.  */
218   long (*extract) (unsigned long instruction, int dialect, int *invalid);
219 
220   /* One bit syntax flags.  */
221   unsigned long flags;
222 };
223 
224 /* Elements in the table are retrieved by indexing with values from
225    the operands field of the powerpc_opcodes table.  */
226 
227 extern const struct powerpc_operand powerpc_operands[];
228 extern const unsigned int num_powerpc_operands;
229 
230 /* Values defined for the flags field of a struct powerpc_operand.  */
231 
232 /* This operand takes signed values.  */
233 #define PPC_OPERAND_SIGNED (0x1)
234 
235 /* This operand takes signed values, but also accepts a full positive
236    range of values when running in 32 bit mode.  That is, if bits is
237    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
238    this flag is ignored.  */
239 #define PPC_OPERAND_SIGNOPT (0x2)
240 
241 /* This operand does not actually exist in the assembler input.  This
242    is used to support extended mnemonics such as mr, for which two
243    operands fields are identical.  The assembler should call the
244    insert function with any op value.  The disassembler should call
245    the extract function, ignore the return value, and check the value
246    placed in the valid argument.  */
247 #define PPC_OPERAND_FAKE (0x4)
248 
249 /* The next operand should be wrapped in parentheses rather than
250    separated from this one by a comma.  This is used for the load and
251    store instructions which want their operands to look like
252        reg,displacement(reg)
253    */
254 #define PPC_OPERAND_PARENS (0x8)
255 
256 /* This operand may use the symbolic names for the CR fields, which
257    are
258        lt  0	gt  1	eq  2	so  3	un  3
259        cr0 0	cr1 1	cr2 2	cr3 3
260        cr4 4	cr5 5	cr6 6	cr7 7
261    These may be combined arithmetically, as in cr2*4+gt.  These are
262    only supported on the PowerPC, not the POWER.  */
263 #define PPC_OPERAND_CR (0x10)
264 
265 /* This operand names a register.  The disassembler uses this to print
266    register names with a leading 'r'.  */
267 #define PPC_OPERAND_GPR (0x20)
268 
269 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
270 #define PPC_OPERAND_GPR_0 (0x40)
271 
272 /* This operand names a floating point register.  The disassembler
273    prints these with a leading 'f'.  */
274 #define PPC_OPERAND_FPR (0x80)
275 
276 /* This operand is a relative branch displacement.  The disassembler
277    prints these symbolically if possible.  */
278 #define PPC_OPERAND_RELATIVE (0x100)
279 
280 /* This operand is an absolute branch address.  The disassembler
281    prints these symbolically if possible.  */
282 #define PPC_OPERAND_ABSOLUTE (0x200)
283 
284 /* This operand is optional, and is zero if omitted.  This is used for
285    example, in the optional BF field in the comparison instructions.  The
286    assembler must count the number of operands remaining on the line,
287    and the number of operands remaining for the opcode, and decide
288    whether this operand is present or not.  The disassembler should
289    print this operand out only if it is not zero.  */
290 #define PPC_OPERAND_OPTIONAL (0x400)
291 
292 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
293    is omitted, then for the next operand use this operand value plus
294    1, ignoring the next operand field for the opcode.  This wretched
295    hack is needed because the Power rotate instructions can take
296    either 4 or 5 operands.  The disassembler should print this operand
297    out regardless of the PPC_OPERAND_OPTIONAL field.  */
298 #define PPC_OPERAND_NEXT (0x800)
299 
300 /* This operand should be regarded as a negative number for the
301    purposes of overflow checking (i.e., the normal most negative
302    number is disallowed and one more than the normal most positive
303    number is allowed).  This flag will only be set for a signed
304    operand.  */
305 #define PPC_OPERAND_NEGATIVE (0x1000)
306 
307 /* This operand names a vector unit register.  The disassembler
308    prints these with a leading 'v'.  */
309 #define PPC_OPERAND_VR (0x2000)
310 
311 /* This operand is for the DS field in a DS form instruction.  */
312 #define PPC_OPERAND_DS (0x4000)
313 
314 /* This operand is for the DQ field in a DQ form instruction.  */
315 #define PPC_OPERAND_DQ (0x8000)
316 
317 /* Valid range of operand is 0..n rather than 0..n-1.  */
318 #define PPC_OPERAND_PLUS1 (0x10000)
319 
320 /* The POWER and PowerPC assemblers use a few macros.  We keep them
321    with the operands table for simplicity.  The macro table is an
322    array of struct powerpc_macro.  */
323 
324 struct powerpc_macro
325 {
326   /* The macro name.  */
327   const char *name;
328 
329   /* The number of operands the macro takes.  */
330   unsigned int operands;
331 
332   /* One bit flags for the opcode.  These are used to indicate which
333      specific processors support the instructions.  The values are the
334      same as those for the struct powerpc_opcode flags field.  */
335   unsigned long flags;
336 
337   /* A format string to turn the macro into a normal instruction.
338      Each %N in the string is replaced with operand number N (zero
339      based).  */
340   const char *format;
341 };
342 
343 extern const struct powerpc_macro powerpc_macros[];
344 extern const int powerpc_num_macros;
345 
346 /* ppc-opc.c -- PowerPC opcode list
347    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
348    2005, 2006, 2007 Free Software Foundation, Inc.
349    Written by Ian Lance Taylor, Cygnus Support
350 
351    This file is part of GDB, GAS, and the GNU binutils.
352 
353    GDB, GAS, and the GNU binutils are free software; you can redistribute
354    them and/or modify them under the terms of the GNU General Public
355    License as published by the Free Software Foundation; either version
356    2, or (at your option) any later version.
357 
358    GDB, GAS, and the GNU binutils are distributed in the hope that they
359    will be useful, but WITHOUT ANY WARRANTY; without even the implied
360    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
361    the GNU General Public License for more details.
362 
363    You should have received a copy of the GNU General Public License
364    along with this file; see the file COPYING.
365    If not, see <http://www.gnu.org/licenses/>.  */
366 
367 /* This file holds the PowerPC opcode table.  The opcode table
368    includes almost all of the extended instruction mnemonics.  This
369    permits the disassembler to use them, and simplifies the assembler
370    logic, at the cost of increasing the table size.  The table is
371    strictly constant data, so the compiler should be able to put it in
372    the .text section.
373 
374    This file also holds the operand table.  All knowledge about
375    inserting operands into instructions and vice-versa is kept in this
376    file.  */
377 
378 /* Local insertion and extraction functions.  */
379 
380 static unsigned long insert_bat (unsigned long, long, int, const char **);
381 static long extract_bat (unsigned long, int, int *);
382 static unsigned long insert_bba (unsigned long, long, int, const char **);
383 static long extract_bba (unsigned long, int, int *);
384 static unsigned long insert_bdm (unsigned long, long, int, const char **);
385 static long extract_bdm (unsigned long, int, int *);
386 static unsigned long insert_bdp (unsigned long, long, int, const char **);
387 static long extract_bdp (unsigned long, int, int *);
388 static unsigned long insert_bo (unsigned long, long, int, const char **);
389 static long extract_bo (unsigned long, int, int *);
390 static unsigned long insert_boe (unsigned long, long, int, const char **);
391 static long extract_boe (unsigned long, int, int *);
392 static unsigned long insert_fxm (unsigned long, long, int, const char **);
393 static long extract_fxm (unsigned long, int, int *);
394 static unsigned long insert_mbe (unsigned long, long, int, const char **);
395 static long extract_mbe (unsigned long, int, int *);
396 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
397 static long extract_mb6 (unsigned long, int, int *);
398 static long extract_nb (unsigned long, int, int *);
399 static unsigned long insert_nsi (unsigned long, long, int, const char **);
400 static long extract_nsi (unsigned long, int, int *);
401 static unsigned long insert_ral (unsigned long, long, int, const char **);
402 static unsigned long insert_ram (unsigned long, long, int, const char **);
403 static unsigned long insert_raq (unsigned long, long, int, const char **);
404 static unsigned long insert_ras (unsigned long, long, int, const char **);
405 static unsigned long insert_rbs (unsigned long, long, int, const char **);
406 static long extract_rbs (unsigned long, int, int *);
407 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
408 static long extract_sh6 (unsigned long, int, int *);
409 static unsigned long insert_spr (unsigned long, long, int, const char **);
410 static long extract_spr (unsigned long, int, int *);
411 static unsigned long insert_sprg (unsigned long, long, int, const char **);
412 static long extract_sprg (unsigned long, int, int *);
413 static unsigned long insert_tbr (unsigned long, long, int, const char **);
414 static long extract_tbr (unsigned long, int, int *);
415 
416 /* The operands table.
417 
418    The fields are bitm, shift, insert, extract, flags.
419 
420    We used to put parens around the various additions, like the one
421    for BA just below.  However, that caused trouble with feeble
422    compilers with a limit on depth of a parenthesized expression, like
423    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
424    omit the parens, since the macros are never used in a context where
425    the addition will be ambiguous.  */
426 
427 const struct powerpc_operand powerpc_operands[] =
428 {
429   /* The zero index is used to indicate the end of the list of
430      operands.  */
431 #define UNUSED 0
432   { 0, 0, NULL, NULL, 0 },
433 
434   /* The BA field in an XL form instruction.  */
435 #define BA UNUSED + 1
436   /* The BI field in a B form or XL form instruction.  */
437 #define BI BA
438 #define BI_MASK (0x1f << 16)
439   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
440 
441   /* The BA field in an XL form instruction when it must be the same
442      as the BT field in the same instruction.  */
443 #define BAT BA + 1
444   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
445 
446   /* The BB field in an XL form instruction.  */
447 #define BB BAT + 1
448 #define BB_MASK (0x1f << 11)
449   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
450 
451   /* The BB field in an XL form instruction when it must be the same
452      as the BA field in the same instruction.  */
453 #define BBA BB + 1
454   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
455 
456   /* The BD field in a B form instruction.  The lower two bits are
457      forced to zero.  */
458 #define BD BBA + 1
459   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
460 
461   /* The BD field in a B form instruction when absolute addressing is
462      used.  */
463 #define BDA BD + 1
464   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
465 
466   /* The BD field in a B form instruction when the - modifier is used.
467      This sets the y bit of the BO field appropriately.  */
468 #define BDM BDA + 1
469   { 0xfffc, 0, insert_bdm, extract_bdm,
470       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
471 
472   /* The BD field in a B form instruction when the - modifier is used
473      and absolute address is used.  */
474 #define BDMA BDM + 1
475   { 0xfffc, 0, insert_bdm, extract_bdm,
476       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
477 
478   /* The BD field in a B form instruction when the + modifier is used.
479      This sets the y bit of the BO field appropriately.  */
480 #define BDP BDMA + 1
481   { 0xfffc, 0, insert_bdp, extract_bdp,
482       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
483 
484   /* The BD field in a B form instruction when the + modifier is used
485      and absolute addressing is used.  */
486 #define BDPA BDP + 1
487   { 0xfffc, 0, insert_bdp, extract_bdp,
488       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
489 
490   /* The BF field in an X or XL form instruction.  */
491 #define BF BDPA + 1
492   /* The CRFD field in an X form instruction.  */
493 #define CRFD BF
494   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
495 
496   /* The BF field in an X or XL form instruction.  */
497 #define BFF BF + 1
498   { 0x7, 23, NULL, NULL, 0 },
499 
500   /* An optional BF field.  This is used for comparison instructions,
501      in which an omitted BF field is taken as zero.  */
502 #define OBF BFF + 1
503   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
504 
505   /* The BFA field in an X or XL form instruction.  */
506 #define BFA OBF + 1
507   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
508 
509   /* The BO field in a B form instruction.  Certain values are
510      illegal.  */
511 #define BO BFA + 1
512 #define BO_MASK (0x1f << 21)
513   { 0x1f, 21, insert_bo, extract_bo, 0 },
514 
515   /* The BO field in a B form instruction when the + or - modifier is
516      used.  This is like the BO field, but it must be even.  */
517 #define BOE BO + 1
518   { 0x1e, 21, insert_boe, extract_boe, 0 },
519 
520 #define BH BOE + 1
521   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
522 
523   /* The BT field in an X or XL form instruction.  */
524 #define BT BH + 1
525   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
526 
527   /* The condition register number portion of the BI field in a B form
528      or XL form instruction.  This is used for the extended
529      conditional branch mnemonics, which set the lower two bits of the
530      BI field.  This field is optional.  */
531 #define CR BT + 1
532   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
533 
534   /* The CRB field in an X form instruction.  */
535 #define CRB CR + 1
536   /* The MB field in an M form instruction.  */
537 #define MB CRB
538 #define MB_MASK (0x1f << 6)
539   { 0x1f, 6, NULL, NULL, 0 },
540 
541   /* The CRFS field in an X form instruction.  */
542 #define CRFS CRB + 1
543   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
544 
545   /* The CT field in an X form instruction.  */
546 #define CT CRFS + 1
547   /* The MO field in an mbar instruction.  */
548 #define MO CT
549   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
550 
551   /* The D field in a D form instruction.  This is a displacement off
552      a register, and implies that the next operand is a register in
553      parentheses.  */
554 #define D CT + 1
555   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
556 
557   /* The DE field in a DE form instruction.  This is like D, but is 12
558      bits only.  */
559 #define DE D + 1
560   { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
561 
562   /* The DES field in a DES form instruction.  This is like DS, but is 14
563      bits only (12 stored.)  */
564 #define DES DE + 1
565   { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
566 
567   /* The DQ field in a DQ form instruction.  This is like D, but the
568      lower four bits are forced to zero. */
569 #define DQ DES + 1
570   { 0xfff0, 0, NULL, NULL,
571     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
572 
573   /* The DS field in a DS form instruction.  This is like D, but the
574      lower two bits are forced to zero.  */
575 #undef DS
576 #define DS DQ + 1
577   { 0xfffc, 0, NULL, NULL,
578     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
579 
580   /* The E field in a wrteei instruction.  */
581 #define E DS + 1
582   { 0x1, 15, NULL, NULL, 0 },
583 
584   /* The FL1 field in a POWER SC form instruction.  */
585 #define FL1 E + 1
586   /* The U field in an X form instruction.  */
587 #define U FL1
588   { 0xf, 12, NULL, NULL, 0 },
589 
590   /* The FL2 field in a POWER SC form instruction.  */
591 #define FL2 FL1 + 1
592   { 0x7, 2, NULL, NULL, 0 },
593 
594   /* The FLM field in an XFL form instruction.  */
595 #define FLM FL2 + 1
596   { 0xff, 17, NULL, NULL, 0 },
597 
598   /* The FRA field in an X or A form instruction.  */
599 #define FRA FLM + 1
600 #define FRA_MASK (0x1f << 16)
601   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
602 
603   /* The FRB field in an X or A form instruction.  */
604 #define FRB FRA + 1
605 #define FRB_MASK (0x1f << 11)
606   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
607 
608   /* The FRC field in an A form instruction.  */
609 #define FRC FRB + 1
610 #define FRC_MASK (0x1f << 6)
611   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
612 
613   /* The FRS field in an X form instruction or the FRT field in a D, X
614      or A form instruction.  */
615 #define FRS FRC + 1
616 #define FRT FRS
617   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
618 
619   /* The FXM field in an XFX instruction.  */
620 #define FXM FRS + 1
621   { 0xff, 12, insert_fxm, extract_fxm, 0 },
622 
623   /* Power4 version for mfcr.  */
624 #define FXM4 FXM + 1
625   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
626 
627   /* The L field in a D or X form instruction.  */
628 #define L FXM4 + 1
629   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
630 
631   /* The LEV field in a POWER SVC form instruction.  */
632 #define SVC_LEV L + 1
633   { 0x7f, 5, NULL, NULL, 0 },
634 
635   /* The LEV field in an SC form instruction.  */
636 #define LEV SVC_LEV + 1
637   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
638 
639   /* The LI field in an I form instruction.  The lower two bits are
640      forced to zero.  */
641 #define LI LEV + 1
642   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
643 
644   /* The LI field in an I form instruction when used as an absolute
645      address.  */
646 #define LIA LI + 1
647   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
648 
649   /* The LS field in an X (sync) form instruction.  */
650 #define LS LIA + 1
651   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
652 
653   /* The ME field in an M form instruction.  */
654 #define ME LS + 1
655 #define ME_MASK (0x1f << 1)
656   { 0x1f, 1, NULL, NULL, 0 },
657 
658   /* The MB and ME fields in an M form instruction expressed a single
659      operand which is a bitmask indicating which bits to select.  This
660      is a two operand form using PPC_OPERAND_NEXT.  See the
661      description in opcode/ppc.h for what this means.  */
662 #define MBE ME + 1
663   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
664   { -1, 0, insert_mbe, extract_mbe, 0 },
665 
666   /* The MB or ME field in an MD or MDS form instruction.  The high
667      bit is wrapped to the low end.  */
668 #define MB6 MBE + 2
669 #define ME6 MB6
670 #define MB6_MASK (0x3f << 5)
671   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
672 
673   /* The NB field in an X form instruction.  The value 32 is stored as
674      0.  */
675 #define NB MB6 + 1
676   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
677 
678   /* The NSI field in a D form instruction.  This is the same as the
679      SI field, only negated.  */
680 #define NSI NB + 1
681   { 0xffff, 0, insert_nsi, extract_nsi,
682       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
683 
684   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
685 #define RA NSI + 1
686 #define RA_MASK (0x1f << 16)
687   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
688 
689   /* As above, but 0 in the RA field means zero, not r0.  */
690 #define RA0 RA + 1
691   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
692 
693   /* The RA field in the DQ form lq instruction, which has special
694      value restrictions.  */
695 #define RAQ RA0 + 1
696   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
697 
698   /* The RA field in a D or X form instruction which is an updating
699      load, which means that the RA field may not be zero and may not
700      equal the RT field.  */
701 #define RAL RAQ + 1
702   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
703 
704   /* The RA field in an lmw instruction, which has special value
705      restrictions.  */
706 #define RAM RAL + 1
707   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
708 
709   /* The RA field in a D or X form instruction which is an updating
710      store or an updating floating point load, which means that the RA
711      field may not be zero.  */
712 #define RAS RAM + 1
713   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
714 
715   /* The RA field of the tlbwe instruction, which is optional.  */
716 #define RAOPT RAS + 1
717   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
718 
719   /* The RB field in an X, XO, M, or MDS form instruction.  */
720 #define RB RAOPT + 1
721 #define RB_MASK (0x1f << 11)
722   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
723 
724   /* The RB field in an X form instruction when it must be the same as
725      the RS field in the instruction.  This is used for extended
726      mnemonics like mr.  */
727 #define RBS RB + 1
728   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
729 
730   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
731      instruction or the RT field in a D, DS, X, XFX or XO form
732      instruction.  */
733 #define RS RBS + 1
734 #define RT RS
735 #define RT_MASK (0x1f << 21)
736   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
737 
738   /* The RS and RT fields of the DS form stq instruction, which have
739      special value restrictions.  */
740 #define RSQ RS + 1
741 #define RTQ RSQ
742   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
743 
744   /* The RS field of the tlbwe instruction, which is optional.  */
745 #define RSO RSQ + 1
746 #define RTO RSO
747   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
748 
749   /* The SH field in an X or M form instruction.  */
750 #define SH RSO + 1
751 #define SH_MASK (0x1f << 11)
752   /* The other UIMM field in a EVX form instruction.  */
753 #define EVUIMM SH
754   { 0x1f, 11, NULL, NULL, 0 },
755 
756   /* The SH field in an MD form instruction.  This is split.  */
757 #define SH6 SH + 1
758 #define SH6_MASK ((0x1f << 11) | (1 << 1))
759   { 0x3f, -1, insert_sh6, extract_sh6, 0 },
760 
761   /* The SH field of the tlbwe instruction, which is optional.  */
762 #define SHO SH6 + 1
763   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
764 
765   /* The SI field in a D form instruction.  */
766 #define SI SHO + 1
767   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
768 
769   /* The SI field in a D form instruction when we accept a wide range
770      of positive values.  */
771 #define SISIGNOPT SI + 1
772   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
773 
774   /* The SPR field in an XFX form instruction.  This is flipped--the
775      lower 5 bits are stored in the upper 5 and vice- versa.  */
776 #define SPR SISIGNOPT + 1
777 #define PMR SPR
778 #define SPR_MASK (0x3ff << 11)
779   { 0x3ff, 11, insert_spr, extract_spr, 0 },
780 
781   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
782 #define SPRBAT SPR + 1
783 #define SPRBAT_MASK (0x3 << 17)
784   { 0x3, 17, NULL, NULL, 0 },
785 
786   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
787 #define SPRG SPRBAT + 1
788   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
789 
790   /* The SR field in an X form instruction.  */
791 #define SR SPRG + 1
792   { 0xf, 16, NULL, NULL, 0 },
793 
794   /* The STRM field in an X AltiVec form instruction.  */
795 #define STRM SR + 1
796   { 0x3, 21, NULL, NULL, 0 },
797 
798   /* The SV field in a POWER SC form instruction.  */
799 #define SV STRM + 1
800   { 0x3fff, 2, NULL, NULL, 0 },
801 
802   /* The TBR field in an XFX form instruction.  This is like the SPR
803      field, but it is optional.  */
804 #define TBR SV + 1
805   { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
806 
807   /* The TO field in a D or X form instruction.  */
808 #define TO TBR + 1
809 #define TO_MASK (0x1f << 21)
810   { 0x1f, 21, NULL, NULL, 0 },
811 
812   /* The UI field in a D form instruction.  */
813 #define UI TO + 1
814   { 0xffff, 0, NULL, NULL, 0 },
815 
816   /* The VA field in a VA, VX or VXR form instruction.  */
817 #define VA UI + 1
818   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
819 
820   /* The VB field in a VA, VX or VXR form instruction.  */
821 #define VB VA + 1
822   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
823 
824   /* The VC field in a VA form instruction.  */
825 #define VC VB + 1
826   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
827 
828   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
829 #define VD VC + 1
830 #define VS VD
831   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
832 
833   /* The SIMM field in a VX form instruction.  */
834 #define SIMM VD + 1
835   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
836 
837   /* The UIMM field in a VX form instruction, and TE in Z form.  */
838 #define UIMM SIMM + 1
839 #define TE UIMM
840   { 0x1f, 16, NULL, NULL, 0 },
841 
842   /* The SHB field in a VA form instruction.  */
843 #define SHB UIMM + 1
844   { 0xf, 6, NULL, NULL, 0 },
845 
846   /* The other UIMM field in a half word EVX form instruction.  */
847 #define EVUIMM_2 SHB + 1
848   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
849 
850   /* The other UIMM field in a word EVX form instruction.  */
851 #define EVUIMM_4 EVUIMM_2 + 1
852   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
853 
854   /* The other UIMM field in a double EVX form instruction.  */
855 #define EVUIMM_8 EVUIMM_4 + 1
856   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
857 
858   /* The WS field.  */
859 #define WS EVUIMM_8 + 1
860   { 0x7, 11, NULL, NULL, 0 },
861 
862   /* The L field in an mtmsrd or A form instruction or W in an X form.  */
863 #define A_L WS + 1
864 #define W A_L
865   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
866 
867 #define RMC A_L + 1
868   { 0x3, 9, NULL, NULL, 0 },
869 
870 #define R RMC + 1
871   { 0x1, 16, NULL, NULL, 0 },
872 
873 #define SP R + 1
874   { 0x3, 19, NULL, NULL, 0 },
875 
876 #define S SP + 1
877   { 0x1, 20, NULL, NULL, 0 },
878 
879   /* SH field starting at bit position 16.  */
880 #define SH16 S + 1
881   /* The DCM and DGM fields in a Z form instruction.  */
882 #define DCM SH16
883 #define DGM DCM
884   { 0x3f, 10, NULL, NULL, 0 },
885 
886   /* The EH field in larx instruction.  */
887 #define EH SH16 + 1
888   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
889 
890   /* The L field in an mtfsf or XFL form instruction.  */
891 #define XFL_L EH + 1
892   { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
893 };
894 
895 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
896 					   / sizeof (powerpc_operands[0]));
897 
898 /* The functions used to insert and extract complicated operands.  */
899 
900 /* The BA field in an XL form instruction when it must be the same as
901    the BT field in the same instruction.  This operand is marked FAKE.
902    The insertion function just copies the BT field into the BA field,
903    and the extraction function just checks that the fields are the
904    same.  */
905 
906 static unsigned long
insert_bat(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)907 insert_bat (unsigned long insn,
908 	    long value ATTRIBUTE_UNUSED,
909 	    int dialect ATTRIBUTE_UNUSED,
910 	    const char **errmsg ATTRIBUTE_UNUSED)
911 {
912   return insn | (((insn >> 21) & 0x1f) << 16);
913 }
914 
915 static long
extract_bat(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)916 extract_bat (unsigned long insn,
917 	     int dialect ATTRIBUTE_UNUSED,
918 	     int *invalid)
919 {
920   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
921     *invalid = 1;
922   return 0;
923 }
924 
925 /* The BB field in an XL form instruction when it must be the same as
926    the BA field in the same instruction.  This operand is marked FAKE.
927    The insertion function just copies the BA field into the BB field,
928    and the extraction function just checks that the fields are the
929    same.  */
930 
931 static unsigned long
insert_bba(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)932 insert_bba (unsigned long insn,
933 	    long value ATTRIBUTE_UNUSED,
934 	    int dialect ATTRIBUTE_UNUSED,
935 	    const char **errmsg ATTRIBUTE_UNUSED)
936 {
937   return insn | (((insn >> 16) & 0x1f) << 11);
938 }
939 
940 static long
extract_bba(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)941 extract_bba (unsigned long insn,
942 	     int dialect ATTRIBUTE_UNUSED,
943 	     int *invalid)
944 {
945   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
946     *invalid = 1;
947   return 0;
948 }
949 
950 /* The BD field in a B form instruction when the - modifier is used.
951    This modifier means that the branch is not expected to be taken.
952    For chips built to versions of the architecture prior to version 2
953    (ie. not Power4 compatible), we set the y bit of the BO field to 1
954    if the offset is negative.  When extracting, we require that the y
955    bit be 1 and that the offset be positive, since if the y bit is 0
956    we just want to print the normal form of the instruction.
957    Power4 compatible targets use two bits, "a", and "t", instead of
958    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
959    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
960    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
961    for branch on CTR.  We only handle the taken/not-taken hint here.
962    Note that we don't relax the conditions tested here when
963    disassembling with -Many because insns using extract_bdm and
964    extract_bdp always occur in pairs.  One or the other will always
965    be valid.  */
966 
967 static unsigned long
insert_bdm(unsigned long insn,long value,int dialect,const char ** errmsg ATTRIBUTE_UNUSED)968 insert_bdm (unsigned long insn,
969 	    long value,
970 	    int dialect,
971 	    const char **errmsg ATTRIBUTE_UNUSED)
972 {
973   if ((dialect & PPC_OPCODE_POWER4) == 0)
974     {
975       if ((value & 0x8000) != 0)
976 	insn |= 1 << 21;
977     }
978   else
979     {
980       if ((insn & (0x14 << 21)) == (0x04 << 21))
981 	insn |= 0x02 << 21;
982       else if ((insn & (0x14 << 21)) == (0x10 << 21))
983 	insn |= 0x08 << 21;
984     }
985   return insn | (value & 0xfffc);
986 }
987 
988 static long
extract_bdm(unsigned long insn,int dialect,int * invalid)989 extract_bdm (unsigned long insn,
990 	     int dialect,
991 	     int *invalid)
992 {
993   if ((dialect & PPC_OPCODE_POWER4) == 0)
994     {
995       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
996 	*invalid = 1;
997     }
998   else
999     {
1000       if ((insn & (0x17 << 21)) != (0x06 << 21)
1001 	  && (insn & (0x1d << 21)) != (0x18 << 21))
1002 	*invalid = 1;
1003     }
1004 
1005   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1006 }
1007 
1008 /* The BD field in a B form instruction when the + modifier is used.
1009    This is like BDM, above, except that the branch is expected to be
1010    taken.  */
1011 
1012 static unsigned long
insert_bdp(unsigned long insn,long value,int dialect,const char ** errmsg ATTRIBUTE_UNUSED)1013 insert_bdp (unsigned long insn,
1014 	    long value,
1015 	    int dialect,
1016 	    const char **errmsg ATTRIBUTE_UNUSED)
1017 {
1018   if ((dialect & PPC_OPCODE_POWER4) == 0)
1019     {
1020       if ((value & 0x8000) == 0)
1021 	insn |= 1 << 21;
1022     }
1023   else
1024     {
1025       if ((insn & (0x14 << 21)) == (0x04 << 21))
1026 	insn |= 0x03 << 21;
1027       else if ((insn & (0x14 << 21)) == (0x10 << 21))
1028 	insn |= 0x09 << 21;
1029     }
1030   return insn | (value & 0xfffc);
1031 }
1032 
1033 static long
extract_bdp(unsigned long insn,int dialect,int * invalid)1034 extract_bdp (unsigned long insn,
1035 	     int dialect,
1036 	     int *invalid)
1037 {
1038   if ((dialect & PPC_OPCODE_POWER4) == 0)
1039     {
1040       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1041 	*invalid = 1;
1042     }
1043   else
1044     {
1045       if ((insn & (0x17 << 21)) != (0x07 << 21)
1046 	  && (insn & (0x1d << 21)) != (0x19 << 21))
1047 	*invalid = 1;
1048     }
1049 
1050   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1051 }
1052 
1053 /* Check for legal values of a BO field.  */
1054 
1055 static int
valid_bo(long value,int dialect,int extract)1056 valid_bo (long value, int dialect, int extract)
1057 {
1058   if ((dialect & PPC_OPCODE_POWER4) == 0)
1059     {
1060       int valid;
1061       /* Certain encodings have bits that are required to be zero.
1062 	 These are (z must be zero, y may be anything):
1063 	     001zy
1064 	     011zy
1065 	     1z00y
1066 	     1z01y
1067 	     1z1zz
1068       */
1069       switch (value & 0x14)
1070 	{
1071 	default:
1072 	case 0:
1073 	  valid = 1;
1074 	  break;
1075 	case 0x4:
1076 	  valid = (value & 0x2) == 0;
1077 	  break;
1078 	case 0x10:
1079 	  valid = (value & 0x8) == 0;
1080 	  break;
1081 	case 0x14:
1082 	  valid = value == 0x14;
1083 	  break;
1084 	}
1085       /* When disassembling with -Many, accept power4 encodings too.  */
1086       if (valid
1087 	  || (dialect & PPC_OPCODE_ANY) == 0
1088 	  || !extract)
1089 	return valid;
1090     }
1091 
1092   /* Certain encodings have bits that are required to be zero.
1093      These are (z must be zero, a & t may be anything):
1094 	 0000z
1095 	 0001z
1096 	 0100z
1097 	 0101z
1098 	 001at
1099 	 011at
1100 	 1a00t
1101 	 1a01t
1102 	 1z1zz
1103   */
1104   if ((value & 0x14) == 0)
1105     return (value & 0x1) == 0;
1106   else if ((value & 0x14) == 0x14)
1107     return value == 0x14;
1108   else
1109     return 1;
1110 }
1111 
1112 /* The BO field in a B form instruction.  Warn about attempts to set
1113    the field to an illegal value.  */
1114 
1115 static unsigned long
insert_bo(unsigned long insn,long value,int dialect,const char ** errmsg)1116 insert_bo (unsigned long insn,
1117 	   long value,
1118 	   int dialect,
1119 	   const char **errmsg)
1120 {
1121   if (!valid_bo (value, dialect, 0))
1122     *errmsg = _("invalid conditional option");
1123   return insn | ((value & 0x1f) << 21);
1124 }
1125 
1126 static long
extract_bo(unsigned long insn,int dialect,int * invalid)1127 extract_bo (unsigned long insn,
1128 	    int dialect,
1129 	    int *invalid)
1130 {
1131   long value;
1132 
1133   value = (insn >> 21) & 0x1f;
1134   if (!valid_bo (value, dialect, 1))
1135     *invalid = 1;
1136   return value;
1137 }
1138 
1139 /* The BO field in a B form instruction when the + or - modifier is
1140    used.  This is like the BO field, but it must be even.  When
1141    extracting it, we force it to be even.  */
1142 
1143 static unsigned long
insert_boe(unsigned long insn,long value,int dialect,const char ** errmsg)1144 insert_boe (unsigned long insn,
1145 	    long value,
1146 	    int dialect,
1147 	    const char **errmsg)
1148 {
1149   if (!valid_bo (value, dialect, 0))
1150     *errmsg = _("invalid conditional option");
1151   else if ((value & 1) != 0)
1152     *errmsg = _("attempt to set y bit when using + or - modifier");
1153 
1154   return insn | ((value & 0x1f) << 21);
1155 }
1156 
1157 static long
extract_boe(unsigned long insn,int dialect,int * invalid)1158 extract_boe (unsigned long insn,
1159 	     int dialect,
1160 	     int *invalid)
1161 {
1162   long value;
1163 
1164   value = (insn >> 21) & 0x1f;
1165   if (!valid_bo (value, dialect, 1))
1166     *invalid = 1;
1167   return value & 0x1e;
1168 }
1169 
1170 /* FXM mask in mfcr and mtcrf instructions.  */
1171 
1172 static unsigned long
insert_fxm(unsigned long insn,long value,int dialect,const char ** errmsg)1173 insert_fxm (unsigned long insn,
1174 	    long value,
1175 	    int dialect,
1176 	    const char **errmsg)
1177 {
1178   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1179      one bit of the mask field is set.  */
1180   if ((insn & (1 << 20)) != 0)
1181     {
1182       if (value == 0 || (value & -value) != value)
1183 	{
1184 	  *errmsg = _("invalid mask field");
1185 	  value = 0;
1186 	}
1187     }
1188 
1189   /* If the optional field on mfcr is missing that means we want to use
1190      the old form of the instruction that moves the whole cr.  In that
1191      case we'll have VALUE zero.  There doesn't seem to be a way to
1192      distinguish this from the case where someone writes mfcr %r3,0.  */
1193   else if (value == 0)
1194     ;
1195 
1196   /* If only one bit of the FXM field is set, we can use the new form
1197      of the instruction, which is faster.  Unlike the Power4 branch hint
1198      encoding, this is not backward compatible.  Do not generate the
1199      new form unless -mpower4 has been given, or -many and the two
1200      operand form of mfcr was used.  */
1201   else if ((value & -value) == value
1202 	   && ((dialect & PPC_OPCODE_POWER4) != 0
1203 	       || ((dialect & PPC_OPCODE_ANY) != 0
1204 		   && (insn & (0x3ff << 1)) == 19 << 1)))
1205     insn |= 1 << 20;
1206 
1207   /* Any other value on mfcr is an error.  */
1208   else if ((insn & (0x3ff << 1)) == 19 << 1)
1209     {
1210       *errmsg = _("ignoring invalid mfcr mask");
1211       value = 0;
1212     }
1213 
1214   return insn | ((value & 0xff) << 12);
1215 }
1216 
1217 static long
extract_fxm(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1218 extract_fxm (unsigned long insn,
1219 	     int dialect ATTRIBUTE_UNUSED,
1220 	     int *invalid)
1221 {
1222   long mask = (insn >> 12) & 0xff;
1223 
1224   /* Is this a Power4 insn?  */
1225   if ((insn & (1 << 20)) != 0)
1226     {
1227       /* Exactly one bit of MASK should be set.  */
1228       if (mask == 0 || (mask & -mask) != mask)
1229 	*invalid = 1;
1230     }
1231 
1232   /* Check that non-power4 form of mfcr has a zero MASK.  */
1233   else if ((insn & (0x3ff << 1)) == 19 << 1)
1234     {
1235       if (mask != 0)
1236 	*invalid = 1;
1237     }
1238 
1239   return mask;
1240 }
1241 
1242 /* The MB and ME fields in an M form instruction expressed as a single
1243    operand which is itself a bitmask.  The extraction function always
1244    marks it as invalid, since we never want to recognize an
1245    instruction which uses a field of this type.  */
1246 
1247 static unsigned long
insert_mbe(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1248 insert_mbe (unsigned long insn,
1249 	    long value,
1250 	    int dialect ATTRIBUTE_UNUSED,
1251 	    const char **errmsg)
1252 {
1253   unsigned long uval, mask;
1254   int mb, me, mx, count, last;
1255 
1256   uval = value;
1257 
1258   if (uval == 0)
1259     {
1260       *errmsg = _("illegal bitmask");
1261       return insn;
1262     }
1263 
1264   mb = 0;
1265   me = 32;
1266   if ((uval & 1) != 0)
1267     last = 1;
1268   else
1269     last = 0;
1270   count = 0;
1271 
1272   /* mb: location of last 0->1 transition */
1273   /* me: location of last 1->0 transition */
1274   /* count: # transitions */
1275 
1276   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1277     {
1278       if ((uval & mask) && !last)
1279 	{
1280 	  ++count;
1281 	  mb = mx;
1282 	  last = 1;
1283 	}
1284       else if (!(uval & mask) && last)
1285 	{
1286 	  ++count;
1287 	  me = mx;
1288 	  last = 0;
1289 	}
1290     }
1291   if (me == 0)
1292     me = 32;
1293 
1294   if (count != 2 && (count != 0 || ! last))
1295     *errmsg = _("illegal bitmask");
1296 
1297   return insn | (mb << 6) | ((me - 1) << 1);
1298 }
1299 
1300 static long
extract_mbe(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1301 extract_mbe (unsigned long insn,
1302 	     int dialect ATTRIBUTE_UNUSED,
1303 	     int *invalid)
1304 {
1305   long ret;
1306   int mb, me;
1307   int i;
1308 
1309   *invalid = 1;
1310 
1311   mb = (insn >> 6) & 0x1f;
1312   me = (insn >> 1) & 0x1f;
1313   if (mb < me + 1)
1314     {
1315       ret = 0;
1316       for (i = mb; i <= me; i++)
1317 	ret |= 1L << (31 - i);
1318     }
1319   else if (mb == me + 1)
1320     ret = ~0;
1321   else /* (mb > me + 1) */
1322     {
1323       ret = ~0;
1324       for (i = me + 1; i < mb; i++)
1325 	ret &= ~(1L << (31 - i));
1326     }
1327   return ret;
1328 }
1329 
1330 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1331    is wrapped to the low end.  */
1332 
1333 static unsigned long
insert_mb6(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1334 insert_mb6 (unsigned long insn,
1335 	    long value,
1336 	    int dialect ATTRIBUTE_UNUSED,
1337 	    const char **errmsg ATTRIBUTE_UNUSED)
1338 {
1339   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1340 }
1341 
1342 static long
extract_mb6(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1343 extract_mb6 (unsigned long insn,
1344 	     int dialect ATTRIBUTE_UNUSED,
1345 	     int *invalid ATTRIBUTE_UNUSED)
1346 {
1347   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1348 }
1349 
1350 /* The NB field in an X form instruction.  The value 32 is stored as
1351    0.  */
1352 
1353 static long
extract_nb(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1354 extract_nb (unsigned long insn,
1355 	    int dialect ATTRIBUTE_UNUSED,
1356 	    int *invalid ATTRIBUTE_UNUSED)
1357 {
1358   long ret;
1359 
1360   ret = (insn >> 11) & 0x1f;
1361   if (ret == 0)
1362     ret = 32;
1363   return ret;
1364 }
1365 
1366 /* The NSI field in a D form instruction.  This is the same as the SI
1367    field, only negated.  The extraction function always marks it as
1368    invalid, since we never want to recognize an instruction which uses
1369    a field of this type.  */
1370 
1371 static unsigned long
insert_nsi(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1372 insert_nsi (unsigned long insn,
1373 	    long value,
1374 	    int dialect ATTRIBUTE_UNUSED,
1375 	    const char **errmsg ATTRIBUTE_UNUSED)
1376 {
1377   return insn | (-value & 0xffff);
1378 }
1379 
1380 static long
extract_nsi(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1381 extract_nsi (unsigned long insn,
1382 	     int dialect ATTRIBUTE_UNUSED,
1383 	     int *invalid)
1384 {
1385   *invalid = 1;
1386   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1387 }
1388 
1389 /* The RA field in a D or X form instruction which is an updating
1390    load, which means that the RA field may not be zero and may not
1391    equal the RT field.  */
1392 
1393 static unsigned long
insert_ral(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1394 insert_ral (unsigned long insn,
1395 	    long value,
1396 	    int dialect ATTRIBUTE_UNUSED,
1397 	    const char **errmsg)
1398 {
1399   if (value == 0
1400       || (unsigned long) value == ((insn >> 21) & 0x1f))
1401     *errmsg = "invalid register operand when updating";
1402   return insn | ((value & 0x1f) << 16);
1403 }
1404 
1405 /* The RA field in an lmw instruction, which has special value
1406    restrictions.  */
1407 
1408 static unsigned long
insert_ram(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1409 insert_ram (unsigned long insn,
1410 	    long value,
1411 	    int dialect ATTRIBUTE_UNUSED,
1412 	    const char **errmsg)
1413 {
1414   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1415     *errmsg = _("index register in load range");
1416   return insn | ((value & 0x1f) << 16);
1417 }
1418 
1419 /* The RA field in the DQ form lq instruction, which has special
1420    value restrictions.  */
1421 
1422 static unsigned long
insert_raq(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1423 insert_raq (unsigned long insn,
1424 	    long value,
1425 	    int dialect ATTRIBUTE_UNUSED,
1426 	    const char **errmsg)
1427 {
1428   long rtvalue = (insn & RT_MASK) >> 21;
1429 
1430   if (value == rtvalue)
1431     *errmsg = _("source and target register operands must be different");
1432   return insn | ((value & 0x1f) << 16);
1433 }
1434 
1435 /* The RA field in a D or X form instruction which is an updating
1436    store or an updating floating point load, which means that the RA
1437    field may not be zero.  */
1438 
1439 static unsigned long
insert_ras(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1440 insert_ras (unsigned long insn,
1441 	    long value,
1442 	    int dialect ATTRIBUTE_UNUSED,
1443 	    const char **errmsg)
1444 {
1445   if (value == 0)
1446     *errmsg = _("invalid register operand when updating");
1447   return insn | ((value & 0x1f) << 16);
1448 }
1449 
1450 /* The RB field in an X form instruction when it must be the same as
1451    the RS field in the instruction.  This is used for extended
1452    mnemonics like mr.  This operand is marked FAKE.  The insertion
1453    function just copies the BT field into the BA field, and the
1454    extraction function just checks that the fields are the same.  */
1455 
1456 static unsigned long
insert_rbs(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1457 insert_rbs (unsigned long insn,
1458 	    long value ATTRIBUTE_UNUSED,
1459 	    int dialect ATTRIBUTE_UNUSED,
1460 	    const char **errmsg ATTRIBUTE_UNUSED)
1461 {
1462   return insn | (((insn >> 21) & 0x1f) << 11);
1463 }
1464 
1465 static long
extract_rbs(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1466 extract_rbs (unsigned long insn,
1467 	     int dialect ATTRIBUTE_UNUSED,
1468 	     int *invalid)
1469 {
1470   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1471     *invalid = 1;
1472   return 0;
1473 }
1474 
1475 /* The SH field in an MD form instruction.  This is split.  */
1476 
1477 static unsigned long
insert_sh6(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1478 insert_sh6 (unsigned long insn,
1479 	    long value,
1480 	    int dialect ATTRIBUTE_UNUSED,
1481 	    const char **errmsg ATTRIBUTE_UNUSED)
1482 {
1483   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1484 }
1485 
1486 static long
extract_sh6(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1487 extract_sh6 (unsigned long insn,
1488 	     int dialect ATTRIBUTE_UNUSED,
1489 	     int *invalid ATTRIBUTE_UNUSED)
1490 {
1491   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1492 }
1493 
1494 /* The SPR field in an XFX form instruction.  This is flipped--the
1495    lower 5 bits are stored in the upper 5 and vice- versa.  */
1496 
1497 static unsigned long
insert_spr(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1498 insert_spr (unsigned long insn,
1499 	    long value,
1500 	    int dialect ATTRIBUTE_UNUSED,
1501 	    const char **errmsg ATTRIBUTE_UNUSED)
1502 {
1503   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1504 }
1505 
1506 static long
extract_spr(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1507 extract_spr (unsigned long insn,
1508 	     int dialect ATTRIBUTE_UNUSED,
1509 	     int *invalid ATTRIBUTE_UNUSED)
1510 {
1511   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1512 }
1513 
1514 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1515 
1516 static unsigned long
insert_sprg(unsigned long insn,long value,int dialect,const char ** errmsg)1517 insert_sprg (unsigned long insn,
1518 	     long value,
1519 	     int dialect,
1520 	     const char **errmsg)
1521 {
1522   /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1523      as a synonym.  If ever a 405 specific dialect is added this
1524      check should use that instead.  */
1525   if (value > 7
1526       || (value > 3
1527 	  && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1528     *errmsg = _("invalid sprg number");
1529 
1530   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1531      user mode.  Anything else must use spr 272..279.  */
1532   if (value <= 3 || (insn & 0x100) != 0)
1533     value |= 0x10;
1534 
1535   return insn | ((value & 0x17) << 16);
1536 }
1537 
1538 static long
extract_sprg(unsigned long insn,int dialect,int * invalid)1539 extract_sprg (unsigned long insn,
1540 	      int dialect,
1541 	      int *invalid)
1542 {
1543   unsigned long val = (insn >> 16) & 0x1f;
1544 
1545   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1546      If not BOOKE or 405, then both use only 272..275.  */
1547   if (val <= 3
1548       || (val < 0x10 && (insn & 0x100) != 0)
1549       || (val - 0x10 > 3
1550 	  && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1551     *invalid = 1;
1552   return val & 7;
1553 }
1554 
1555 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1556    is optional.  When TBR is omitted, it must be inserted as 268 (the
1557    magic number of the TB register).  These functions treat 0
1558    (indicating an omitted optional operand) as 268.  This means that
1559    ``mftb 4,0'' is not handled correctly.  This does not matter very
1560    much, since the architecture manual does not define mftb as
1561    accepting any values other than 268 or 269.  */
1562 
1563 #define TB (268)
1564 
1565 static unsigned long
insert_tbr(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1566 insert_tbr (unsigned long insn,
1567 	    long value,
1568 	    int dialect ATTRIBUTE_UNUSED,
1569 	    const char **errmsg ATTRIBUTE_UNUSED)
1570 {
1571   if (value == 0)
1572     value = TB;
1573   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1574 }
1575 
1576 static long
extract_tbr(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1577 extract_tbr (unsigned long insn,
1578 	     int dialect ATTRIBUTE_UNUSED,
1579 	     int *invalid ATTRIBUTE_UNUSED)
1580 {
1581   long ret;
1582 
1583   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1584   if (ret == TB)
1585     ret = 0;
1586   return ret;
1587 }
1588 
1589 /* Macros used to form opcodes.  */
1590 
1591 /* The main opcode.  */
1592 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1593 #define OP_MASK OP (0x3f)
1594 
1595 /* The main opcode combined with a trap code in the TO field of a D
1596    form instruction.  Used for extended mnemonics for the trap
1597    instructions.  */
1598 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1599 #define OPTO_MASK (OP_MASK | TO_MASK)
1600 
1601 /* The main opcode combined with a comparison size bit in the L field
1602    of a D form or X form instruction.  Used for extended mnemonics for
1603    the comparison instructions.  */
1604 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1605 #define OPL_MASK OPL (0x3f,1)
1606 
1607 /* An A form instruction.  */
1608 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1609 #define A_MASK A (0x3f, 0x1f, 1)
1610 
1611 /* An A_MASK with the FRB field fixed.  */
1612 #define AFRB_MASK (A_MASK | FRB_MASK)
1613 
1614 /* An A_MASK with the FRC field fixed.  */
1615 #define AFRC_MASK (A_MASK | FRC_MASK)
1616 
1617 /* An A_MASK with the FRA and FRC fields fixed.  */
1618 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1619 
1620 /* An AFRAFRC_MASK, but with L bit clear.  */
1621 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1622 
1623 /* A B form instruction.  */
1624 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1625 #define B_MASK B (0x3f, 1, 1)
1626 
1627 /* A B form instruction setting the BO field.  */
1628 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1629 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1630 
1631 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1632    matching a conditional branch regardless of the setting of the y
1633    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1634 #define Y_MASK   (((unsigned long) 1) << 21)
1635 #define AT1_MASK (((unsigned long) 3) << 21)
1636 #define AT2_MASK (((unsigned long) 9) << 21)
1637 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1638 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1639 
1640 /* A B form instruction setting the BO field and the condition bits of
1641    the BI field.  */
1642 #define BBOCB(op, bo, cb, aa, lk) \
1643   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1644 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1645 
1646 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1647 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1648 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1649 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1650 
1651 /* A BBOYCB_MASK in which the BI field is fixed.  */
1652 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1653 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1654 
1655 /* An Context form instruction.  */
1656 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1657 #define CTX_MASK CTX(0x3f, 0x7)
1658 
1659 /* An User Context form instruction.  */
1660 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1661 #define UCTX_MASK UCTX(0x3f, 0x1f)
1662 
1663 /* The main opcode mask with the RA field clear.  */
1664 #define DRA_MASK (OP_MASK | RA_MASK)
1665 
1666 /* A DS form instruction.  */
1667 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1668 #define DS_MASK DSO (0x3f, 3)
1669 
1670 /* A DE form instruction.  */
1671 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1672 #define DE_MASK DEO (0x3e, 0xf)
1673 
1674 /* An EVSEL form instruction.  */
1675 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1676 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1677 
1678 /* An M form instruction.  */
1679 #define M(op, rc) (OP (op) | ((rc) & 1))
1680 #define M_MASK M (0x3f, 1)
1681 
1682 /* An M form instruction with the ME field specified.  */
1683 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1684 
1685 /* An M_MASK with the MB and ME fields fixed.  */
1686 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1687 
1688 /* An M_MASK with the SH and ME fields fixed.  */
1689 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1690 
1691 /* An MD form instruction.  */
1692 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1693 #define MD_MASK MD (0x3f, 0x7, 1)
1694 
1695 /* An MD_MASK with the MB field fixed.  */
1696 #define MDMB_MASK (MD_MASK | MB6_MASK)
1697 
1698 /* An MD_MASK with the SH field fixed.  */
1699 #define MDSH_MASK (MD_MASK | SH6_MASK)
1700 
1701 /* An MDS form instruction.  */
1702 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1703 #define MDS_MASK MDS (0x3f, 0xf, 1)
1704 
1705 /* An MDS_MASK with the MB field fixed.  */
1706 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1707 
1708 /* An SC form instruction.  */
1709 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1710 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1711 
1712 /* An VX form instruction.  */
1713 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1714 
1715 /* The mask for an VX form instruction.  */
1716 #define VX_MASK	VX(0x3f, 0x7ff)
1717 
1718 /* An VA form instruction.  */
1719 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1720 
1721 /* The mask for an VA form instruction.  */
1722 #define VXA_MASK VXA(0x3f, 0x3f)
1723 
1724 /* An VXR form instruction.  */
1725 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1726 
1727 /* The mask for a VXR form instruction.  */
1728 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1729 
1730 /* An X form instruction.  */
1731 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1732 
1733 /* A Z form instruction.  */
1734 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1735 
1736 /* An X form instruction with the RC bit specified.  */
1737 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1738 
1739 /* A Z form instruction with the RC bit specified.  */
1740 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1741 
1742 /* The mask for an X form instruction.  */
1743 #define X_MASK XRC (0x3f, 0x3ff, 1)
1744 
1745 /* The mask for a Z form instruction.  */
1746 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1747 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1748 
1749 /* An X_MASK with the RA field fixed.  */
1750 #define XRA_MASK (X_MASK | RA_MASK)
1751 
1752 /* An XRA_MASK with the W field clear.  */
1753 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1754 
1755 /* An X_MASK with the RB field fixed.  */
1756 #define XRB_MASK (X_MASK | RB_MASK)
1757 
1758 /* An X_MASK with the RT field fixed.  */
1759 #define XRT_MASK (X_MASK | RT_MASK)
1760 
1761 /* An XRT_MASK mask with the L bits clear.  */
1762 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1763 
1764 /* An X_MASK with the RA and RB fields fixed.  */
1765 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1766 
1767 /* An XRARB_MASK, but with the L bit clear.  */
1768 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1769 
1770 /* An X_MASK with the RT and RA fields fixed.  */
1771 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1772 
1773 /* An XRTRA_MASK, but with L bit clear.  */
1774 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1775 
1776 /* An X form instruction with the L bit specified.  */
1777 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1778 
1779 /* The mask for an X form comparison instruction.  */
1780 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1781 
1782 /* The mask for an X form comparison instruction with the L field
1783    fixed.  */
1784 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1785 
1786 /* An X form trap instruction with the TO field specified.  */
1787 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1788 #define XTO_MASK (X_MASK | TO_MASK)
1789 
1790 /* An X form tlb instruction with the SH field specified.  */
1791 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1792 #define XTLB_MASK (X_MASK | SH_MASK)
1793 
1794 /* An X form sync instruction.  */
1795 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1796 
1797 /* An X form sync instruction with everything filled in except the LS field.  */
1798 #define XSYNC_MASK (0xff9fffff)
1799 
1800 /* An X_MASK, but with the EH bit clear.  */
1801 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1802 
1803 /* An X form AltiVec dss instruction.  */
1804 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1805 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1806 
1807 /* An XFL form instruction.  */
1808 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1809 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
1810 
1811 /* An X form isel instruction.  */
1812 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1813 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1814 
1815 /* An XL form instruction with the LK field set to 0.  */
1816 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1817 
1818 /* An XL form instruction which uses the LK field.  */
1819 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1820 
1821 /* The mask for an XL form instruction.  */
1822 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1823 
1824 /* An XL form instruction which explicitly sets the BO field.  */
1825 #define XLO(op, bo, xop, lk) \
1826   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1827 #define XLO_MASK (XL_MASK | BO_MASK)
1828 
1829 /* An XL form instruction which explicitly sets the y bit of the BO
1830    field.  */
1831 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1832 #define XLYLK_MASK (XL_MASK | Y_MASK)
1833 
1834 /* An XL form instruction which sets the BO field and the condition
1835    bits of the BI field.  */
1836 #define XLOCB(op, bo, cb, xop, lk) \
1837   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1838 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1839 
1840 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1841 #define XLBB_MASK (XL_MASK | BB_MASK)
1842 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1843 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1844 
1845 /* A mask for branch instructions using the BH field.  */
1846 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1847 
1848 /* An XL_MASK with the BO and BB fields fixed.  */
1849 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1850 
1851 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1852 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1853 
1854 /* An XO form instruction.  */
1855 #define XO(op, xop, oe, rc) \
1856   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1857 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1858 
1859 /* An XO_MASK with the RB field fixed.  */
1860 #define XORB_MASK (XO_MASK | RB_MASK)
1861 
1862 /* An XS form instruction.  */
1863 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1864 #define XS_MASK XS (0x3f, 0x1ff, 1)
1865 
1866 /* A mask for the FXM version of an XFX form instruction.  */
1867 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1868 
1869 /* An XFX form instruction with the FXM field filled in.  */
1870 #define XFXM(op, xop, fxm, p4) \
1871   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1872    | ((unsigned long)(p4) << 20))
1873 
1874 /* An XFX form instruction with the SPR field filled in.  */
1875 #define XSPR(op, xop, spr) \
1876   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1877 #define XSPR_MASK (X_MASK | SPR_MASK)
1878 
1879 /* An XFX form instruction with the SPR field filled in except for the
1880    SPRBAT field.  */
1881 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1882 
1883 /* An XFX form instruction with the SPR field filled in except for the
1884    SPRG field.  */
1885 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1886 
1887 /* An X form instruction with everything filled in except the E field.  */
1888 #define XE_MASK (0xffff7fff)
1889 
1890 /* An X form user context instruction.  */
1891 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1892 #define XUC_MASK      XUC(0x3f, 0x1f)
1893 
1894 /* The BO encodings used in extended conditional branch mnemonics.  */
1895 #define BODNZF	(0x0)
1896 #define BODNZFP	(0x1)
1897 #define BODZF	(0x2)
1898 #define BODZFP	(0x3)
1899 #define BODNZT	(0x8)
1900 #define BODNZTP	(0x9)
1901 #define BODZT	(0xa)
1902 #define BODZTP	(0xb)
1903 
1904 #define BOF	(0x4)
1905 #define BOFP	(0x5)
1906 #define BOFM4	(0x6)
1907 #define BOFP4	(0x7)
1908 #define BOT	(0xc)
1909 #define BOTP	(0xd)
1910 #define BOTM4	(0xe)
1911 #define BOTP4	(0xf)
1912 
1913 #define BODNZ	(0x10)
1914 #define BODNZP	(0x11)
1915 #define BODZ	(0x12)
1916 #define BODZP	(0x13)
1917 #define BODNZM4 (0x18)
1918 #define BODNZP4 (0x19)
1919 #define BODZM4	(0x1a)
1920 #define BODZP4	(0x1b)
1921 
1922 #define BOU	(0x14)
1923 
1924 /* The BI condition bit encodings used in extended conditional branch
1925    mnemonics.  */
1926 #define CBLT	(0)
1927 #define CBGT	(1)
1928 #define CBEQ	(2)
1929 #define CBSO	(3)
1930 
1931 /* The TO encodings used in extended trap mnemonics.  */
1932 #define TOLGT	(0x1)
1933 #define TOLLT	(0x2)
1934 #define TOEQ	(0x4)
1935 #define TOLGE	(0x5)
1936 #define TOLNL	(0x5)
1937 #define TOLLE	(0x6)
1938 #define TOLNG	(0x6)
1939 #define TOGT	(0x8)
1940 #define TOGE	(0xc)
1941 #define TONL	(0xc)
1942 #define TOLT	(0x10)
1943 #define TOLE	(0x14)
1944 #define TONG	(0x14)
1945 #define TONE	(0x18)
1946 #define TOU	(0x1f)
1947 
1948 /* Smaller names for the flags so each entry in the opcodes table will
1949    fit on a single line.  */
1950 #undef	PPC
1951 #define PPC     PPC_OPCODE_PPC
1952 #define PPCCOM	PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1953 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1954 #define POWER4	PPC_OPCODE_POWER4
1955 #define POWER5	PPC_OPCODE_POWER5
1956 #define POWER6	PPC_OPCODE_POWER6
1957 #define CELL	PPC_OPCODE_CELL
1958 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1959 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1960 #define PPC403	PPC_OPCODE_403
1961 #define PPC405	PPC403
1962 #define PPC440	PPC_OPCODE_440
1963 #define PPC750	PPC
1964 #define PPC860	PPC
1965 #define PPCVEC	PPC_OPCODE_ALTIVEC
1966 #define	POWER   PPC_OPCODE_POWER
1967 #define	POWER2	PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1968 #define PPCPWR2	PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1969 #define	POWER32	PPC_OPCODE_POWER | PPC_OPCODE_32
1970 #define	COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1971 #define	COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1972 #define	M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1973 #define PWRCOM	PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1974 #define	MFDEC1	PPC_OPCODE_POWER
1975 #define	MFDEC2	PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1976 #define BOOKE	PPC_OPCODE_BOOKE
1977 #define BOOKE64	PPC_OPCODE_BOOKE64
1978 #define CLASSIC	PPC_OPCODE_CLASSIC
1979 #define PPCE300 PPC_OPCODE_E300
1980 #define PPCSPE	PPC_OPCODE_SPE
1981 #define PPCISEL	PPC_OPCODE_ISEL
1982 #define PPCEFS	PPC_OPCODE_EFS
1983 #define PPCBRLK	PPC_OPCODE_BRLOCK
1984 #define PPCPMR	PPC_OPCODE_PMR
1985 #define PPCCHLK	PPC_OPCODE_CACHELCK
1986 #define PPCCHLK64	PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1987 #define PPCRFMCI	PPC_OPCODE_RFMCI
1988 
1989 /* The opcode table.
1990 
1991    The format of the opcode table is:
1992 
1993    NAME	     OPCODE	MASK		FLAGS		{ OPERANDS }
1994 
1995    NAME is the name of the instruction.
1996    OPCODE is the instruction opcode.
1997    MASK is the opcode mask; this is used to tell the disassembler
1998      which bits in the actual opcode must match OPCODE.
1999    FLAGS are flags indicated what processors support the instruction.
2000    OPERANDS is the list of operands.
2001 
2002    The disassembler reads the table in order and prints the first
2003    instruction which matches, so this table is sorted to put more
2004    specific instructions before more general instructions.  It is also
2005    sorted by major opcode.  */
2006 
2007 const struct powerpc_opcode powerpc_opcodes[] = {
2008 { "attn",    X(0,256), X_MASK,		POWER4,		{ 0 } },
2009 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,	PPC64,		{ RA, SI } },
2010 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,	PPC64,		{ RA, SI } },
2011 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,	PPC64,		{ RA, SI } },
2012 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,	PPC64,		{ RA, SI } },
2013 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,	PPC64,		{ RA, SI } },
2014 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,	PPC64,		{ RA, SI } },
2015 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,	PPC64,		{ RA, SI } },
2016 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,	PPC64,		{ RA, SI } },
2017 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,	PPC64,		{ RA, SI } },
2018 { "tdnli",   OPTO(2,TONL), OPTO_MASK,	PPC64,		{ RA, SI } },
2019 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,	PPC64,		{ RA, SI } },
2020 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,	PPC64,		{ RA, SI } },
2021 { "tdngi",   OPTO(2,TONG), OPTO_MASK,	PPC64,		{ RA, SI } },
2022 { "tdnei",   OPTO(2,TONE), OPTO_MASK,	PPC64,		{ RA, SI } },
2023 { "tdi",     OP(2),	OP_MASK,	PPC64,		{ TO, RA, SI } },
2024 
2025 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2026 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2027 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2028 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2029 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2030 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2031 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2032 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2033 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2034 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2035 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2036 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2037 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2038 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2039 { "twgti",   OPTO(3,TOGT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2040 { "tgti",    OPTO(3,TOGT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2041 { "twgei",   OPTO(3,TOGE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2042 { "tgei",    OPTO(3,TOGE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2043 { "twnli",   OPTO(3,TONL), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2044 { "tnli",    OPTO(3,TONL), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2045 { "twlti",   OPTO(3,TOLT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2046 { "tlti",    OPTO(3,TOLT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2047 { "twlei",   OPTO(3,TOLE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2048 { "tlei",    OPTO(3,TOLE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2049 { "twngi",   OPTO(3,TONG), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2050 { "tngi",    OPTO(3,TONG), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2051 { "twnei",   OPTO(3,TONE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2052 { "tnei",    OPTO(3,TONE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2053 { "twi",     OP(3),	OP_MASK,	PPCCOM,		{ TO, RA, SI } },
2054 { "ti",      OP(3),	OP_MASK,	PWRCOM,		{ TO, RA, SI } },
2055 
2056 { "macchw",	XO(4,172,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2057 { "macchw.",	XO(4,172,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2058 { "macchwo",	XO(4,172,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2059 { "macchwo.",	XO(4,172,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2060 { "macchws",	XO(4,236,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2061 { "macchws.",	XO(4,236,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2062 { "macchwso",	XO(4,236,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2063 { "macchwso.",	XO(4,236,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2064 { "macchwsu",	XO(4,204,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2065 { "macchwsu.",	XO(4,204,0,1), XO_MASK, PPC405|PPC440,	{ RT, RA, RB } },
2066 { "macchwsuo",	XO(4,204,1,0), XO_MASK, PPC405|PPC440,	{ RT, RA, RB } },
2067 { "macchwsuo.",	XO(4,204,1,1), XO_MASK, PPC405|PPC440,	{ RT, RA, RB } },
2068 { "macchwu",	XO(4,140,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2069 { "macchwu.",	XO(4,140,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2070 { "macchwuo",	XO(4,140,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2071 { "macchwuo.",	XO(4,140,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2072 { "machhw",	XO(4,44,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2073 { "machhw.",	XO(4,44,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2074 { "machhwo",	XO(4,44,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2075 { "machhwo.",	XO(4,44,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2076 { "machhws",	XO(4,108,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2077 { "machhws.",	XO(4,108,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2078 { "machhwso",	XO(4,108,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2079 { "machhwso.",	XO(4,108,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2080 { "machhwsu",	XO(4,76,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2081 { "machhwsu.",	XO(4,76,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2082 { "machhwsuo",	XO(4,76,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2083 { "machhwsuo.",	XO(4,76,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2084 { "machhwu",	XO(4,12,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2085 { "machhwu.",	XO(4,12,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2086 { "machhwuo",	XO(4,12,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2087 { "machhwuo.",	XO(4,12,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2088 { "maclhw",	XO(4,428,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2089 { "maclhw.",	XO(4,428,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2090 { "maclhwo",	XO(4,428,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2091 { "maclhwo.",	XO(4,428,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2092 { "maclhws",	XO(4,492,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2093 { "maclhws.",	XO(4,492,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2094 { "maclhwso",	XO(4,492,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2095 { "maclhwso.",	XO(4,492,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2096 { "maclhwsu",	XO(4,460,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2097 { "maclhwsu.",	XO(4,460,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2098 { "maclhwsuo",	XO(4,460,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2099 { "maclhwsuo.",	XO(4,460,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2100 { "maclhwu",	XO(4,396,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2101 { "maclhwu.",	XO(4,396,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2102 { "maclhwuo",	XO(4,396,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2103 { "maclhwuo.",	XO(4,396,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2104 { "mulchw",	XRC(4,168,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2105 { "mulchw.",	XRC(4,168,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2106 { "mulchwu",	XRC(4,136,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2107 { "mulchwu.",	XRC(4,136,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2108 { "mulhhw",	XRC(4,40,0),   X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2109 { "mulhhw.",	XRC(4,40,1),   X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2110 { "mulhhwu",	XRC(4,8,0),    X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2111 { "mulhhwu.",	XRC(4,8,1),    X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2112 { "mullhw",	XRC(4,424,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2113 { "mullhw.",	XRC(4,424,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2114 { "mullhwu",	XRC(4,392,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2115 { "mullhwu.",	XRC(4,392,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2116 { "nmacchw",	XO(4,174,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2117 { "nmacchw.",	XO(4,174,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2118 { "nmacchwo",	XO(4,174,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2119 { "nmacchwo.",	XO(4,174,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2120 { "nmacchws",	XO(4,238,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2121 { "nmacchws.",	XO(4,238,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2122 { "nmacchwso",	XO(4,238,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2123 { "nmacchwso.",	XO(4,238,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2124 { "nmachhw",	XO(4,46,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2125 { "nmachhw.",	XO(4,46,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2126 { "nmachhwo",	XO(4,46,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2127 { "nmachhwo.",	XO(4,46,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2128 { "nmachhws",	XO(4,110,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2129 { "nmachhws.",	XO(4,110,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2130 { "nmachhwso",	XO(4,110,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2131 { "nmachhwso.",	XO(4,110,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2132 { "nmaclhw",	XO(4,430,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2133 { "nmaclhw.",	XO(4,430,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2134 { "nmaclhwo",	XO(4,430,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2135 { "nmaclhwo.",	XO(4,430,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2136 { "nmaclhws",	XO(4,494,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2137 { "nmaclhws.",	XO(4,494,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2138 { "nmaclhwso",	XO(4,494,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2139 { "nmaclhwso.",	XO(4,494,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2140 { "mfvscr",  VX(4, 1540), VX_MASK,	PPCVEC,		{ VD } },
2141 { "mtvscr",  VX(4, 1604), VX_MASK,	PPCVEC,		{ VB } },
2142 
2143   /* Double-precision opcodes.  */
2144   /* Some of these conflict with AltiVec, so move them before, since
2145      PPCVEC includes the PPC_OPCODE_PPC set.  */
2146 { "efscfd",   VX(4, 719), VX_MASK,	PPCEFS,		{ RS, RB } },
2147 { "efdabs",   VX(4, 740), VX_MASK,	PPCEFS,		{ RS, RA } },
2148 { "efdnabs",  VX(4, 741), VX_MASK,	PPCEFS,		{ RS, RA } },
2149 { "efdneg",   VX(4, 742), VX_MASK,	PPCEFS,		{ RS, RA } },
2150 { "efdadd",   VX(4, 736), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2151 { "efdsub",   VX(4, 737), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2152 { "efdmul",   VX(4, 744), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2153 { "efddiv",   VX(4, 745), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2154 { "efdcmpgt", VX(4, 748), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2155 { "efdcmplt", VX(4, 749), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2156 { "efdcmpeq", VX(4, 750), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2157 { "efdtstgt", VX(4, 764), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2158 { "efdtstlt", VX(4, 765), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2159 { "efdtsteq", VX(4, 766), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2160 { "efdcfsi",  VX(4, 753), VX_MASK,	PPCEFS,		{ RS, RB } },
2161 { "efdcfsid", VX(4, 739), VX_MASK,	PPCEFS,		{ RS, RB } },
2162 { "efdcfui",  VX(4, 752), VX_MASK,	PPCEFS,		{ RS, RB } },
2163 { "efdcfuid", VX(4, 738), VX_MASK,	PPCEFS,		{ RS, RB } },
2164 { "efdcfsf",  VX(4, 755), VX_MASK,	PPCEFS,		{ RS, RB } },
2165 { "efdcfuf",  VX(4, 754), VX_MASK,	PPCEFS,		{ RS, RB } },
2166 { "efdctsi",  VX(4, 757), VX_MASK,	PPCEFS,		{ RS, RB } },
2167 { "efdctsidz",VX(4, 747), VX_MASK,	PPCEFS,		{ RS, RB } },
2168 { "efdctsiz", VX(4, 762), VX_MASK,	PPCEFS,		{ RS, RB } },
2169 { "efdctui",  VX(4, 756), VX_MASK,	PPCEFS,		{ RS, RB } },
2170 { "efdctuidz",VX(4, 746), VX_MASK,	PPCEFS,		{ RS, RB } },
2171 { "efdctuiz", VX(4, 760), VX_MASK,	PPCEFS,		{ RS, RB } },
2172 { "efdctsf",  VX(4, 759), VX_MASK,	PPCEFS,		{ RS, RB } },
2173 { "efdctuf",  VX(4, 758), VX_MASK,	PPCEFS,		{ RS, RB } },
2174 { "efdcfs",   VX(4, 751), VX_MASK,	PPCEFS,		{ RS, RB } },
2175   /* End of double-precision opcodes.  */
2176 
2177 { "vaddcuw", VX(4,  384), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2178 { "vaddfp",  VX(4,   10), VX_MASK, 	PPCVEC,		{ VD, VA, VB } },
2179 { "vaddsbs", VX(4,  768), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2180 { "vaddshs", VX(4,  832), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2181 { "vaddsws", VX(4,  896), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2182 { "vaddubm", VX(4,    0), VX_MASK, 	PPCVEC,		{ VD, VA, VB } },
2183 { "vaddubs", VX(4,  512), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2184 { "vadduhm", VX(4,   64), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2185 { "vadduhs", VX(4,  576), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2186 { "vadduwm", VX(4,  128), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2187 { "vadduws", VX(4,  640), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2188 { "vand",    VX(4, 1028), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2189 { "vandc",   VX(4, 1092), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2190 { "vavgsb",  VX(4, 1282), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2191 { "vavgsh",  VX(4, 1346), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2192 { "vavgsw",  VX(4, 1410), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2193 { "vavgub",  VX(4, 1026), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2194 { "vavguh",  VX(4, 1090), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2195 { "vavguw",  VX(4, 1154), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2196 { "vcfsx",   VX(4,  842), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2197 { "vcfux",   VX(4,  778), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2198 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2199 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2200 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2201 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2202 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2203 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2204 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2205 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2206 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2207 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2208 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2209 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2210 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2211 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2212 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2213 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2214 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2215 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2216 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2217 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2218 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2219 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2220 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2221 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2222 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2223 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2224 { "vctsxs",    VX(4,  970), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2225 { "vctuxs",    VX(4,  906), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2226 { "vexptefp",  VX(4,  394), VX_MASK,	PPCVEC,		{ VD, VB } },
2227 { "vlogefp",   VX(4,  458), VX_MASK,	PPCVEC,		{ VD, VB } },
2228 { "vmaddfp",   VXA(4,  46), VXA_MASK,	PPCVEC,		{ VD, VA, VC, VB } },
2229 { "vmaxfp",    VX(4, 1034), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2230 { "vmaxsb",    VX(4,  258), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2231 { "vmaxsh",    VX(4,  322), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2232 { "vmaxsw",    VX(4,  386), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2233 { "vmaxub",    VX(4,    2), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2234 { "vmaxuh",    VX(4,   66), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2235 { "vmaxuw",    VX(4,  130), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2236 { "vmhaddshs", VXA(4,  32), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2237 { "vmhraddshs", VXA(4, 33), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2238 { "vminfp",    VX(4, 1098), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2239 { "vminsb",    VX(4,  770), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2240 { "vminsh",    VX(4,  834), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2241 { "vminsw",    VX(4,  898), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2242 { "vminub",    VX(4,  514), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2243 { "vminuh",    VX(4,  578), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2244 { "vminuw",    VX(4,  642), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2245 { "vmladduhm", VXA(4,  34), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2246 { "vmrghb",    VX(4,   12), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2247 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,		{ VD, VA, VB } },
2248 { "vmrghw",    VX(4,  140), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2249 { "vmrglb",    VX(4,  268), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2250 { "vmrglh",    VX(4,  332), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2251 { "vmrglw",    VX(4,  396), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2252 { "vmsummbm",  VXA(4,  37), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2253 { "vmsumshm",  VXA(4,  40), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2254 { "vmsumshs",  VXA(4,  41), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2255 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
2256 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
2257 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
2258 { "vmulesb",   VX(4,  776), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2259 { "vmulesh",   VX(4,  840), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2260 { "vmuleub",   VX(4,  520), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2261 { "vmuleuh",   VX(4,  584), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2262 { "vmulosb",   VX(4,  264), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2263 { "vmulosh",   VX(4,  328), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2264 { "vmuloub",   VX(4,    8), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2265 { "vmulouh",   VX(4,   72), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2266 { "vnmsubfp",  VXA(4,  47), VXA_MASK,	PPCVEC,		{ VD, VA, VC, VB } },
2267 { "vnor",      VX(4, 1284), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2268 { "vor",       VX(4, 1156), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2269 { "vperm",     VXA(4,  43), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2270 { "vpkpx",     VX(4,  782), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2271 { "vpkshss",   VX(4,  398), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2272 { "vpkshus",   VX(4,  270), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2273 { "vpkswss",   VX(4,  462), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2274 { "vpkswus",   VX(4,  334), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2275 { "vpkuhum",   VX(4,   14), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2276 { "vpkuhus",   VX(4,  142), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2277 { "vpkuwum",   VX(4,   78), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2278 { "vpkuwus",   VX(4,  206), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2279 { "vrefp",     VX(4,  266), VX_MASK,	PPCVEC,		{ VD, VB } },
2280 { "vrfim",     VX(4,  714), VX_MASK,	PPCVEC,		{ VD, VB } },
2281 { "vrfin",     VX(4,  522), VX_MASK,	PPCVEC,		{ VD, VB } },
2282 { "vrfip",     VX(4,  650), VX_MASK,	PPCVEC,		{ VD, VB } },
2283 { "vrfiz",     VX(4,  586), VX_MASK,	PPCVEC,		{ VD, VB } },
2284 { "vrlb",      VX(4,    4), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2285 { "vrlh",      VX(4,   68), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2286 { "vrlw",      VX(4,  132), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2287 { "vrsqrtefp", VX(4,  330), VX_MASK,	PPCVEC,		{ VD, VB } },
2288 { "vsel",      VXA(4,  42), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2289 { "vsl",       VX(4,  452), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2290 { "vslb",      VX(4,  260), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2291 { "vsldoi",    VXA(4,  44), VXA_MASK,	PPCVEC,		{ VD, VA, VB, SHB } },
2292 { "vslh",      VX(4,  324), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2293 { "vslo",      VX(4, 1036), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2294 { "vslw",      VX(4,  388), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2295 { "vspltb",    VX(4,  524), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2296 { "vsplth",    VX(4,  588), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2297 { "vspltisb",  VX(4,  780), VX_MASK,	PPCVEC,		{ VD, SIMM } },
2298 { "vspltish",  VX(4,  844), VX_MASK,	PPCVEC,		{ VD, SIMM } },
2299 { "vspltisw",  VX(4,  908), VX_MASK,	PPCVEC,		{ VD, SIMM } },
2300 { "vspltw",    VX(4,  652), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2301 { "vsr",       VX(4,  708), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2302 { "vsrab",     VX(4,  772), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2303 { "vsrah",     VX(4,  836), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2304 { "vsraw",     VX(4,  900), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2305 { "vsrb",      VX(4,  516), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2306 { "vsrh",      VX(4,  580), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2307 { "vsro",      VX(4, 1100), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2308 { "vsrw",      VX(4,  644), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2309 { "vsubcuw",   VX(4, 1408), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2310 { "vsubfp",    VX(4,   74), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2311 { "vsubsbs",   VX(4, 1792), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2312 { "vsubshs",   VX(4, 1856), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2313 { "vsubsws",   VX(4, 1920), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2314 { "vsububm",   VX(4, 1024), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2315 { "vsububs",   VX(4, 1536), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2316 { "vsubuhm",   VX(4, 1088), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2317 { "vsubuhs",   VX(4, 1600), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2318 { "vsubuwm",   VX(4, 1152), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2319 { "vsubuws",   VX(4, 1664), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2320 { "vsumsws",   VX(4, 1928), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2321 { "vsum2sws",  VX(4, 1672), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2322 { "vsum4sbs",  VX(4, 1800), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2323 { "vsum4shs",  VX(4, 1608), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2324 { "vsum4ubs",  VX(4, 1544), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2325 { "vupkhpx",   VX(4,  846), VX_MASK,	PPCVEC,		{ VD, VB } },
2326 { "vupkhsb",   VX(4,  526), VX_MASK,	PPCVEC,		{ VD, VB } },
2327 { "vupkhsh",   VX(4,  590), VX_MASK,	PPCVEC,		{ VD, VB } },
2328 { "vupklpx",   VX(4,  974), VX_MASK,	PPCVEC,		{ VD, VB } },
2329 { "vupklsb",   VX(4,  654), VX_MASK,	PPCVEC,		{ VD, VB } },
2330 { "vupklsh",   VX(4,  718), VX_MASK,	PPCVEC,		{ VD, VB } },
2331 { "vxor",      VX(4, 1220), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2332 
2333 { "evaddw",    VX(4, 512), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2334 { "evaddiw",   VX(4, 514), VX_MASK,	PPCSPE,		{ RS, RB, UIMM } },
2335 { "evsubfw",   VX(4, 516), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2336 { "evsubw",    VX(4, 516), VX_MASK,	PPCSPE,		{ RS, RB, RA } },
2337 { "evsubifw",  VX(4, 518), VX_MASK,	PPCSPE,		{ RS, UIMM, RB } },
2338 { "evsubiw",   VX(4, 518), VX_MASK,	PPCSPE,		{ RS, RB, UIMM } },
2339 { "evabs",     VX(4, 520), VX_MASK,	PPCSPE,		{ RS, RA } },
2340 { "evneg",     VX(4, 521), VX_MASK,	PPCSPE,		{ RS, RA } },
2341 { "evextsb",   VX(4, 522), VX_MASK,	PPCSPE,		{ RS, RA } },
2342 { "evextsh",   VX(4, 523), VX_MASK,	PPCSPE,		{ RS, RA } },
2343 { "evrndw",    VX(4, 524), VX_MASK,	PPCSPE,		{ RS, RA } },
2344 { "evcntlzw",  VX(4, 525), VX_MASK,	PPCSPE,		{ RS, RA } },
2345 { "evcntlsw",  VX(4, 526), VX_MASK,	PPCSPE,		{ RS, RA } },
2346 
2347 { "brinc",     VX(4, 527), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2348 
2349 { "evand",     VX(4, 529), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2350 { "evandc",    VX(4, 530), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2351 { "evmr",      VX(4, 535), VX_MASK,	PPCSPE,		{ RS, RA, BBA } },
2352 { "evor",      VX(4, 535), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2353 { "evorc",     VX(4, 539), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2354 { "evxor",     VX(4, 534), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2355 { "eveqv",     VX(4, 537), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2356 { "evnand",    VX(4, 542), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2357 { "evnot",     VX(4, 536), VX_MASK,	PPCSPE,		{ RS, RA, BBA } },
2358 { "evnor",     VX(4, 536), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2359 
2360 { "evrlw",     VX(4, 552), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2361 { "evrlwi",    VX(4, 554), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2362 { "evslw",     VX(4, 548), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2363 { "evslwi",    VX(4, 550), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2364 { "evsrws",    VX(4, 545), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2365 { "evsrwu",    VX(4, 544), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2366 { "evsrwis",   VX(4, 547), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2367 { "evsrwiu",   VX(4, 546), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2368 { "evsplati",  VX(4, 553), VX_MASK,	PPCSPE,		{ RS, SIMM } },
2369 { "evsplatfi", VX(4, 555), VX_MASK,	PPCSPE,		{ RS, SIMM } },
2370 { "evmergehi", VX(4, 556), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2371 { "evmergelo", VX(4, 557), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2372 { "evmergehilo",VX(4,558), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2373 { "evmergelohi",VX(4,559), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2374 
2375 { "evcmpgts",  VX(4, 561), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2376 { "evcmpgtu",  VX(4, 560), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2377 { "evcmplts",  VX(4, 563), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2378 { "evcmpltu",  VX(4, 562), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2379 { "evcmpeq",   VX(4, 564), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2380 { "evsel",     EVSEL(4,79),EVSEL_MASK,	PPCSPE,		{ RS, RA, RB, CRFS } },
2381 
2382 { "evldd",     VX(4, 769), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2383 { "evlddx",    VX(4, 768), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2384 { "evldw",     VX(4, 771), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2385 { "evldwx",    VX(4, 770), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2386 { "evldh",     VX(4, 773), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2387 { "evldhx",    VX(4, 772), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2388 { "evlwhe",    VX(4, 785), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2389 { "evlwhex",   VX(4, 784), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2390 { "evlwhou",   VX(4, 789), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2391 { "evlwhoux",  VX(4, 788), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2392 { "evlwhos",   VX(4, 791), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2393 { "evlwhosx",  VX(4, 790), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2394 { "evlwwsplat",VX(4, 793), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2395 { "evlwwsplatx",VX(4, 792), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2396 { "evlwhsplat",VX(4, 797), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2397 { "evlwhsplatx",VX(4, 796), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2398 { "evlhhesplat",VX(4, 777), VX_MASK,	PPCSPE,		{ RS, EVUIMM_2, RA } },
2399 { "evlhhesplatx",VX(4, 776), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2400 { "evlhhousplat",VX(4, 781), VX_MASK,	PPCSPE,		{ RS, EVUIMM_2, RA } },
2401 { "evlhhousplatx",VX(4, 780), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2402 { "evlhhossplat",VX(4, 783), VX_MASK,	PPCSPE,		{ RS, EVUIMM_2, RA } },
2403 { "evlhhossplatx",VX(4, 782), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2404 
2405 { "evstdd",    VX(4, 801), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2406 { "evstddx",   VX(4, 800), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2407 { "evstdw",    VX(4, 803), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2408 { "evstdwx",   VX(4, 802), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2409 { "evstdh",    VX(4, 805), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2410 { "evstdhx",   VX(4, 804), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2411 { "evstwwe",   VX(4, 825), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2412 { "evstwwex",  VX(4, 824), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2413 { "evstwwo",   VX(4, 829), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2414 { "evstwwox",  VX(4, 828), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2415 { "evstwhe",   VX(4, 817), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2416 { "evstwhex",  VX(4, 816), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2417 { "evstwho",   VX(4, 821), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2418 { "evstwhox",  VX(4, 820), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2419 
2420 { "evfsabs",   VX(4, 644), VX_MASK,	PPCSPE,		{ RS, RA } },
2421 { "evfsnabs",  VX(4, 645), VX_MASK,	PPCSPE,		{ RS, RA } },
2422 { "evfsneg",   VX(4, 646), VX_MASK,	PPCSPE,		{ RS, RA } },
2423 { "evfsadd",   VX(4, 640), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2424 { "evfssub",   VX(4, 641), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2425 { "evfsmul",   VX(4, 648), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2426 { "evfsdiv",   VX(4, 649), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2427 { "evfscmpgt", VX(4, 652), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2428 { "evfscmplt", VX(4, 653), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2429 { "evfscmpeq", VX(4, 654), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2430 { "evfststgt", VX(4, 668), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2431 { "evfststlt", VX(4, 669), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2432 { "evfststeq", VX(4, 670), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2433 { "evfscfui",  VX(4, 656), VX_MASK,	PPCSPE,		{ RS, RB } },
2434 { "evfsctuiz", VX(4, 664), VX_MASK,	PPCSPE,		{ RS, RB } },
2435 { "evfscfsi",  VX(4, 657), VX_MASK,	PPCSPE,		{ RS, RB } },
2436 { "evfscfuf",  VX(4, 658), VX_MASK,	PPCSPE,		{ RS, RB } },
2437 { "evfscfsf",  VX(4, 659), VX_MASK,	PPCSPE,		{ RS, RB } },
2438 { "evfsctui",  VX(4, 660), VX_MASK,	PPCSPE,		{ RS, RB } },
2439 { "evfsctsi",  VX(4, 661), VX_MASK,	PPCSPE,		{ RS, RB } },
2440 { "evfsctsiz", VX(4, 666), VX_MASK,	PPCSPE,		{ RS, RB } },
2441 { "evfsctuf",  VX(4, 662), VX_MASK,	PPCSPE,		{ RS, RB } },
2442 { "evfsctsf",  VX(4, 663), VX_MASK,	PPCSPE,		{ RS, RB } },
2443 
2444 { "efsabs",   VX(4, 708), VX_MASK,	PPCEFS,		{ RS, RA } },
2445 { "efsnabs",  VX(4, 709), VX_MASK,	PPCEFS,		{ RS, RA } },
2446 { "efsneg",   VX(4, 710), VX_MASK,	PPCEFS,		{ RS, RA } },
2447 { "efsadd",   VX(4, 704), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2448 { "efssub",   VX(4, 705), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2449 { "efsmul",   VX(4, 712), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2450 { "efsdiv",   VX(4, 713), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2451 { "efscmpgt", VX(4, 716), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2452 { "efscmplt", VX(4, 717), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2453 { "efscmpeq", VX(4, 718), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2454 { "efststgt", VX(4, 732), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2455 { "efststlt", VX(4, 733), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2456 { "efststeq", VX(4, 734), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2457 { "efscfui",  VX(4, 720), VX_MASK,	PPCEFS,		{ RS, RB } },
2458 { "efsctuiz", VX(4, 728), VX_MASK,	PPCEFS,		{ RS, RB } },
2459 { "efscfsi",  VX(4, 721), VX_MASK,	PPCEFS,		{ RS, RB } },
2460 { "efscfuf",  VX(4, 722), VX_MASK,	PPCEFS,		{ RS, RB } },
2461 { "efscfsf",  VX(4, 723), VX_MASK,	PPCEFS,		{ RS, RB } },
2462 { "efsctui",  VX(4, 724), VX_MASK,	PPCEFS,		{ RS, RB } },
2463 { "efsctsi",  VX(4, 725), VX_MASK,	PPCEFS,		{ RS, RB } },
2464 { "efsctsiz", VX(4, 730), VX_MASK,	PPCEFS,		{ RS, RB } },
2465 { "efsctuf",  VX(4, 726), VX_MASK,	PPCEFS,		{ RS, RB } },
2466 { "efsctsf",  VX(4, 727), VX_MASK,	PPCEFS,		{ RS, RB } },
2467 
2468 { "evmhossf",  VX(4, 1031), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2469 { "evmhossfa", VX(4, 1063), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2470 { "evmhosmf",  VX(4, 1039), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2471 { "evmhosmfa", VX(4, 1071), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2472 { "evmhosmi",  VX(4, 1037), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2473 { "evmhosmia", VX(4, 1069), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2474 { "evmhoumi",  VX(4, 1036), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2475 { "evmhoumia", VX(4, 1068), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2476 { "evmhessf",  VX(4, 1027), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2477 { "evmhessfa", VX(4, 1059), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2478 { "evmhesmf",  VX(4, 1035), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2479 { "evmhesmfa", VX(4, 1067), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2480 { "evmhesmi",  VX(4, 1033), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2481 { "evmhesmia", VX(4, 1065), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2482 { "evmheumi",  VX(4, 1032), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2483 { "evmheumia", VX(4, 1064), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2484 
2485 { "evmhossfaaw",VX(4, 1287), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2486 { "evmhossiaaw",VX(4, 1285), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2487 { "evmhosmfaaw",VX(4, 1295), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2488 { "evmhosmiaaw",VX(4, 1293), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2489 { "evmhousiaaw",VX(4, 1284), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2490 { "evmhoumiaaw",VX(4, 1292), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2491 { "evmhessfaaw",VX(4, 1283), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2492 { "evmhessiaaw",VX(4, 1281), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2493 { "evmhesmfaaw",VX(4, 1291), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2494 { "evmhesmiaaw",VX(4, 1289), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2495 { "evmheusiaaw",VX(4, 1280), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2496 { "evmheumiaaw",VX(4, 1288), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2497 
2498 { "evmhossfanw",VX(4, 1415), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2499 { "evmhossianw",VX(4, 1413), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2500 { "evmhosmfanw",VX(4, 1423), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2501 { "evmhosmianw",VX(4, 1421), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2502 { "evmhousianw",VX(4, 1412), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2503 { "evmhoumianw",VX(4, 1420), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2504 { "evmhessfanw",VX(4, 1411), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2505 { "evmhessianw",VX(4, 1409), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2506 { "evmhesmfanw",VX(4, 1419), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2507 { "evmhesmianw",VX(4, 1417), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2508 { "evmheusianw",VX(4, 1408), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2509 { "evmheumianw",VX(4, 1416), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2510 
2511 { "evmhogsmfaa",VX(4, 1327), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2512 { "evmhogsmiaa",VX(4, 1325), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2513 { "evmhogumiaa",VX(4, 1324), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2514 { "evmhegsmfaa",VX(4, 1323), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2515 { "evmhegsmiaa",VX(4, 1321), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2516 { "evmhegumiaa",VX(4, 1320), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2517 
2518 { "evmhogsmfan",VX(4, 1455), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2519 { "evmhogsmian",VX(4, 1453), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2520 { "evmhogumian",VX(4, 1452), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2521 { "evmhegsmfan",VX(4, 1451), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2522 { "evmhegsmian",VX(4, 1449), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2523 { "evmhegumian",VX(4, 1448), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2524 
2525 { "evmwhssf",  VX(4, 1095), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2526 { "evmwhssfa", VX(4, 1127), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2527 { "evmwhsmf",  VX(4, 1103), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2528 { "evmwhsmfa", VX(4, 1135), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2529 { "evmwhsmi",  VX(4, 1101), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2530 { "evmwhsmia", VX(4, 1133), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2531 { "evmwhumi",  VX(4, 1100), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2532 { "evmwhumia", VX(4, 1132), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2533 
2534 { "evmwlumi",  VX(4, 1096), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2535 { "evmwlumia", VX(4, 1128), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2536 
2537 { "evmwlssiaaw",VX(4, 1345), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2538 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2539 { "evmwlusiaaw",VX(4, 1344), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2540 { "evmwlumiaaw",VX(4, 1352), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2541 
2542 { "evmwlssianw",VX(4, 1473), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2543 { "evmwlsmianw",VX(4, 1481), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2544 { "evmwlusianw",VX(4, 1472), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2545 { "evmwlumianw",VX(4, 1480), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2546 
2547 { "evmwssf",   VX(4, 1107), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2548 { "evmwssfa",  VX(4, 1139), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2549 { "evmwsmf",   VX(4, 1115), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2550 { "evmwsmfa",  VX(4, 1147), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2551 { "evmwsmi",   VX(4, 1113), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2552 { "evmwsmia",  VX(4, 1145), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2553 { "evmwumi",   VX(4, 1112), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2554 { "evmwumia",  VX(4, 1144), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2555 
2556 { "evmwssfaa", VX(4, 1363), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2557 { "evmwsmfaa", VX(4, 1371), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2558 { "evmwsmiaa", VX(4, 1369), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2559 { "evmwumiaa", VX(4, 1368), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2560 
2561 { "evmwssfan", VX(4, 1491), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2562 { "evmwsmfan", VX(4, 1499), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2563 { "evmwsmian", VX(4, 1497), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2564 { "evmwumian", VX(4, 1496), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2565 
2566 { "evaddssiaaw",VX(4, 1217), VX_MASK,	PPCSPE,		{ RS, RA } },
2567 { "evaddsmiaaw",VX(4, 1225), VX_MASK,	PPCSPE,		{ RS, RA } },
2568 { "evaddusiaaw",VX(4, 1216), VX_MASK,	PPCSPE,		{ RS, RA } },
2569 { "evaddumiaaw",VX(4, 1224), VX_MASK,	PPCSPE,		{ RS, RA } },
2570 
2571 { "evsubfssiaaw",VX(4, 1219), VX_MASK,	PPCSPE,		{ RS, RA } },
2572 { "evsubfsmiaaw",VX(4, 1227), VX_MASK,	PPCSPE,		{ RS, RA } },
2573 { "evsubfusiaaw",VX(4, 1218), VX_MASK,	PPCSPE,		{ RS, RA } },
2574 { "evsubfumiaaw",VX(4, 1226), VX_MASK,	PPCSPE,		{ RS, RA } },
2575 
2576 { "evmra",    VX(4, 1220), VX_MASK,	PPCSPE,		{ RS, RA } },
2577 
2578 { "evdivws",  VX(4, 1222), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2579 { "evdivwu",  VX(4, 1223), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2580 
2581 { "mulli",   OP(7),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2582 { "muli",    OP(7),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2583 
2584 { "subfic",  OP(8),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2585 { "sfi",     OP(8),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2586 
2587 { "dozi",    OP(9),	OP_MASK,	M601,		{ RT, RA, SI } },
2588 
2589 { "bce",     B(9,0,0),	B_MASK,		BOOKE64,	{ BO, BI, BD } },
2590 { "bcel",    B(9,0,1),	B_MASK,		BOOKE64,	{ BO, BI, BD } },
2591 { "bcea",    B(9,1,0),	B_MASK,		BOOKE64,	{ BO, BI, BDA } },
2592 { "bcela",   B(9,1,1),	B_MASK,		BOOKE64,	{ BO, BI, BDA } },
2593 
2594 { "cmplwi",  OPL(10,0),	OPL_MASK,	PPCCOM,		{ OBF, RA, UI } },
2595 { "cmpldi",  OPL(10,1), OPL_MASK,	PPC64,		{ OBF, RA, UI } },
2596 { "cmpli",   OP(10),	OP_MASK,	PPC,		{ BF, L, RA, UI } },
2597 { "cmpli",   OP(10),	OP_MASK,	PWRCOM,		{ BF, RA, UI } },
2598 
2599 { "cmpwi",   OPL(11,0),	OPL_MASK,	PPCCOM,		{ OBF, RA, SI } },
2600 { "cmpdi",   OPL(11,1),	OPL_MASK,	PPC64,		{ OBF, RA, SI } },
2601 { "cmpi",    OP(11),	OP_MASK,	PPC,		{ BF, L, RA, SI } },
2602 { "cmpi",    OP(11),	OP_MASK,	PWRCOM,		{ BF, RA, SI } },
2603 
2604 { "addic",   OP(12),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2605 { "ai",	     OP(12),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2606 { "subic",   OP(12),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
2607 
2608 { "addic.",  OP(13),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2609 { "ai.",     OP(13),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2610 { "subic.",  OP(13),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
2611 
2612 { "li",	     OP(14),	DRA_MASK,	PPCCOM,		{ RT, SI } },
2613 { "lil",     OP(14),	DRA_MASK,	PWRCOM,		{ RT, SI } },
2614 { "addi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, SI } },
2615 { "cal",     OP(14),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
2616 { "subi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
2617 { "la",	     OP(14),	OP_MASK,	PPCCOM,		{ RT, D, RA0 } },
2618 
2619 { "lis",     OP(15),	DRA_MASK,	PPCCOM,		{ RT, SISIGNOPT } },
2620 { "liu",     OP(15),	DRA_MASK,	PWRCOM,		{ RT, SISIGNOPT } },
2621 { "addis",   OP(15),	OP_MASK,	PPCCOM,		{ RT,RA0,SISIGNOPT } },
2622 { "cau",     OP(15),	OP_MASK,	PWRCOM,		{ RT,RA0,SISIGNOPT } },
2623 { "subis",   OP(15),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
2624 
2625 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BDM } },
2626 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BDP } },
2627 { "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BD } },
2628 { "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,	{ BD } },
2629 { "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,	{ BDM } },
2630 { "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,	{ BDP } },
2631 { "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,	{ BD } },
2632 { "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,	{ BD } },
2633 { "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,	{ BDMA } },
2634 { "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,	{ BDPA } },
2635 { "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,	{ BDA } },
2636 { "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,	{ BDA } },
2637 { "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,	{ BDMA } },
2638 { "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,	{ BDPA } },
2639 { "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,	{ BDA } },
2640 { "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,	{ BDA } },
2641 { "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,	{ BDM } },
2642 { "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,	{ BDP } },
2643 { "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,		{ BD } },
2644 { "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,	{ BDM } },
2645 { "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,	{ BDP } },
2646 { "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,		{ BD } },
2647 { "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,	{ BDMA } },
2648 { "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,	{ BDPA } },
2649 { "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,		{ BDA } },
2650 { "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,	{ BDMA } },
2651 { "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,	{ BDPA } },
2652 { "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,		{ BDA } },
2653 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2654 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2655 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2656 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2657 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2658 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2659 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2660 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2661 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2662 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2663 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2664 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2665 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2666 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2667 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2668 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2669 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2670 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2671 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2672 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2673 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2674 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2675 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2676 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2677 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2678 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2679 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2680 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2681 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2682 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2683 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2684 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2685 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2686 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2687 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2688 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2689 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2690 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2691 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2692 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2693 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2694 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2695 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2696 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2697 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2698 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2699 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2700 { "bsola",   BBOCB<