xref: /illumos-kvm-cmd/mips-dis.c (revision 68396ea9)
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3    2000, 2001, 2002, 2003
4    Free Software Foundation, Inc.
5    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6 
7 This file is part of GDB, GAS, and the GNU binutils.
8 
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13 
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 GNU General Public License for more details.
18 
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, see <http://www.gnu.org/licenses/>.  */
21 
22 #include "dis-asm.h"
23 
24 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
25    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
26    Free Software Foundation, Inc.
27    Contributed by Ralph Campbell and OSF
28    Commented and modified by Ian Lance Taylor, Cygnus Support
29 
30 This file is part of GDB, GAS, and the GNU binutils.
31 
32 GDB, GAS, and the GNU binutils are free software; you can redistribute
33 them and/or modify them under the terms of the GNU General Public
34 License as published by the Free Software Foundation; either version
35 1, or (at your option) any later version.
36 
37 GDB, GAS, and the GNU binutils are distributed in the hope that they
38 will be useful, but WITHOUT ANY WARRANTY; without even the implied
39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
40 the GNU General Public License for more details.
41 
42 You should have received a copy of the GNU General Public License
43 along with this file; see the file COPYING.  If not,
44 see <http://www.gnu.org/licenses/>.  */
45 
46 /* These are bit masks and shift counts to use to access the various
47    fields of an instruction.  To retrieve the X field of an
48    instruction, use the expression
49 	(i >> OP_SH_X) & OP_MASK_X
50    To set the same field (to j), use
51 	i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
52 
53    Make sure you use fields that are appropriate for the instruction,
54    of course.
55 
56    The 'i' format uses OP, RS, RT and IMMEDIATE.
57 
58    The 'j' format uses OP and TARGET.
59 
60    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
61 
62    The 'b' format uses OP, RS, RT and DELTA.
63 
64    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
65 
66    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
67 
68    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
69    breakpoint instruction are not defined; Kane says the breakpoint
70    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
71    only use ten bits).  An optional two-operand form of break/sdbbp
72    allows the lower ten bits to be set too, and MIPS32 and later
73    architectures allow 20 bits to be set with a signal operand
74    (using CODE20).
75 
76    The syscall instruction uses CODE20.
77 
78    The general coprocessor instructions use COPZ.  */
79 
80 #define OP_MASK_OP		0x3f
81 #define OP_SH_OP		26
82 #define OP_MASK_RS		0x1f
83 #define OP_SH_RS		21
84 #define OP_MASK_FR		0x1f
85 #define OP_SH_FR		21
86 #define OP_MASK_FMT		0x1f
87 #define OP_SH_FMT		21
88 #define OP_MASK_BCC		0x7
89 #define OP_SH_BCC		18
90 #define OP_MASK_CODE		0x3ff
91 #define OP_SH_CODE		16
92 #define OP_MASK_CODE2		0x3ff
93 #define OP_SH_CODE2		6
94 #define OP_MASK_RT		0x1f
95 #define OP_SH_RT		16
96 #define OP_MASK_FT		0x1f
97 #define OP_SH_FT		16
98 #define OP_MASK_CACHE		0x1f
99 #define OP_SH_CACHE		16
100 #define OP_MASK_RD		0x1f
101 #define OP_SH_RD		11
102 #define OP_MASK_FS		0x1f
103 #define OP_SH_FS		11
104 #define OP_MASK_PREFX		0x1f
105 #define OP_SH_PREFX		11
106 #define OP_MASK_CCC		0x7
107 #define OP_SH_CCC		8
108 #define OP_MASK_CODE20		0xfffff /* 20 bit syscall/breakpoint code.  */
109 #define OP_SH_CODE20		6
110 #define OP_MASK_SHAMT		0x1f
111 #define OP_SH_SHAMT		6
112 #define OP_MASK_FD		0x1f
113 #define OP_SH_FD		6
114 #define OP_MASK_TARGET		0x3ffffff
115 #define OP_SH_TARGET		0
116 #define OP_MASK_COPZ		0x1ffffff
117 #define OP_SH_COPZ		0
118 #define OP_MASK_IMMEDIATE	0xffff
119 #define OP_SH_IMMEDIATE		0
120 #define OP_MASK_DELTA		0xffff
121 #define OP_SH_DELTA		0
122 #define OP_MASK_FUNCT		0x3f
123 #define OP_SH_FUNCT		0
124 #define OP_MASK_SPEC		0x3f
125 #define OP_SH_SPEC		0
126 #define OP_SH_LOCC              8       /* FP condition code.  */
127 #define OP_SH_HICC              18      /* FP condition code.  */
128 #define OP_MASK_CC              0x7
129 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
130 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
131 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
132 #define OP_MASK_COP1SPEC        0xf
133 #define OP_MASK_COP1SCLR        0x4
134 #define OP_MASK_COP1CMP         0x3
135 #define OP_SH_COP1CMP           4
136 #define OP_SH_FORMAT            21      /* FP short format field.  */
137 #define OP_MASK_FORMAT          0x7
138 #define OP_SH_TRUE              16
139 #define OP_MASK_TRUE            0x1
140 #define OP_SH_GE                17
141 #define OP_MASK_GE              0x01
142 #define OP_SH_UNSIGNED          16
143 #define OP_MASK_UNSIGNED        0x1
144 #define OP_SH_HINT              16
145 #define OP_MASK_HINT            0x1f
146 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
147 #define OP_MASK_MMI             0x3f
148 #define OP_SH_MMISUB            6
149 #define OP_MASK_MMISUB          0x1f
150 #define OP_MASK_PERFREG		0x1f	/* Performance monitoring.  */
151 #define OP_SH_PERFREG		1
152 #define OP_SH_SEL		0	/* Coprocessor select field.  */
153 #define OP_MASK_SEL		0x7	/* The sel field of mfcZ and mtcZ.  */
154 #define OP_SH_CODE19		6       /* 19 bit wait code.  */
155 #define OP_MASK_CODE19		0x7ffff
156 #define OP_SH_ALN		21
157 #define OP_MASK_ALN		0x7
158 #define OP_SH_VSEL		21
159 #define OP_MASK_VSEL		0x1f
160 #define OP_MASK_VECBYTE		0x7	/* Selector field is really 4 bits,
161 					   but 0x8-0xf don't select bytes.  */
162 #define OP_SH_VECBYTE		22
163 #define OP_MASK_VECALIGN	0x7	/* Vector byte-align (alni.ob) op.  */
164 #define OP_SH_VECALIGN		21
165 #define OP_MASK_INSMSB		0x1f	/* "ins" MSB.  */
166 #define OP_SH_INSMSB		11
167 #define OP_MASK_EXTMSBD		0x1f	/* "ext" MSBD.  */
168 #define OP_SH_EXTMSBD		11
169 
170 #define	OP_OP_COP0		0x10
171 #define	OP_OP_COP1		0x11
172 #define	OP_OP_COP2		0x12
173 #define	OP_OP_COP3		0x13
174 #define	OP_OP_LWC1		0x31
175 #define	OP_OP_LWC2		0x32
176 #define	OP_OP_LWC3		0x33	/* a.k.a. pref */
177 #define	OP_OP_LDC1		0x35
178 #define	OP_OP_LDC2		0x36
179 #define	OP_OP_LDC3		0x37	/* a.k.a. ld */
180 #define	OP_OP_SWC1		0x39
181 #define	OP_OP_SWC2		0x3a
182 #define	OP_OP_SWC3		0x3b
183 #define	OP_OP_SDC1		0x3d
184 #define	OP_OP_SDC2		0x3e
185 #define	OP_OP_SDC3		0x3f	/* a.k.a. sd */
186 
187 /* MIPS DSP ASE */
188 #define OP_SH_DSPACC		11
189 #define OP_MASK_DSPACC  	0x3
190 #define OP_SH_DSPACC_S  	21
191 #define OP_MASK_DSPACC_S	0x3
192 #define OP_SH_DSPSFT		20
193 #define OP_MASK_DSPSFT  	0x3f
194 #define OP_SH_DSPSFT_7  	19
195 #define OP_MASK_DSPSFT_7	0x7f
196 #define OP_SH_SA3		21
197 #define OP_MASK_SA3		0x7
198 #define OP_SH_SA4		21
199 #define OP_MASK_SA4		0xf
200 #define OP_SH_IMM8		16
201 #define OP_MASK_IMM8		0xff
202 #define OP_SH_IMM10		16
203 #define OP_MASK_IMM10		0x3ff
204 #define OP_SH_WRDSP		11
205 #define OP_MASK_WRDSP		0x3f
206 #define OP_SH_RDDSP		16
207 #define OP_MASK_RDDSP		0x3f
208 #define OP_SH_BP		11
209 #define OP_MASK_BP		0x3
210 
211 /* MIPS MT ASE */
212 #define OP_SH_MT_U		5
213 #define OP_MASK_MT_U		0x1
214 #define OP_SH_MT_H		4
215 #define OP_MASK_MT_H		0x1
216 #define OP_SH_MTACC_T		18
217 #define OP_MASK_MTACC_T		0x3
218 #define OP_SH_MTACC_D		13
219 #define OP_MASK_MTACC_D		0x3
220 
221 #define	OP_OP_COP0		0x10
222 #define	OP_OP_COP1		0x11
223 #define	OP_OP_COP2		0x12
224 #define	OP_OP_COP3		0x13
225 #define	OP_OP_LWC1		0x31
226 #define	OP_OP_LWC2		0x32
227 #define	OP_OP_LWC3		0x33	/* a.k.a. pref */
228 #define	OP_OP_LDC1		0x35
229 #define	OP_OP_LDC2		0x36
230 #define	OP_OP_LDC3		0x37	/* a.k.a. ld */
231 #define	OP_OP_SWC1		0x39
232 #define	OP_OP_SWC2		0x3a
233 #define	OP_OP_SWC3		0x3b
234 #define	OP_OP_SDC1		0x3d
235 #define	OP_OP_SDC2		0x3e
236 #define	OP_OP_SDC3		0x3f	/* a.k.a. sd */
237 
238 /* Values in the 'VSEL' field.  */
239 #define MDMX_FMTSEL_IMM_QH	0x1d
240 #define MDMX_FMTSEL_IMM_OB	0x1e
241 #define MDMX_FMTSEL_VEC_QH	0x15
242 #define MDMX_FMTSEL_VEC_OB	0x16
243 
244 /* UDI */
245 #define OP_SH_UDI1		6
246 #define OP_MASK_UDI1		0x1f
247 #define OP_SH_UDI2		6
248 #define OP_MASK_UDI2		0x3ff
249 #define OP_SH_UDI3		6
250 #define OP_MASK_UDI3		0x7fff
251 #define OP_SH_UDI4		6
252 #define OP_MASK_UDI4		0xfffff
253 /* This structure holds information for a particular instruction.  */
254 
255 struct mips_opcode
256 {
257   /* The name of the instruction.  */
258   const char *name;
259   /* A string describing the arguments for this instruction.  */
260   const char *args;
261   /* The basic opcode for the instruction.  When assembling, this
262      opcode is modified by the arguments to produce the actual opcode
263      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
264   unsigned long match;
265   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
266      relevant portions of the opcode when disassembling.  If the
267      actual opcode anded with the match field equals the opcode field,
268      then we have found the correct instruction.  If pinfo is
269      INSN_MACRO, then this field is the macro identifier.  */
270   unsigned long mask;
271   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
272      of bits describing the instruction, notably any relevant hazard
273      information.  */
274   unsigned long pinfo;
275   /* A collection of additional bits describing the instruction. */
276   unsigned long pinfo2;
277   /* A collection of bits describing the instruction sets of which this
278      instruction or macro is a member. */
279   unsigned long membership;
280 };
281 
282 /* These are the characters which may appear in the args field of an
283    instruction.  They appear in the order in which the fields appear
284    when the instruction is used.  Commas and parentheses in the args
285    string are ignored when assembling, and written into the output
286    when disassembling.
287 
288    Each of these characters corresponds to a mask field defined above.
289 
290    "<" 5 bit shift amount (OP_*_SHAMT)
291    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
292    "a" 26 bit target address (OP_*_TARGET)
293    "b" 5 bit base register (OP_*_RS)
294    "c" 10 bit breakpoint code (OP_*_CODE)
295    "d" 5 bit destination register specifier (OP_*_RD)
296    "h" 5 bit prefx hint (OP_*_PREFX)
297    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
298    "j" 16 bit signed immediate (OP_*_DELTA)
299    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
300        Also used for immediate operands in vr5400 vector insns.
301    "o" 16 bit signed offset (OP_*_DELTA)
302    "p" 16 bit PC relative branch target address (OP_*_DELTA)
303    "q" 10 bit extra breakpoint code (OP_*_CODE2)
304    "r" 5 bit same register used as both source and target (OP_*_RS)
305    "s" 5 bit source register specifier (OP_*_RS)
306    "t" 5 bit target register (OP_*_RT)
307    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
308    "v" 5 bit same register used as both source and destination (OP_*_RS)
309    "w" 5 bit same register used as both target and destination (OP_*_RT)
310    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
311        (used by clo and clz)
312    "C" 25 bit coprocessor function code (OP_*_COPZ)
313    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
314    "J" 19 bit wait function code (OP_*_CODE19)
315    "x" accept and ignore register name
316    "z" must be zero register
317    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
318    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
319         LSB (OP_*_SHAMT).
320 	Enforces: 0 <= pos < 32.
321    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
322 	Requires that "+A" or "+E" occur first to set position.
323 	Enforces: 0 < (pos+size) <= 32.
324    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
325 	Requires that "+A" or "+E" occur first to set position.
326 	Enforces: 0 < (pos+size) <= 32.
327 	(Also used by "dext" w/ different limits, but limits for
328 	that are checked by the M_DEXT macro.)
329    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
330 	Enforces: 32 <= pos < 64.
331    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
332 	Requires that "+A" or "+E" occur first to set position.
333 	Enforces: 32 < (pos+size) <= 64.
334    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
335 	Requires that "+A" or "+E" occur first to set position.
336 	Enforces: 32 < (pos+size) <= 64.
337    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
338 	Requires that "+A" or "+E" occur first to set position.
339 	Enforces: 32 < (pos+size) <= 64.
340 
341    Floating point instructions:
342    "D" 5 bit destination register (OP_*_FD)
343    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
344    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
345    "S" 5 bit fs source 1 register (OP_*_FS)
346    "T" 5 bit ft source 2 register (OP_*_FT)
347    "R" 5 bit fr source 3 register (OP_*_FR)
348    "V" 5 bit same register used as floating source and destination (OP_*_FS)
349    "W" 5 bit same register used as floating target and destination (OP_*_FT)
350 
351    Coprocessor instructions:
352    "E" 5 bit target register (OP_*_RT)
353    "G" 5 bit destination register (OP_*_RD)
354    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
355    "P" 5 bit performance-monitor register (OP_*_PERFREG)
356    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
357    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
358    see also "k" above
359    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
360 	for pretty-printing in disassembly only.
361 
362    Macro instructions:
363    "A" General 32 bit expression
364    "I" 32 bit immediate (value placed in imm_expr).
365    "+I" 32 bit immediate (value placed in imm2_expr).
366    "F" 64 bit floating point constant in .rdata
367    "L" 64 bit floating point constant in .lit8
368    "f" 32 bit floating point constant
369    "l" 32 bit floating point constant in .lit4
370 
371    MDMX instruction operands (note that while these use the FP register
372    fields, they accept both $fN and $vN names for the registers):
373    "O"	MDMX alignment offset (OP_*_ALN)
374    "Q"	MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
375    "X"	MDMX destination register (OP_*_FD)
376    "Y"	MDMX source register (OP_*_FS)
377    "Z"	MDMX source register (OP_*_FT)
378 
379    DSP ASE usage:
380    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
381    "3" 3 bit unsigned immediate (OP_*_SA3)
382    "4" 4 bit unsigned immediate (OP_*_SA4)
383    "5" 8 bit unsigned immediate (OP_*_IMM8)
384    "6" 5 bit unsigned immediate (OP_*_RS)
385    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
386    "8" 6 bit unsigned immediate (OP_*_WRDSP)
387    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
388    "0" 6 bit signed immediate (OP_*_DSPSFT)
389    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
390    "'" 6 bit unsigned immediate (OP_*_RDDSP)
391    "@" 10 bit signed immediate (OP_*_IMM10)
392 
393    MT ASE usage:
394    "!" 1 bit usermode flag (OP_*_MT_U)
395    "$" 1 bit load high flag (OP_*_MT_H)
396    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
397    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
398    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
399    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
400    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
401 
402    UDI immediates:
403    "+1" UDI immediate bits 6-10
404    "+2" UDI immediate bits 6-15
405    "+3" UDI immediate bits 6-20
406    "+4" UDI immediate bits 6-25
407 
408    Other:
409    "()" parens surrounding optional value
410    ","  separates operands
411    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
412    "+"  Start of extension sequence.
413 
414    Characters used so far, for quick reference when adding more:
415    "234567890"
416    "%[]<>(),+:'@!$*&"
417    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
418    "abcdefghijklopqrstuvwxz"
419 
420    Extension character sequences used so far ("+" followed by the
421    following), for quick reference when adding more:
422    "1234"
423    "ABCDEFGHIT"
424    "t"
425 */
426 
427 /* These are the bits which may be set in the pinfo field of an
428    instructions, if it is not equal to INSN_MACRO.  */
429 
430 /* Modifies the general purpose register in OP_*_RD.  */
431 #define INSN_WRITE_GPR_D            0x00000001
432 /* Modifies the general purpose register in OP_*_RT.  */
433 #define INSN_WRITE_GPR_T            0x00000002
434 /* Modifies general purpose register 31.  */
435 #define INSN_WRITE_GPR_31           0x00000004
436 /* Modifies the floating point register in OP_*_FD.  */
437 #define INSN_WRITE_FPR_D            0x00000008
438 /* Modifies the floating point register in OP_*_FS.  */
439 #define INSN_WRITE_FPR_S            0x00000010
440 /* Modifies the floating point register in OP_*_FT.  */
441 #define INSN_WRITE_FPR_T            0x00000020
442 /* Reads the general purpose register in OP_*_RS.  */
443 #define INSN_READ_GPR_S             0x00000040
444 /* Reads the general purpose register in OP_*_RT.  */
445 #define INSN_READ_GPR_T             0x00000080
446 /* Reads the floating point register in OP_*_FS.  */
447 #define INSN_READ_FPR_S             0x00000100
448 /* Reads the floating point register in OP_*_FT.  */
449 #define INSN_READ_FPR_T             0x00000200
450 /* Reads the floating point register in OP_*_FR.  */
451 #define INSN_READ_FPR_R		    0x00000400
452 /* Modifies coprocessor condition code.  */
453 #define INSN_WRITE_COND_CODE        0x00000800
454 /* Reads coprocessor condition code.  */
455 #define INSN_READ_COND_CODE         0x00001000
456 /* TLB operation.  */
457 #define INSN_TLB                    0x00002000
458 /* Reads coprocessor register other than floating point register.  */
459 #define INSN_COP                    0x00004000
460 /* Instruction loads value from memory, requiring delay.  */
461 #define INSN_LOAD_MEMORY_DELAY      0x00008000
462 /* Instruction loads value from coprocessor, requiring delay.  */
463 #define INSN_LOAD_COPROC_DELAY	    0x00010000
464 /* Instruction has unconditional branch delay slot.  */
465 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
466 /* Instruction has conditional branch delay slot.  */
467 #define INSN_COND_BRANCH_DELAY      0x00040000
468 /* Conditional branch likely: if branch not taken, insn nullified.  */
469 #define INSN_COND_BRANCH_LIKELY	    0x00080000
470 /* Moves to coprocessor register, requiring delay.  */
471 #define INSN_COPROC_MOVE_DELAY      0x00100000
472 /* Loads coprocessor register from memory, requiring delay.  */
473 #define INSN_COPROC_MEMORY_DELAY    0x00200000
474 /* Reads the HI register.  */
475 #define INSN_READ_HI		    0x00400000
476 /* Reads the LO register.  */
477 #define INSN_READ_LO		    0x00800000
478 /* Modifies the HI register.  */
479 #define INSN_WRITE_HI		    0x01000000
480 /* Modifies the LO register.  */
481 #define INSN_WRITE_LO		    0x02000000
482 /* Takes a trap (easier to keep out of delay slot).  */
483 #define INSN_TRAP                   0x04000000
484 /* Instruction stores value into memory.  */
485 #define INSN_STORE_MEMORY	    0x08000000
486 /* Instruction uses single precision floating point.  */
487 #define FP_S			    0x10000000
488 /* Instruction uses double precision floating point.  */
489 #define FP_D			    0x20000000
490 /* Instruction is part of the tx39's integer multiply family.    */
491 #define INSN_MULT                   0x40000000
492 /* Instruction synchronize shared memory.  */
493 #define INSN_SYNC		    0x80000000
494 
495 /* These are the bits which may be set in the pinfo2 field of an
496    instruction. */
497 
498 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
499 #define	INSN2_ALIAS		    0x00000001
500 /* Instruction reads MDMX accumulator. */
501 #define INSN2_READ_MDMX_ACC	    0x00000002
502 /* Instruction writes MDMX accumulator. */
503 #define INSN2_WRITE_MDMX_ACC	    0x00000004
504 
505 /* Instruction is actually a macro.  It should be ignored by the
506    disassembler, and requires special treatment by the assembler.  */
507 #define INSN_MACRO                  0xffffffff
508 
509 /* Masks used to mark instructions to indicate which MIPS ISA level
510    they were introduced in.  ISAs, as defined below, are logical
511    ORs of these bits, indicating that they support the instructions
512    defined at the given level.  */
513 
514 #define INSN_ISA_MASK		  0x00000fff
515 #define INSN_ISA1                 0x00000001
516 #define INSN_ISA2                 0x00000002
517 #define INSN_ISA3                 0x00000004
518 #define INSN_ISA4                 0x00000008
519 #define INSN_ISA5                 0x00000010
520 #define INSN_ISA32                0x00000020
521 #define INSN_ISA64                0x00000040
522 #define INSN_ISA32R2              0x00000080
523 #define INSN_ISA64R2              0x00000100
524 
525 /* Masks used for MIPS-defined ASEs.  */
526 #define INSN_ASE_MASK		  0x0000f000
527 
528 /* DSP ASE */
529 #define INSN_DSP                  0x00001000
530 #define INSN_DSP64                0x00002000
531 /* MIPS 16 ASE */
532 #define INSN_MIPS16               0x00004000
533 /* MIPS-3D ASE */
534 #define INSN_MIPS3D               0x00008000
535 
536 /* Chip specific instructions.  These are bitmasks.  */
537 
538 /* MIPS R4650 instruction.  */
539 #define INSN_4650                 0x00010000
540 /* LSI R4010 instruction.  */
541 #define INSN_4010                 0x00020000
542 /* NEC VR4100 instruction.  */
543 #define INSN_4100                 0x00040000
544 /* Toshiba R3900 instruction.  */
545 #define INSN_3900                 0x00080000
546 /* MIPS R10000 instruction.  */
547 #define INSN_10000                0x00100000
548 /* Broadcom SB-1 instruction.  */
549 #define INSN_SB1                  0x00200000
550 /* NEC VR4111/VR4181 instruction.  */
551 #define INSN_4111                 0x00400000
552 /* NEC VR4120 instruction.  */
553 #define INSN_4120                 0x00800000
554 /* NEC VR5400 instruction.  */
555 #define INSN_5400		  0x01000000
556 /* NEC VR5500 instruction.  */
557 #define INSN_5500		  0x02000000
558 
559 /* MDMX ASE */
560 #define INSN_MDMX                 0x04000000
561 /* MT ASE */
562 #define INSN_MT                   0x08000000
563 /* SmartMIPS ASE  */
564 #define INSN_SMARTMIPS            0x10000000
565 /* DSP R2 ASE  */
566 #define INSN_DSPR2                0x20000000
567 
568 /* ST Microelectronics Loongson 2E.  */
569 #define INSN_LOONGSON_2E          0x40000000
570 /* ST Microelectronics Loongson 2F.  */
571 #define INSN_LOONGSON_2F          0x80000000
572 
573 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
574 
575 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
576 #define       ISA_MIPS1       (INSN_ISA1)
577 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
578 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
579 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
580 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
581 
582 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
583 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
584 
585 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
586 #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
587 
588 
589 /* CPU defines, use instead of hardcoding processor number. Keep this
590    in sync with bfd/archures.c in order for machine selection to work.  */
591 #define CPU_UNKNOWN	0               /* Gas internal use.  */
592 #define CPU_R3000	3000
593 #define CPU_R3900	3900
594 #define CPU_R4000	4000
595 #define CPU_R4010	4010
596 #define CPU_VR4100	4100
597 #define CPU_R4111	4111
598 #define CPU_VR4120	4120
599 #define CPU_R4300	4300
600 #define CPU_R4400	4400
601 #define CPU_R4600	4600
602 #define CPU_R4650	4650
603 #define CPU_R5000	5000
604 #define CPU_VR5400	5400
605 #define CPU_VR5500	5500
606 #define CPU_R6000	6000
607 #define CPU_RM7000	7000
608 #define CPU_R8000	8000
609 #define CPU_R10000	10000
610 #define CPU_R12000	12000
611 #define CPU_MIPS16	16
612 #define CPU_MIPS32	32
613 #define CPU_MIPS32R2	33
614 #define CPU_MIPS5       5
615 #define CPU_MIPS64      64
616 #define CPU_MIPS64R2	65
617 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
618 
619 /* Test for membership in an ISA including chip specific ISAs.  INSN
620    is pointer to an element of the opcode table; ISA is the specified
621    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
622    test, or zero if no CPU specific ISA test is desired.  */
623 
624 #if 0
625 #define OPCODE_IS_MEMBER(insn, isa, cpu)				\
626     (((insn)->membership & isa) != 0					\
627      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)	\
628      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)	\
629      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)	\
630      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)	\
631      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)	\
632      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)	\
633      || ((cpu == CPU_R10000 || cpu == CPU_R12000)			\
634 	 && ((insn)->membership & INSN_10000) != 0)			\
635      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)	\
636      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)	\
637      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)	\
638      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)	\
639      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)	\
640      || 0)	/* Please keep this term for easier source merging.  */
641 #else
642 #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
643     (1 != 0)
644 #endif
645 
646 /* This is a list of macro expanded instructions.
647 
648    _I appended means immediate
649    _A appended means address
650    _AB appended means address with base register
651    _D appended means 64 bit floating point constant
652    _S appended means 32 bit floating point constant.  */
653 
654 enum
655 {
656   M_ABS,
657   M_ADD_I,
658   M_ADDU_I,
659   M_AND_I,
660   M_BALIGN,
661   M_BEQ,
662   M_BEQ_I,
663   M_BEQL_I,
664   M_BGE,
665   M_BGEL,
666   M_BGE_I,
667   M_BGEL_I,
668   M_BGEU,
669   M_BGEUL,
670   M_BGEU_I,
671   M_BGEUL_I,
672   M_BGT,
673   M_BGTL,
674   M_BGT_I,
675   M_BGTL_I,
676   M_BGTU,
677   M_BGTUL,
678   M_BGTU_I,
679   M_BGTUL_I,
680   M_BLE,
681   M_BLEL,
682   M_BLE_I,
683   M_BLEL_I,
684   M_BLEU,
685   M_BLEUL,
686   M_BLEU_I,
687   M_BLEUL_I,
688   M_BLT,
689   M_BLTL,
690   M_BLT_I,
691   M_BLTL_I,
692   M_BLTU,
693   M_BLTUL,
694   M_BLTU_I,
695   M_BLTUL_I,
696   M_BNE,
697   M_BNE_I,
698   M_BNEL_I,
699   M_CACHE_AB,
700   M_DABS,
701   M_DADD_I,
702   M_DADDU_I,
703   M_DDIV_3,
704   M_DDIV_3I,
705   M_DDIVU_3,
706   M_DDIVU_3I,
707   M_DEXT,
708   M_DINS,
709   M_DIV_3,
710   M_DIV_3I,
711   M_DIVU_3,
712   M_DIVU_3I,
713   M_DLA_AB,
714   M_DLCA_AB,
715   M_DLI,
716   M_DMUL,
717   M_DMUL_I,
718   M_DMULO,
719   M_DMULO_I,
720   M_DMULOU,
721   M_DMULOU_I,
722   M_DREM_3,
723   M_DREM_3I,
724   M_DREMU_3,
725   M_DREMU_3I,
726   M_DSUB_I,
727   M_DSUBU_I,
728   M_DSUBU_I_2,
729   M_J_A,
730   M_JAL_1,
731   M_JAL_2,
732   M_JAL_A,
733   M_L_DOB,
734   M_L_DAB,
735   M_LA_AB,
736   M_LB_A,
737   M_LB_AB,
738   M_LBU_A,
739   M_LBU_AB,
740   M_LCA_AB,
741   M_LD_A,
742   M_LD_OB,
743   M_LD_AB,
744   M_LDC1_AB,
745   M_LDC2_AB,
746   M_LDC3_AB,
747   M_LDL_AB,
748   M_LDR_AB,
749   M_LH_A,
750   M_LH_AB,
751   M_LHU_A,
752   M_LHU_AB,
753   M_LI,
754   M_LI_D,
755   M_LI_DD,
756   M_LI_S,
757   M_LI_SS,
758   M_LL_AB,
759   M_LLD_AB,
760   M_LS_A,
761   M_LW_A,
762   M_LW_AB,
763   M_LWC0_A,
764   M_LWC0_AB,
765   M_LWC1_A,
766   M_LWC1_AB,
767   M_LWC2_A,
768   M_LWC2_AB,
769   M_LWC3_A,
770   M_LWC3_AB,
771   M_LWL_A,
772   M_LWL_AB,
773   M_LWR_A,
774   M_LWR_AB,
775   M_LWU_AB,
776   M_MOVE,
777   M_MUL,
778   M_MUL_I,
779   M_MULO,
780   M_MULO_I,
781   M_MULOU,
782   M_MULOU_I,
783   M_NOR_I,
784   M_OR_I,
785   M_REM_3,
786   M_REM_3I,
787   M_REMU_3,
788   M_REMU_3I,
789   M_DROL,
790   M_ROL,
791   M_DROL_I,
792   M_ROL_I,
793   M_DROR,
794   M_ROR,
795   M_DROR_I,
796   M_ROR_I,
797   M_S_DA,
798   M_S_DOB,
799   M_S_DAB,
800   M_S_S,
801   M_SC_AB,
802   M_SCD_AB,
803   M_SD_A,
804   M_SD_OB,
805   M_SD_AB,
806   M_SDC1_AB,
807   M_SDC2_AB,
808   M_SDC3_AB,
809   M_SDL_AB,
810   M_SDR_AB,
811   M_SEQ,
812   M_SEQ_I,
813   M_SGE,
814   M_SGE_I,
815   M_SGEU,
816   M_SGEU_I,
817   M_SGT,
818   M_SGT_I,
819   M_SGTU,
820   M_SGTU_I,
821   M_SLE,
822   M_SLE_I,
823   M_SLEU,
824   M_SLEU_I,
825   M_SLT_I,
826   M_SLTU_I,
827   M_SNE,
828   M_SNE_I,
829   M_SB_A,
830   M_SB_AB,
831   M_SH_A,
832   M_SH_AB,
833   M_SW_A,
834   M_SW_AB,
835   M_SWC0_A,
836   M_SWC0_AB,
837   M_SWC1_A,
838   M_SWC1_AB,
839   M_SWC2_A,
840   M_SWC2_AB,
841   M_SWC3_A,
842   M_SWC3_AB,
843   M_SWL_A,
844   M_SWL_AB,
845   M_SWR_A,
846   M_SWR_AB,
847   M_SUB_I,
848   M_SUBU_I,
849   M_SUBU_I_2,
850   M_TEQ_I,
851   M_TGE_I,
852   M_TGEU_I,
853   M_TLT_I,
854   M_TLTU_I,
855   M_TNE_I,
856   M_TRUNCWD,
857   M_TRUNCWS,
858   M_ULD,
859   M_ULD_A,
860   M_ULH,
861   M_ULH_A,
862   M_ULHU,
863   M_ULHU_A,
864   M_ULW,
865   M_ULW_A,
866   M_USH,
867   M_USH_A,
868   M_USW,
869   M_USW_A,
870   M_USD,
871   M_USD_A,
872   M_XOR_I,
873   M_COP0,
874   M_COP1,
875   M_COP2,
876   M_COP3,
877   M_NUM_MACROS
878 };
879 
880 
881 /* The order of overloaded instructions matters.  Label arguments and
882    register arguments look the same. Instructions that can have either
883    for arguments must apear in the correct order in this table for the
884    assembler to pick the right one. In other words, entries with
885    immediate operands must apear after the same instruction with
886    registers.
887 
888    Many instructions are short hand for other instructions (i.e., The
889    jal <register> instruction is short for jalr <register>).  */
890 
891 extern const struct mips_opcode mips_builtin_opcodes[];
892 extern const int bfd_mips_num_builtin_opcodes;
893 extern struct mips_opcode *mips_opcodes;
894 extern int bfd_mips_num_opcodes;
895 #define NUMOPCODES bfd_mips_num_opcodes
896 
897 
898 /* The rest of this file adds definitions for the mips16 TinyRISC
899    processor.  */
900 
901 /* These are the bitmasks and shift counts used for the different
902    fields in the instruction formats.  Other than OP, no masks are
903    provided for the fixed portions of an instruction, since they are
904    not needed.
905 
906    The I format uses IMM11.
907 
908    The RI format uses RX and IMM8.
909 
910    The RR format uses RX, and RY.
911 
912    The RRI format uses RX, RY, and IMM5.
913 
914    The RRR format uses RX, RY, and RZ.
915 
916    The RRI_A format uses RX, RY, and IMM4.
917 
918    The SHIFT format uses RX, RY, and SHAMT.
919 
920    The I8 format uses IMM8.
921 
922    The I8_MOVR32 format uses RY and REGR32.
923 
924    The IR_MOV32R format uses REG32R and MOV32Z.
925 
926    The I64 format uses IMM8.
927 
928    The RI64 format uses RY and IMM5.
929    */
930 
931 #define MIPS16OP_MASK_OP	0x1f
932 #define MIPS16OP_SH_OP		11
933 #define MIPS16OP_MASK_IMM11	0x7ff
934 #define MIPS16OP_SH_IMM11	0
935 #define MIPS16OP_MASK_RX	0x7
936 #define MIPS16OP_SH_RX		8
937 #define MIPS16OP_MASK_IMM8	0xff
938 #define MIPS16OP_SH_IMM8	0
939 #define MIPS16OP_MASK_RY	0x7
940 #define MIPS16OP_SH_RY		5
941 #define MIPS16OP_MASK_IMM5	0x1f
942 #define MIPS16OP_SH_IMM5	0
943 #define MIPS16OP_MASK_RZ	0x7
944 #define MIPS16OP_SH_RZ		2
945 #define MIPS16OP_MASK_IMM4	0xf
946 #define MIPS16OP_SH_IMM4	0
947 #define MIPS16OP_MASK_REGR32	0x1f
948 #define MIPS16OP_SH_REGR32	0
949 #define MIPS16OP_MASK_REG32R	0x1f
950 #define MIPS16OP_SH_REG32R	3
951 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
952 #define MIPS16OP_MASK_MOVE32Z	0x7
953 #define MIPS16OP_SH_MOVE32Z	0
954 #define MIPS16OP_MASK_IMM6	0x3f
955 #define MIPS16OP_SH_IMM6	5
956 
957 /* These are the characters which may appears in the args field of an
958    instruction.  They appear in the order in which the fields appear
959    when the instruction is used.  Commas and parentheses in the args
960    string are ignored when assembling, and written into the output
961    when disassembling.
962 
963    "y" 3 bit register (MIPS16OP_*_RY)
964    "x" 3 bit register (MIPS16OP_*_RX)
965    "z" 3 bit register (MIPS16OP_*_RZ)
966    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
967    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
968    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
969    "0" zero register ($0)
970    "S" stack pointer ($sp or $29)
971    "P" program counter
972    "R" return address register ($ra or $31)
973    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
974    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
975    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
976    "a" 26 bit jump address
977    "e" 11 bit extension value
978    "l" register list for entry instruction
979    "L" register list for exit instruction
980 
981    The remaining codes may be extended.  Except as otherwise noted,
982    the full extended operand is a 16 bit signed value.
983    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
984    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
985    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
986    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
987    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
988    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
989    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
990    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
991    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
992    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
993    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
994    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
995    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
996    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
997    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
998    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
999    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1000    "q" 11 bit branch address (MIPS16OP_*_IMM11)
1001    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1002    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1003    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1004    */
1005 
1006 /* Save/restore encoding for the args field when all 4 registers are
1007    either saved as arguments or saved/restored as statics.  */
1008 #define MIPS16_ALL_ARGS    0xe
1009 #define MIPS16_ALL_STATICS 0xb
1010 
1011 /* For the mips16, we use the same opcode table format and a few of
1012    the same flags.  However, most of the flags are different.  */
1013 
1014 /* Modifies the register in MIPS16OP_*_RX.  */
1015 #define MIPS16_INSN_WRITE_X		    0x00000001
1016 /* Modifies the register in MIPS16OP_*_RY.  */
1017 #define MIPS16_INSN_WRITE_Y		    0x00000002
1018 /* Modifies the register in MIPS16OP_*_RZ.  */
1019 #define MIPS16_INSN_WRITE_Z		    0x00000004
1020 /* Modifies the T ($24) register.  */
1021 #define MIPS16_INSN_WRITE_T		    0x00000008
1022 /* Modifies the SP ($29) register.  */
1023 #define MIPS16_INSN_WRITE_SP		    0x00000010
1024 /* Modifies the RA ($31) register.  */
1025 #define MIPS16_INSN_WRITE_31		    0x00000020
1026 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1027 #define MIPS16_INSN_WRITE_GPR_Y		    0x00000040
1028 /* Reads the register in MIPS16OP_*_RX.  */
1029 #define MIPS16_INSN_READ_X		    0x00000080
1030 /* Reads the register in MIPS16OP_*_RY.  */
1031 #define MIPS16_INSN_READ_Y		    0x00000100
1032 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1033 #define MIPS16_INSN_READ_Z		    0x00000200
1034 /* Reads the T ($24) register.  */
1035 #define MIPS16_INSN_READ_T		    0x00000400
1036 /* Reads the SP ($29) register.  */
1037 #define MIPS16_INSN_READ_SP		    0x00000800
1038 /* Reads the RA ($31) register.  */
1039 #define MIPS16_INSN_READ_31		    0x00001000
1040 /* Reads the program counter.  */
1041 #define MIPS16_INSN_READ_PC		    0x00002000
1042 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1043 #define MIPS16_INSN_READ_GPR_X		    0x00004000
1044 /* Is a branch insn. */
1045 #define MIPS16_INSN_BRANCH                  0x00010000
1046 
1047 /* The following flags have the same value for the mips16 opcode
1048    table:
1049    INSN_UNCOND_BRANCH_DELAY
1050    INSN_COND_BRANCH_DELAY
1051    INSN_COND_BRANCH_LIKELY (never used)
1052    INSN_READ_HI
1053    INSN_READ_LO
1054    INSN_WRITE_HI
1055    INSN_WRITE_LO
1056    INSN_TRAP
1057    INSN_ISA3
1058    */
1059 
1060 extern const struct mips_opcode mips16_opcodes[];
1061 extern const int bfd_mips16_num_opcodes;
1062 
1063 /* Short hand so the lines aren't too long.  */
1064 
1065 #define LDD     INSN_LOAD_MEMORY_DELAY
1066 #define LCD	INSN_LOAD_COPROC_DELAY
1067 #define UBD     INSN_UNCOND_BRANCH_DELAY
1068 #define CBD	INSN_COND_BRANCH_DELAY
1069 #define COD     INSN_COPROC_MOVE_DELAY
1070 #define CLD	INSN_COPROC_MEMORY_DELAY
1071 #define CBL	INSN_COND_BRANCH_LIKELY
1072 #define TRAP	INSN_TRAP
1073 #define SM	INSN_STORE_MEMORY
1074 
1075 #define WR_d    INSN_WRITE_GPR_D
1076 #define WR_t    INSN_WRITE_GPR_T
1077 #define WR_31   INSN_WRITE_GPR_31
1078 #define WR_D    INSN_WRITE_FPR_D
1079 #define WR_T	INSN_WRITE_FPR_T
1080 #define WR_S	INSN_WRITE_FPR_S
1081 #define RD_s    INSN_READ_GPR_S
1082 #define RD_b    INSN_READ_GPR_S
1083 #define RD_t    INSN_READ_GPR_T
1084 #define RD_S    INSN_READ_FPR_S
1085 #define RD_T    INSN_READ_FPR_T
1086 #define RD_R	INSN_READ_FPR_R
1087 #define WR_CC	INSN_WRITE_COND_CODE
1088 #define RD_CC	INSN_READ_COND_CODE
1089 #define RD_C0   INSN_COP
1090 #define RD_C1	INSN_COP
1091 #define RD_C2   INSN_COP
1092 #define RD_C3   INSN_COP
1093 #define WR_C0   INSN_COP
1094 #define WR_C1	INSN_COP
1095 #define WR_C2   INSN_COP
1096 #define WR_C3   INSN_COP
1097 
1098 #define WR_HI	INSN_WRITE_HI
1099 #define RD_HI	INSN_READ_HI
1100 #define MOD_HI  WR_HI|RD_HI
1101 
1102 #define WR_LO	INSN_WRITE_LO
1103 #define RD_LO	INSN_READ_LO
1104 #define MOD_LO  WR_LO|RD_LO
1105 
1106 #define WR_HILO WR_HI|WR_LO
1107 #define RD_HILO RD_HI|RD_LO
1108 #define MOD_HILO WR_HILO|RD_HILO
1109 
1110 #define IS_M    INSN_MULT
1111 
1112 #define WR_MACC INSN2_WRITE_MDMX_ACC
1113 #define RD_MACC INSN2_READ_MDMX_ACC
1114 
1115 #define I1	INSN_ISA1
1116 #define I2	INSN_ISA2
1117 #define I3	INSN_ISA3
1118 #define I4	INSN_ISA4
1119 #define I5	INSN_ISA5
1120 #define I32	INSN_ISA32
1121 #define I64     INSN_ISA64
1122 #define I33	INSN_ISA32R2
1123 #define I65	INSN_ISA64R2
1124 
1125 /* MIPS64 MIPS-3D ASE support.  */
1126 #define I16     INSN_MIPS16
1127 
1128 /* MIPS32 SmartMIPS ASE support.  */
1129 #define SMT	INSN_SMARTMIPS
1130 
1131 /* MIPS64 MIPS-3D ASE support.  */
1132 #define M3D     INSN_MIPS3D
1133 
1134 /* MIPS64 MDMX ASE support.  */
1135 #define MX      INSN_MDMX
1136 
1137 #define IL2E	(INSN_LOONGSON_2E)
1138 #define IL2F	(INSN_LOONGSON_2F)
1139 
1140 #define P3	INSN_4650
1141 #define L1	INSN_4010
1142 #define V1	(INSN_4100 | INSN_4111 | INSN_4120)
1143 #define T3      INSN_3900
1144 #define M1	INSN_10000
1145 #define SB1     INSN_SB1
1146 #define N411	INSN_4111
1147 #define N412	INSN_4120
1148 #define N5	(INSN_5400 | INSN_5500)
1149 #define N54	INSN_5400
1150 #define N55	INSN_5500
1151 
1152 #define G1      (T3             \
1153                  )
1154 
1155 #define G2      (T3             \
1156                  )
1157 
1158 #define G3      (I4             \
1159                  )
1160 
1161 /* MIPS DSP ASE support.
1162    NOTE:
1163    1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
1164    of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have
1165    the same structure as $ac0 (HI + LO).  For DSP instructions that write or
1166    read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1167    (RD_HILO) attributes, such that HILO dependencies are maintained
1168    conservatively.
1169 
1170    2. For some mul. instructions that use integer registers as destinations
1171    but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1172 
1173    3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1174    (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write
1175    certain fields of the DSP control register.  For simplicity, we decide not
1176    to track dependencies of these fields.
1177    However, "bposge32" is a branch instruction that depends on the "pos"
1178    field.  In order to make sure that GAS does not reorder DSP instructions
1179    that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1180    attribute to those instructions that write the "pos" field.  */
1181 
1182 #define WR_a	WR_HILO	/* Write dsp accumulators (reuse WR_HILO)  */
1183 #define RD_a	RD_HILO	/* Read dsp accumulators (reuse RD_HILO)  */
1184 #define MOD_a	WR_a|RD_a
1185 #define DSP_VOLA	INSN_TRAP
1186 #define D32	INSN_DSP
1187 #define D33	INSN_DSPR2
1188 #define D64	INSN_DSP64
1189 
1190 /* MIPS MT ASE support.  */
1191 #define MT32	INSN_MT
1192 
1193 /* The order of overloaded instructions matters.  Label arguments and
1194    register arguments look the same. Instructions that can have either
1195    for arguments must apear in the correct order in this table for the
1196    assembler to pick the right one. In other words, entries with
1197    immediate operands must apear after the same instruction with
1198    registers.
1199 
1200    Because of the lookup algorithm used, entries with the same opcode
1201    name must be contiguous.
1202 
1203    Many instructions are short hand for other instructions (i.e., The
1204    jal <register> instruction is short for jalr <register>).  */
1205 
1206 const struct mips_opcode mips_builtin_opcodes[] =
1207 {
1208 /* These instructions appear first so that the disassembler will find
1209    them first.  The assemblers uses a hash table based on the
1210    instruction name anyhow.  */
1211 /* name,    args,	match,	    mask,	pinfo,          	membership */
1212 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           	0,		I4|I32|G3	},
1213 {"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t,		0,		I4|I33	},
1214 {"nop",     "",         0x00000000, 0xffffffff, 0,              	INSN2_ALIAS,	I1      }, /* sll */
1215 {"ssnop",   "",         0x00000040, 0xffffffff, 0,              	INSN2_ALIAS,	I32|N55	}, /* sll */
1216 {"ehb",     "",         0x000000c0, 0xffffffff, 0,              	INSN2_ALIAS,	I33	}, /* sll */
1217 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,			INSN2_ALIAS,	I1	}, /* addiu */
1218 {"li",	    "t,i",	0x34000000, 0xffe00000, WR_t,			INSN2_ALIAS,	I1	}, /* ori */
1219 {"li",      "t,I",	0,    (int) M_LI,	INSN_MACRO,		0,		I1	},
1220 {"move",    "d,s",	0,    (int) M_MOVE,	INSN_MACRO,		0,		I1	},
1221 {"move",    "d,s",	0x0000002d, 0xfc1f07ff, WR_d|RD_s,		INSN2_ALIAS,	I3	},/* daddu */
1222 {"move",    "d,s",	0x00000021, 0xfc1f07ff, WR_d|RD_s,		INSN2_ALIAS,	I1	},/* addu */
1223 {"move",    "d,s",	0x00000025, 0xfc1f07ff,	WR_d|RD_s,		INSN2_ALIAS,	I1	},/* or */
1224 {"b",       "p",	0x10000000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1	},/* beq 0,0 */
1225 {"b",       "p",	0x04010000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1	},/* bgez 0 */
1226 {"bal",     "p",	0x04110000, 0xffff0000,	UBD|WR_31,		INSN2_ALIAS,	I1	},/* bgezal 0*/
1227 
1228 {"abs",     "d,v",	0,    (int) M_ABS,	INSN_MACRO,		0,		I1	},
1229 {"abs.s",   "D,V",	0x46000005, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
1230 {"abs.d",   "D,V",	0x46200005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
1231 {"abs.ps",  "D,V",	0x46c00005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I5|I33	},
1232 {"add",     "d,v,t",	0x00000020, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
1233 {"add",     "t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,		0,		I1	},
1234 {"add.s",   "D,V,T",	0x46000000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
1235 {"add.d",   "D,V,T",	0x46200000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
1236 {"add.ob",  "X,Y,Q",	0x7800000b, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
1237 {"add.ob",  "D,S,T",	0x4ac0000b, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
1238 {"add.ob",  "D,S,T[e]",	0x4800000b, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
1239 {"add.ob",  "D,S,k",	0x4bc0000b, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
1240 {"add.ps",  "D,V,T",	0x46c00000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5|I33	},
1241 {"add.qh",  "X,Y,Q",	0x7820000b, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
1242 {"adda.ob", "Y,Q",	0x78000037, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
1243 {"adda.qh", "Y,Q",	0x78200037, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
1244 {"addi",    "t,r,j",	0x20000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
1245 {"addiu",   "t,r,j",	0x24000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
1246 {"addl.ob", "Y,Q",	0x78000437, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
1247 {"addl.qh", "Y,Q",	0x78200437, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
1248 {"addr.ps", "D,S,T",	0x46c00018, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		M3D	},
1249 {"addu",    "d,v,t",	0x00000021, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
1250 {"addu",    "t,r,I",	0,    (int) M_ADDU_I,	INSN_MACRO,		0,		I1	},
1251 {"alni.ob", "X,Y,Z,O",	0x78000018, 0xff00003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
1252 {"alni.ob", "D,S,T,%",	0x48000018, 0xff00003f,	WR_D|RD_S|RD_T, 	0,		N54	},
1253 {"alni.qh", "X,Y,Z,O",	0x7800001a, 0xff00003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
1254 {"alnv.ps", "D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5|I33	},
1255 {"alnv.ob", "X,Y,Z,s",	0x78000019, 0xfc00003f,	WR_D|RD_S|RD_T|RD_s|FP_D, 0,		MX|SB1	},
1256 {"alnv.qh", "X,Y,Z,s",	0x7800001b, 0xfc00003f,	WR_D|RD_S|RD_T|RD_s|FP_D, 0,		MX	},
1257 {"and",     "d,v,t",	0x00000024, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
1258 {"and",     "t,r,I",	0,    (int) M_AND_I,	INSN_MACRO,		0,		I1	},
1259 {"and.ob",  "X,Y,Q",	0x7800000c, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
1260 {"and.ob",  "D,S,T",	0x4ac0000c, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
1261 {"and.ob",  "D,S,T[e]",	0x4800000c, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
1262 {"and.ob",  "D,S,k",	0x4bc0000c, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
1263 {"and.qh",  "X,Y,Q",	0x7820000c, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
1264 {"andi",    "t,r,i",	0x30000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
1265 /* b is at the top of the table.  */
1266 /* bal is at the top of the table.  */
1267 /* bc0[tf]l? are at the bottom of the table.  */
1268 {"bc1any2f", "N,p",	0x45200000, 0xffe30000,	CBD|RD_CC|FP_S,		0,		M3D	},
1269 {"bc1any2t", "N,p",	0x45210000, 0xffe30000,	CBD|RD_CC|FP_S,		0,		M3D	},
1270 {"bc1any4f", "N,p",	0x45400000, 0xffe30000,	CBD|RD_CC|FP_S,		0,		M3D	},
1271 {"bc1any4t", "N,p",	0x45410000, 0xffe30000,	CBD|RD_CC|FP_S,		0,		M3D	},
1272 {"bc1f",    "p",	0x45000000, 0xffff0000,	CBD|RD_CC|FP_S,		0,		I1	},
1273 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 	0,		I4|I32	},
1274 {"bc1fl",   "p",	0x45020000, 0xffff0000,	CBL|RD_CC|FP_S,		0,		I2|T3	},
1275 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 	0,		I4|I32	},
1276 {"bc1t",    "p",	0x45010000, 0xffff0000,	CBD|RD_CC|FP_S,		0,		I1	},
1277 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 	0,		I4|I32	},
1278 {"bc1tl",   "p",	0x45030000, 0xffff0000,	CBL|RD_CC|FP_S,		0,		I2|T3	},
1279 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 	0,		I4|I32	},
1280 /* bc2* are at the bottom of the table.  */
1281 /* bc3* are at the bottom of the table.  */
1282 {"beqz",    "s,p",	0x10000000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
1283 {"beqzl",   "s,p",	0x50000000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
1284 {"beq",     "s,t,p",	0x10000000, 0xfc000000,	CBD|RD_s|RD_t,		0,		I1	},
1285 {"beq",     "s,I,p",	0,    (int) M_BEQ_I,	INSN_MACRO,		0,		I1	},
1286 {"beql",    "s,t,p",	0x50000000, 0xfc000000,	CBL|RD_s|RD_t,		0,		I2|T3	},
1287 {"beql",    "s,I,p",	0,    (int) M_BEQL_I,	INSN_MACRO,		0,		I2|T3	},
1288 {"bge",     "s,t,p",	0,    (int) M_BGE,	INSN_MACRO,		0,		I1	},
1289 {"bge",     "s,I,p",	0,    (int) M_BGE_I,	INSN_MACRO,		0,		I1	},
1290 {"bgel",    "s,t,p",	0,    (int) M_BGEL,	INSN_MACRO,		0,		I2|T3	},
1291 {"bgel",    "s,I,p",	0,    (int) M_BGEL_I,	INSN_MACRO,		0,		I2|T3	},
1292 {"bgeu",    "s,t,p",	0,    (int) M_BGEU,	INSN_MACRO,		0,		I1	},
1293 {"bgeu",    "s,I,p",	0,    (int) M_BGEU_I,	INSN_MACRO,		0,		I1	},
1294 {"bgeul",   "s,t,p",	0,    (int) M_BGEUL,	INSN_MACRO,		0,		I2|T3	},
1295 {"bgeul",   "s,I,p",	0,    (int) M_BGEUL_I,	INSN_MACRO,		0,		I2|T3	},
1296 {"bgez",    "s,p",	0x04010000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
1297 {"bgezl",   "s,p",	0x04030000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
1298 {"bgezal",  "s,p",	0x04110000, 0xfc1f0000,	CBD|RD_s|WR_31,		0,		I1	},
1299 {"bgezall", "s,p",	0x04130000, 0xfc1f0000,	CBL|RD_s|WR_31,		0,		I2|T3	},
1300 {"bgt",     "s,t,p",	0,    (int) M_BGT,	INSN_MACRO,		0,		I1	},
1301 {"bgt",     "s,I,p",	0,    (int) M_BGT_I,	INSN_MACRO,		0,		I1	},
1302 {"bgtl",    "s,t,p",	0,    (int) M_BGTL,	INSN_MACRO,		0,		I2|T3	},
1303 {"bgtl",    "s,I,p",	0,    (int) M_BGTL_I,	INSN_MACRO,		0,		I2|T3	},
1304 {"bgtu",    "s,t,p",	0,    (int) M_BGTU,	INSN_MACRO,		0,		I1	},
1305 {"bgtu",    "s,I,p",	0,    (int) M_BGTU_I,	INSN_MACRO,		0,		I1	},
1306 {"bgtul",   "s,t,p",	0,    (int) M_BGTUL,	INSN_MACRO,		0,		I2|T3	},
1307 {"bgtul",   "s,I,p",	0,    (int) M_BGTUL_I,	INSN_MACRO,		0,		I2|T3	},
1308 {"bgtz",    "s,p",	0x1c000000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
1309 {"bgtzl",   "s,p",	0x5c000000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
1310 {"ble",     "s,t,p",	0,    (int) M_BLE,	INSN_MACRO,		0,		I1	},
1311 {"ble",     "s,I,p",	0,    (int) M_BLE_I,	INSN_MACRO,		0,		I1	},
1312 {"blel",    "s,t,p",	0,    (int) M_BLEL,	INSN_MACRO,		0,		I2|T3	},
1313 {"blel",    "s,I,p",	0,    (int) M_BLEL_I,	INSN_MACRO,		0,		I2|T3	},
1314 {"bleu",    "s,t,p",	0,    (int) M_BLEU,	INSN_MACRO,		0,		I1	},
1315 {"bleu",    "s,I,p",	0,    (int) M_BLEU_I,	INSN_MACRO,		0,		I1	},
1316 {"bleul",   "s,t,p",	0,    (int) M_BLEUL,	INSN_MACRO,		0,		I2|T3	},
1317 {"bleul",   "s,I,p",	0,    (int) M_BLEUL_I,	INSN_MACRO,		0,		I2|T3	},
1318 {"blez",    "s,p",	0x18000000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
1319 {"blezl",   "s,p",	0x58000000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
1320 {"blt",     "s,t,p",	0,    (int) M_BLT,	INSN_MACRO,		0,		I1	},
1321 {"blt",     "s,I,p",	0,    (int) M_BLT_I,	INSN_MACRO,		0,		I1	},
1322 {"bltl",    "s,t,p",	0,    (int) M_BLTL,	INSN_MACRO,		0,		I2|T3	},
1323 {"bltl",    "s,I,p",	0,    (int) M_BLTL_I,	INSN_MACRO,		0,		I2|T3	},
1324 {"bltu",    "s,t,p",	0,    (int) M_BLTU,	INSN_MACRO,		0,		I1	},
1325 {"bltu",    "s,I,p",	0,    (int) M_BLTU_I,	INSN_MACRO,		0,		I1	},
1326 {"bltul",   "s,t,p",	0,    (int) M_BLTUL,	INSN_MACRO,		0,		I2|T3	},
1327 {"bltul",   "s,I,p",	0,    (int) M_BLTUL_I,	INSN_MACRO,		0,		I2|T3	},
1328 {"bltz",    "s,p",	0x04000000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
1329 {"bltzl",   "s,p",	0x04020000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
1330 {"bltzal",  "s,p",	0x04100000, 0xfc1f0000,	CBD|RD_s|WR_31,		0,		I1	},
1331 {"bltzall", "s,p",	0x04120000, 0xfc1f0000,	CBL|RD_s|WR_31,		0,		I2|T3	},
1332 {"bnez",    "s,p",	0x14000000, 0xfc1f0000,	CBD|RD_s,		0,		I1	},
1333 {"bnezl",   "s,p",	0x54000000, 0xfc1f0000,	CBL|RD_s,		0,		I2|T3	},
1334 {"bne",     "s,t,p",	0x14000000, 0xfc000000,	CBD|RD_s|RD_t,		0,		I1	},
1335 {"bne",     "s,I,p",	0,    (int) M_BNE_I,	INSN_MACRO,		0,		I1	},
1336 {"bnel",    "s,t,p",	0x54000000, 0xfc000000,	CBL|RD_s|RD_t, 		0,		I2|T3	},
1337 {"bnel",    "s,I,p",	0,    (int) M_BNEL_I,	INSN_MACRO,		0,		I2|T3	},
1338 {"break",   "",		0x0000000d, 0xffffffff,	TRAP,			0,		I1	},
1339 {"break",   "c",	0x0000000d, 0xfc00ffff,	TRAP,			0,		I1	},
1340 {"break",   "c,q",	0x0000000d, 0xfc00003f,	TRAP,			0,		I1	},
1341 {"c.f.d",   "S,T",	0x46200030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1342 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1343 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1344 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1345 {"c.f.ps",  "S,T",	0x46c00030, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1346 {"c.f.ps",  "M,S,T",	0x46c00030, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1347 {"c.un.d",  "S,T",	0x46200031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1348 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1349 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1350 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1351 {"c.un.ps", "S,T",	0x46c00031, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1352 {"c.un.ps", "M,S,T",	0x46c00031, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1353 {"c.eq.d",  "S,T",	0x46200032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1354 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1355 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1356 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1357 {"c.eq.ob", "Y,Q",	0x78000001, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX|SB1	},
1358 {"c.eq.ob", "S,T",	0x4ac00001, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1359 {"c.eq.ob", "S,T[e]",	0x48000001, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1360 {"c.eq.ob", "S,k",	0x4bc00001, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1361 {"c.eq.ps", "S,T",	0x46c00032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1362 {"c.eq.ps", "M,S,T",	0x46c00032, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1363 {"c.eq.qh", "Y,Q",	0x78200001, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX	},
1364 {"c.ueq.d", "S,T",	0x46200033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1365 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1366 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1367 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1368 {"c.ueq.ps","S,T",	0x46c00033, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1369 {"c.ueq.ps","M,S,T",	0x46c00033, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1370 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,		I1      },
1371 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1372 {"c.olt.s", "S,T",	0x46000034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1	},
1373 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1374 {"c.olt.ps","S,T",	0x46c00034, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1375 {"c.olt.ps","M,S,T",	0x46c00034, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1376 {"c.ult.d", "S,T",	0x46200035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1377 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1378 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1379 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1380 {"c.ult.ps","S,T",	0x46c00035, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1381 {"c.ult.ps","M,S,T",	0x46c00035, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1382 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,		I1      },
1383 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1384 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1385 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1386 {"c.ole.ps","S,T",	0x46c00036, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1387 {"c.ole.ps","M,S,T",	0x46c00036, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1388 {"c.ule.d", "S,T",	0x46200037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1389 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1390 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1391 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1392 {"c.ule.ps","S,T",	0x46c00037, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1393 {"c.ule.ps","M,S,T",	0x46c00037, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1394 {"c.sf.d",  "S,T",	0x46200038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1395 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1396 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1397 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1398 {"c.sf.ps", "S,T",	0x46c00038, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1399 {"c.sf.ps", "M,S,T",	0x46c00038, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1400 {"c.ngle.d","S,T",	0x46200039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1401 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1402 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1403 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1404 {"c.ngle.ps","S,T",	0x46c00039, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1405 {"c.ngle.ps","M,S,T",	0x46c00039, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1406 {"c.seq.d", "S,T",	0x4620003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1407 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1408 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1409 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1410 {"c.seq.ps","S,T",	0x46c0003a, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1411 {"c.seq.ps","M,S,T",	0x46c0003a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1412 {"c.ngl.d", "S,T",	0x4620003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1413 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1414 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1415 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1416 {"c.ngl.ps","S,T",	0x46c0003b, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1417 {"c.ngl.ps","M,S,T",	0x46c0003b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1418 {"c.lt.d",  "S,T",	0x4620003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1419 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1420 {"c.lt.s",  "S,T",	0x4600003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1	},
1421 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1422 {"c.lt.ob", "Y,Q",	0x78000004, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX|SB1	},
1423 {"c.lt.ob", "S,T",	0x4ac00004, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1424 {"c.lt.ob", "S,T[e]",	0x48000004, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1425 {"c.lt.ob", "S,k",	0x4bc00004, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1426 {"c.lt.ps", "S,T",	0x46c0003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1427 {"c.lt.ps", "M,S,T",	0x46c0003c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1428 {"c.lt.qh", "Y,Q",	0x78200004, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX	},
1429 {"c.nge.d", "S,T",	0x4620003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1430 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1431 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1432 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1433 {"c.nge.ps","S,T",	0x46c0003d, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1434 {"c.nge.ps","M,S,T",	0x46c0003d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1435 {"c.le.d",  "S,T",	0x4620003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1436 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1437 {"c.le.s",  "S,T",	0x4600003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1	},
1438 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1439 {"c.le.ob", "Y,Q",	0x78000005, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX|SB1	},
1440 {"c.le.ob", "S,T",	0x4ac00005, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1441 {"c.le.ob", "S,T[e]",	0x48000005, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1442 {"c.le.ob", "S,k",	0x4bc00005, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1443 {"c.le.ps", "S,T",	0x46c0003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1444 {"c.le.ps", "M,S,T",	0x46c0003e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1445 {"c.le.qh", "Y,Q",	0x78200005, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		MX	},
1446 {"c.ngt.d", "S,T",	0x4620003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I1	},
1447 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,		I4|I32	},
1448 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1      },
1449 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4|I32	},
1450 {"c.ngt.ps","S,T",	0x46c0003f, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1451 {"c.ngt.ps","M,S,T",	0x46c0003f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5|I33	},
1452 {"cabs.eq.d",  "M,S,T",	0x46200072, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1453 {"cabs.eq.ps", "M,S,T",	0x46c00072, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1454 {"cabs.eq.s",  "M,S,T",	0x46000072, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1455 {"cabs.f.d",   "M,S,T",	0x46200070, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1456 {"cabs.f.ps",  "M,S,T",	0x46c00070, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1457 {"cabs.f.s",   "M,S,T",	0x46000070, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1458 {"cabs.le.d",  "M,S,T",	0x4620007e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1459 {"cabs.le.ps", "M,S,T",	0x46c0007e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1460 {"cabs.le.s",  "M,S,T",	0x4600007e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1461 {"cabs.lt.d",  "M,S,T",	0x4620007c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1462 {"cabs.lt.ps", "M,S,T",	0x46c0007c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1463 {"cabs.lt.s",  "M,S,T",	0x4600007c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1464 {"cabs.nge.d", "M,S,T",	0x4620007d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1465 {"cabs.nge.ps","M,S,T",	0x46c0007d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1466 {"cabs.nge.s", "M,S,T",	0x4600007d, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1467 {"cabs.ngl.d", "M,S,T",	0x4620007b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1468 {"cabs.ngl.ps","M,S,T",	0x46c0007b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1469 {"cabs.ngl.s", "M,S,T",	0x4600007b, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1470 {"cabs.ngle.d","M,S,T",	0x46200079, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1471 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1472 {"cabs.ngle.s","M,S,T",	0x46000079, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1473 {"cabs.ngt.d", "M,S,T",	0x4620007f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1474 {"cabs.ngt.ps","M,S,T",	0x46c0007f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1475 {"cabs.ngt.s", "M,S,T",	0x4600007f, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1476 {"cabs.ole.d", "M,S,T",	0x46200076, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1477 {"cabs.ole.ps","M,S,T",	0x46c00076, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1478 {"cabs.ole.s", "M,S,T",	0x46000076, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1479 {"cabs.olt.d", "M,S,T",	0x46200074, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1480 {"cabs.olt.ps","M,S,T",	0x46c00074, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1481 {"cabs.olt.s", "M,S,T",	0x46000074, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1482 {"cabs.seq.d", "M,S,T",	0x4620007a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1483 {"cabs.seq.ps","M,S,T",	0x46c0007a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1484 {"cabs.seq.s", "M,S,T",	0x4600007a, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1485 {"cabs.sf.d",  "M,S,T",	0x46200078, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1486 {"cabs.sf.ps", "M,S,T",	0x46c00078, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1487 {"cabs.sf.s",  "M,S,T",	0x46000078, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1488 {"cabs.ueq.d", "M,S,T",	0x46200073, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1489 {"cabs.ueq.ps","M,S,T",	0x46c00073, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1490 {"cabs.ueq.s", "M,S,T",	0x46000073, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1491 {"cabs.ule.d", "M,S,T",	0x46200077, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1492 {"cabs.ule.ps","M,S,T",	0x46c00077, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1493 {"cabs.ule.s", "M,S,T",	0x46000077, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1494 {"cabs.ult.d", "M,S,T",	0x46200075, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1495 {"cabs.ult.ps","M,S,T",	0x46c00075, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1496 {"cabs.ult.s", "M,S,T",	0x46000075, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1497 {"cabs.un.d",  "M,S,T",	0x46200071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1498 {"cabs.un.ps", "M,S,T",	0x46c00071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		M3D	},
1499 {"cabs.un.s",  "M,S,T",	0x46000071, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_S,	0,		M3D	},
1500 /* CW4010 instructions which are aliases for the cache instruction.  */
1501 {"flushi",  "",		0xbc010000, 0xffffffff, 0,			0,		L1	},
1502 {"flushd",  "",		0xbc020000, 0xffffffff, 0, 			0,		L1	},
1503 {"flushid", "",		0xbc030000, 0xffffffff, 0, 			0,		L1	},
1504 {"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,		0,		L1	},
1505 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,           	0,		I3|I32|T3},
1506 {"cache",   "k,A(b)",	0,    (int) M_CACHE_AB, INSN_MACRO,		0,		I3|I32|T3},
1507 {"ceil.l.d", "D,S",	0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3|I33	},
1508 {"ceil.l.s", "D,S",	0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3|I33	},
1509 {"ceil.w.d", "D,S",	0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
1510 {"ceil.w.s", "D,S",	0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
1511 {"cfc0",    "t,G",	0x40400000, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		I1	},
1512 {"cfc1",    "t,G",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	0,		I1	},
1513 {"cfc1",    "t,S",	0x44400000, 0xffe007ff,	LCD|WR_t|RD_C1|FP_S,	0,		I1	},
1514 /* cfc2 is at the bottom of the table.  */
1515 /* cfc3 is at the bottom of the table.  */
1516 {"cftc1",   "d,E",	0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,		MT32	},
1517 {"cftc1",   "d,T",	0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,		MT32	},
1518 {"cftc2",   "d,E",	0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,	0,		MT32	},
1519 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 	0,		I32|N55 },
1520 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 	0,		I32|N55 },
1521 {"ctc0",    "t,G",	0x40c00000, 0xffe007ff,	COD|RD_t|WR_CC,		0,		I1	},
1522 {"ctc1",    "t,G",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	0,		I1	},
1523 {"ctc1",    "t,S",	0x44c00000, 0xffe007ff,	COD|RD_t|WR_CC|FP_S,	0,		I1	},
1524 /* ctc2 is at the bottom of the table.  */
1525 /* ctc3 is at the bottom of the table.  */
1526 {"cttc1",   "t,g",	0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,		MT32	},
1527 {"cttc1",   "t,S",	0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,		MT32	},
1528 {"cttc2",   "t,g",	0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,	0,		MT32	},
1529 {"cvt.d.l", "D,S",	0x46a00021, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I3|I33	},
1530 {"cvt.d.s", "D,S",	0x46000021, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
1531 {"cvt.d.w", "D,S",	0x46800021, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
1532 {"cvt.l.d", "D,S",	0x46200025, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I3|I33	},
1533 {"cvt.l.s", "D,S",	0x46000025, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I3|I33	},
1534 {"cvt.s.l", "D,S",	0x46a00020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I3|I33	},
1535 {"cvt.s.d", "D,S",	0x46200020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
1536 {"cvt.s.w", "D,S",	0x46800020, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
1537 {"cvt.s.pl","D,S",	0x46c00028, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I5|I33	},
1538 {"cvt.s.pu","D,S",	0x46c00020, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I5|I33	},
1539 {"cvt.w.d", "D,S",	0x46200024, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I1	},
1540 {"cvt.w.s", "D,S",	0x46000024, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
1541 {"cvt.ps.pw", "D,S",	0x46800026, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		M3D	},
1542 {"cvt.ps.s","D,V,T",	0x46000026, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S|FP_D, 0,		I5|I33	},
1543 {"cvt.pw.ps", "D,S",	0x46c00024, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		M3D	},
1544 {"dabs",    "d,v",	0,    (int) M_DABS,	INSN_MACRO,		0,		I3	},
1545 {"dadd",    "d,v,t",	0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3	},
1546 {"dadd",    "t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,		0,		I3	},
1547 {"daddi",   "t,r,j",	0x60000000, 0xfc000000, WR_t|RD_s,		0,		I3	},
1548 {"daddiu",  "t,r,j",	0x64000000, 0xfc000000, WR_t|RD_s,		0,		I3	},
1549 {"daddu",   "d,v,t",	0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3	},
1550 {"daddu",   "t,r,I",	0,    (int) M_DADDU_I,	INSN_MACRO,		0,		I3	},
1551 {"dbreak",  "",		0x7000003f, 0xffffffff,	0,			0,		N5	},
1552 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 	0,		I64|N55 },
1553 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 	0,		I64|N55 },
1554 /* dctr and dctw are used on the r5000.  */
1555 {"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,			0,		I3	},
1556 {"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,			0,		I3	},
1557 {"deret",   "",         0x4200001f, 0xffffffff, 0, 			0,		I32|G2	},
1558 {"dext",    "t,r,I,+I",	0,    (int) M_DEXT,	INSN_MACRO,		0,		I65	},
1559 {"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
1560 {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
1561 {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
1562 /* For ddiv, see the comments about div.  */
1563 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
1564 {"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,		0,		I3	},
1565 {"ddiv",    "d,v,I",	0,    (int) M_DDIV_3I,	INSN_MACRO,		0,		I3	},
1566 /* For ddivu, see the comments about div.  */
1567 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
1568 {"ddivu",   "d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,		0,		I3	},
1569 {"ddivu",   "d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,		0,		I3	},
1570 {"di",      "",		0x41606000, 0xffffffff,	WR_t|WR_C0,		0,		I33	},
1571 {"di",      "t",	0x41606000, 0xffe0ffff,	WR_t|WR_C0,		0,		I33	},
1572 {"dins",    "t,r,I,+I",	0,    (int) M_DINS,	INSN_MACRO,		0,		I65	},
1573 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
1574 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
1575 {"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,    		0,		I65	},
1576 /* The MIPS assembler treats the div opcode with two operands as
1577    though the first operand appeared twice (the first operand is both
1578    a source and a destination).  To get the div machine instruction,
1579    you must use an explicit destination of $0.  */
1580 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1      },
1581 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		I1      },
1582 {"div",     "d,v,t",	0,    (int) M_DIV_3,	INSN_MACRO,		0,		I1	},
1583 {"div",     "d,v,I",	0,    (int) M_DIV_3I,	INSN_MACRO,		0,		I1	},
1584 {"div.d",   "D,V,T",	0x46200003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
1585 {"div.s",   "D,V,T",	0x46000003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
1586 {"div.ps",  "D,V,T",	0x46c00003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1	},
1587 /* For divu, see the comments about div.  */
1588 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1      },
1589 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		I1      },
1590 {"divu",    "d,v,t",	0,    (int) M_DIVU_3,	INSN_MACRO,		0,		I1	},
1591 {"divu",    "d,v,I",	0,    (int) M_DIVU_3I,	INSN_MACRO,		0,		I1	},
1592 {"dla",     "t,A(b)",	0,    (int) M_DLA_AB,	INSN_MACRO,		0,		I3	},
1593 {"dlca",    "t,A(b)",	0,    (int) M_DLCA_AB,	INSN_MACRO,		0,		I3	},
1594 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,			0,		I3	}, /* addiu */
1595 {"dli",	    "t,i",	0x34000000, 0xffe00000, WR_t,			0,		I3	}, /* ori */
1596 {"dli",     "t,I",	0,    (int) M_DLI,	INSN_MACRO,		0,		I3	},
1597 {"dmacc",   "d,s,t",	0x00000029, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
1598 {"dmacchi", "d,s,t",	0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
1599 {"dmacchis", "d,s,t",	0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
1600 {"dmacchiu", "d,s,t",	0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
1601 {"dmacchius", "d,s,t",	0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
1602 {"dmaccs",  "d,s,t",	0x00000429, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
1603 {"dmaccu",  "d,s,t",	0x00000069, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
1604 {"dmaccus", "d,s,t",	0x00000469, 0xfc0007ff,	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
1605 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,		N411    },
1606 {"dmfc0",   "t,G",	0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,		0,		I3	},
1607 {"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 	0,		I64     },
1608 {"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 	0,		I64     },
1609 {"dmt",     "",		0x41600bc1, 0xffffffff, TRAP,			0,		MT32	},
1610 {"dmt",     "t",	0x41600bc1, 0xffe0ffff, TRAP|WR_t,		0,		MT32	},
1611 {"dmtc0",   "t,G",	0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,	0,		I3	},
1612 {"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,		I64     },
1613 {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,		I64     },
1614 {"dmfc1",   "t,S",	0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,	0,		I3	},
1615 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,		I3      },
1616 {"dmtc1",   "t,S",	0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,	0,		I3	},
1617 {"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,		I3      },
1618 /* dmfc2 is at the bottom of the table.  */
1619 /* dmtc2 is at the bottom of the table.  */
1620 /* dmfc3 is at the bottom of the table.  */
1621 /* dmtc3 is at the bottom of the table.  */
1622 {"dmul",    "d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,		0,		I3	},
1623 {"dmul",    "d,v,I",	0,    (int) M_DMUL_I,	INSN_MACRO,		0,		I3	},
1624 {"dmulo",   "d,v,t",	0,    (int) M_DMULO,	INSN_MACRO,		0,		I3	},
1625 {"dmulo",   "d,v,I",	0,    (int) M_DMULO_I,	INSN_MACRO,		0,		I3	},
1626 {"dmulou",  "d,v,t",	0,    (int) M_DMULOU,	INSN_MACRO,		0,		I3	},
1627 {"dmulou",  "d,v,I",	0,    (int) M_DMULOU_I,	INSN_MACRO,		0,		I3	},
1628 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3	},
1629 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3	},
1630 {"dneg",    "d,w",	0x0000002e, 0xffe007ff,	WR_d|RD_t,		0,		I3	}, /* dsub 0 */
1631 {"dnegu",   "d,w",	0x0000002f, 0xffe007ff,	WR_d|RD_t,		0,		I3	}, /* dsubu 0*/
1632 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
1633 {"drem",    "d,v,t",	3,    (int) M_DREM_3,	INSN_MACRO,		0,		I3	},
1634 {"drem",    "d,v,I",	3,    (int) M_DREM_3I,	INSN_MACRO,		0,		I3	},
1635 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
1636 {"dremu",   "d,v,t",	3,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3	},
1637 {"dremu",   "d,v,I",	3,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3	},
1638 {"dret",    "",		0x7000003e, 0xffffffff,	0,			0,		N5	},
1639 {"drol",    "d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		0,		I3	},
1640 {"drol",    "d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		0,		I3	},
1641 {"dror",    "d,v,t",	0,    (int) M_DROR,	INSN_MACRO,		0,		I3	},
1642 {"dror",    "d,v,I",	0,    (int) M_DROR_I,	INSN_MACRO,		0,		I3	},
1643 {"dror",    "d,w,<",	0x0020003a, 0xffe0003f,	WR_d|RD_t,		0,		N5|I65	},
1644 {"drorv",   "d,t,s",	0x00000056, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		N5|I65	},
1645 {"dror32",  "d,w,<",	0x0020003e, 0xffe0003f,	WR_d|RD_t,		0,		N5|I65	},
1646 {"drotl",   "d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		0,		I65	},
1647 {"drotl",   "d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		0,		I65	},
1648 {"drotr",   "d,v,t",	0,    (int) M_DROR,	INSN_MACRO,		0,		I65	},
1649 {"drotr",   "d,v,I",	0,    (int) M_DROR_I,	INSN_MACRO,		0,		I65	},
1650 {"drotrv",  "d,t,s",	0x00000056, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		I65	},
1651 {"drotr32", "d,w,<",	0x0020003e, 0xffe0003f,	WR_d|RD_t,		0,		I65	},
1652 {"dsbh",    "d,w",	0x7c0000a4, 0xffe007ff,	WR_d|RD_t,		0,		I65	},
1653 {"dshd",    "d,w",	0x7c000164, 0xffe007ff,	WR_d|RD_t,		0,		I65	},
1654 {"dsllv",   "d,t,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	},
1655 {"dsll32",  "d,w,<",	0x0000003c, 0xffe0003f, WR_d|RD_t,		0,		I3	},
1656 {"dsll",    "d,w,s",	0x00000014, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	}, /* dsllv */
1657 {"dsll",    "d,w,>",	0x0000003c, 0xffe0003f, WR_d|RD_t,		0,		I3	}, /* dsll32 */
1658 {"dsll",    "d,w,<",	0x00000038, 0xffe0003f,	WR_d|RD_t,		0,		I3	},
1659 {"dsrav",   "d,t,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	},
1660 {"dsra32",  "d,w,<",	0x0000003f, 0xffe0003f, WR_d|RD_t,		0,		I3	},
1661 {"dsra",    "d,w,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	}, /* dsrav */
1662 {"dsra",    "d,w,>",	0x0000003f, 0xffe0003f, WR_d|RD_t,		0,		I3	}, /* dsra32 */
1663 {"dsra",    "d,w,<",	0x0000003b, 0xffe0003f,	WR_d|RD_t,		0,		I3	},
1664 {"dsrlv",   "d,t,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	},
1665 {"dsrl32",  "d,w,<",	0x0000003e, 0xffe0003f, WR_d|RD_t,		0,		I3	},
1666 {"dsrl",    "d,w,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	}, /* dsrlv */
1667 {"dsrl",    "d,w,>",	0x0000003e, 0xffe0003f, WR_d|RD_t,		0,		I3	}, /* dsrl32 */
1668 {"dsrl",    "d,w,<",	0x0000003a, 0xffe0003f,	WR_d|RD_t,		0,		I3	},
1669 {"dsub",    "d,v,t",	0x0000002e, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I3	},
1670 {"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,		0,		I3	},
1671 {"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I3	},
1672 {"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,		0,		I3	},
1673 {"dvpe",    "",		0x41600001, 0xffffffff, TRAP,			0,		MT32	},
1674 {"dvpe",    "t",	0x41600001, 0xffe0ffff, TRAP|WR_t,		0,		MT32	},
1675 {"ei",      "",		0x41606020, 0xffffffff,	WR_t|WR_C0,		0,		I33	},
1676 {"ei",      "t",	0x41606020, 0xffe0ffff,	WR_t|WR_C0,		0,		I33	},
1677 {"emt",     "",		0x41600be1, 0xffffffff, TRAP,			0,		MT32	},
1678 {"emt",     "t",	0x41600be1, 0xffe0ffff, TRAP|WR_t,		0,		MT32	},
1679 {"eret",    "",         0x42000018, 0xffffffff, 0,      		0,		I3|I32	},
1680 {"evpe",    "",		0x41600021, 0xffffffff, TRAP,			0,		MT32	},
1681 {"evpe",    "t",	0x41600021, 0xffe0ffff, TRAP|WR_t,		0,		MT32	},
1682 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
1683 {"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3|I33	},
1684 {"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3|I33	},
1685 {"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
1686 {"floor.w.s", "D,S",	0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
1687 {"hibernate","",        0x42000023, 0xffffffff,	0, 			0,		V1	},
1688 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
1689 {"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	},
1690 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
1691    the same hazard barrier effect.  */
1692 {"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		0,		I32	},
1693 {"j",       "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	}, /* jr */
1694 /* SVR4 PIC code requires special handling for j, so it must be a
1695    macro.  */
1696 {"j",	    "a",	0,     (int) M_J_A,	INSN_MACRO,		0,		I1	},
1697 /* This form of j is used by the disassembler and internally by the
1698    assembler, but will never match user input (because the line above
1699    will match first).  */
1700 {"j",       "a",	0x08000000, 0xfc000000,	UBD,			0,		I1	},
1701 {"jalr",    "s",	0x0000f809, 0xfc1fffff,	UBD|RD_s|WR_d,		0,		I1	},
1702 {"jalr",    "d,s",	0x00000009, 0xfc1f07ff,	UBD|RD_s|WR_d,		0,		I1	},
1703 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
1704    with the same hazard barrier effect.  */
1705 {"jalr.hb", "s",	0x0000fc09, 0xfc1fffff,	UBD|RD_s|WR_d,		0,		I32	},
1706 {"jalr.hb", "d,s",	0x00000409, 0xfc1f07ff,	UBD|RD_s|WR_d,		0,		I32	},
1707 /* SVR4 PIC code requires special handling for jal, so it must be a
1708    macro.  */
1709 {"jal",     "d,s",	0,     (int) M_JAL_2,	INSN_MACRO,		0,		I1	},
1710 {"jal",     "s",	0,     (int) M_JAL_1,	INSN_MACRO,		0,		I1	},
1711 {"jal",     "a",	0,     (int) M_JAL_A,	INSN_MACRO,		0,		I1	},
1712 /* This form of jal is used by the disassembler and internally by the
1713    assembler, but will never match user input (because the line above
1714    will match first).  */
1715 {"jal",     "a",	0x0c000000, 0xfc000000,	UBD|WR_31,		0,		I1	},
1716 {"jalx",    "a",	0x74000000, 0xfc000000, UBD|WR_31,		0,		I16     },
1717 {"la",      "t,A(b)",	0,    (int) M_LA_AB,	INSN_MACRO,		0,		I1	},
1718 {"lb",      "t,o(b)",	0x80000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
1719 {"lb",      "t,A(b)",	0,    (int) M_LB_AB,	INSN_MACRO,		0,		I1	},
1720 {"lbu",     "t,o(b)",	0x90000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
1721 {"lbu",     "t,A(b)",	0,    (int) M_LBU_AB,	INSN_MACRO,		0,		I1	},
1722 {"lca",     "t,A(b)",	0,    (int) M_LCA_AB,	INSN_MACRO,		0,		I1	},
1723 {"ld",	    "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,		0,		I3	},
1724 {"ld",      "t,o(b)",	0,    (int) M_LD_OB,	INSN_MACRO,		0,		I1	},
1725 {"ld",      "t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO,		0,		I1	},
1726 {"ldc1",    "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
1727 {"ldc1",    "E,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
1728 {"ldc1",    "T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		0,		I2	},
1729 {"ldc1",    "E,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		0,		I2	},
1730 {"l.d",     "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	}, /* ldc1 */
1731 {"l.d",     "T,o(b)",	0,    (int) M_L_DOB,	INSN_MACRO,		0,		I1	},
1732 {"l.d",     "T,A(b)",	0,    (int) M_L_DAB,	INSN_MACRO,		0,		I1	},
1733 {"ldc2",    "E,o(b)",	0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,		0,		I2	},
1734 {"ldc2",    "E,A(b)",	0,    (int) M_LDC2_AB,	INSN_MACRO,		0,		I2	},
1735 {"ldc3",    "E,o(b)",	0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,		0,		I2	},
1736 {"ldc3",    "E,A(b)",	0,    (int) M_LDC3_AB,	INSN_MACRO,		0,		I2	},
1737 {"ldl",	    "t,o(b)",	0x68000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3	},
1738 {"ldl",	    "t,A(b)",	0,    (int) M_LDL_AB,	INSN_MACRO,		0,		I3	},
1739 {"ldr",	    "t,o(b)",	0x6c000000, 0xfc000000, LDD|WR_t|RD_b,		0,		I3	},
1740 {"ldr",     "t,A(b)",	0,    (int) M_LDR_AB,	INSN_MACRO,		0,		I3	},
1741 {"ldxc1",   "D,t(b)",	0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,		I4|I33	},
1742 {"lh",      "t,o(b)",	0x84000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
1743 {"lh",      "t,A(b)",	0,    (int) M_LH_AB,	INSN_MACRO,		0,		I1	},
1744 {"lhu",     "t,o(b)",	0x94000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
1745 {"lhu",     "t,A(b)",	0,    (int) M_LHU_AB,	INSN_MACRO,		0,		I1	},
1746 /* li is at the start of the table.  */
1747 {"li.d",    "t,F",	0,    (int) M_LI_D,	INSN_MACRO,		0,		I1	},
1748 {"li.d",    "T,L",	0,    (int) M_LI_DD,	INSN_MACRO,		0,		I1	},
1749 {"li.s",    "t,f",	0,    (int) M_LI_S,	INSN_MACRO,		0,		I1	},
1750 {"li.s",    "T,l",	0,    (int) M_LI_SS,	INSN_MACRO,		0,		I1	},
1751 {"ll",	    "t,o(b)",	0xc0000000, 0xfc000000, LDD|RD_b|WR_t,		0,		I2	},
1752 {"ll",	    "t,A(b)",	0,    (int) M_LL_AB,	INSN_MACRO,		0,		I2	},
1753 {"lld",	    "t,o(b)",	0xd0000000, 0xfc000000, LDD|RD_b|WR_t,		0,		I3	},
1754 {"lld",     "t,A(b)",	0,    (int) M_LLD_AB,	INSN_MACRO,		0,		I3	},
1755 {"lui",     "t,u",	0x3c000000, 0xffe00000,	WR_t,			0,		I1	},
1756 {"luxc1",   "D,t(b)",	0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,		I5|I33|N55},
1757 {"lw",      "t,o(b)",	0x8c000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
1758 {"lw",      "t,A(b)",	0,    (int) M_LW_AB,	INSN_MACRO,		0,		I1	},
1759 {"lwc0",    "E,o(b)",	0xc0000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1	},
1760 {"lwc0",    "E,A(b)",	0,    (int) M_LWC0_AB,	INSN_MACRO,		0,		I1	},
1761 {"lwc1",    "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1	},
1762 {"lwc1",    "E,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1	},
1763 {"lwc1",    "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		0,		I1	},
1764 {"lwc1",    "E,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		0,		I1	},
1765 {"l.s",     "T,o(b)",	0xc4000000, 0xfc000000,	CLD|RD_b|WR_T|FP_S,	0,		I1	}, /* lwc1 */
1766 {"l.s",     "T,A(b)",	0,    (int) M_LWC1_AB,	INSN_MACRO,		0,		I1	},
1767 {"lwc2",    "E,o(b)",	0xc8000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1	},
1768 {"lwc2",    "E,A(b)",	0,    (int) M_LWC2_AB,	INSN_MACRO,		0,		I1	},
1769 {"lwc3",    "E,o(b)",	0xcc000000, 0xfc000000,	CLD|RD_b|WR_CC,		0,		I1	},
1770 {"lwc3",    "E,A(b)",	0,    (int) M_LWC3_AB,	INSN_MACRO,		0,		I1	},
1771 {"lwl",     "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
1772 {"lwl",     "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I1	},
1773 {"lcache",  "t,o(b)",	0x88000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I2	}, /* same */
1774 {"lcache",  "t,A(b)",	0,    (int) M_LWL_AB,	INSN_MACRO,		0,		I2	}, /* as lwl */
1775 {"lwr",     "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I1	},
1776 {"lwr",     "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I1	},
1777 {"flush",   "t,o(b)",	0x98000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I2	}, /* same */
1778 {"flush",   "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,		I2	}, /* as lwr */
1779 {"fork",    "d,s,t",	0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,	0,		MT32	},
1780 {"lwu",     "t,o(b)",	0x9c000000, 0xfc000000,	LDD|RD_b|WR_t,		0,		I3	},
1781 {"lwu",     "t,A(b)",	0,    (int) M_LWU_AB,	INSN_MACRO,		0,		I3	},
1782 {"lwxc1",   "D,t(b)",	0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,		I4|I33	},
1783 {"lwxs",    "d,t(b)",	0x70000088, 0xfc0007ff,	LDD|RD_b|RD_t|WR_d,	0,		SMT	},
1784 {"macc",    "d,s,t",	0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
1785 {"macc",    "d,s,t",	0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,	0,		N5      },
1786 {"maccs",   "d,s,t",	0x00000428, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
1787 {"macchi",  "d,s,t",	0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
1788 {"macchi",  "d,s,t",	0x00000358, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5      },
1789 {"macchis", "d,s,t",	0x00000628, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
1790 {"macchiu", "d,s,t",	0x00000268, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
1791 {"macchiu", "d,s,t",	0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,	0,		N5      },
1792 {"macchius","d,s,t",	0x00000668, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
1793 {"maccu",   "d,s,t",	0x00000068, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
1794 {"maccu",   "d,s,t",	0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d,	0,		N5      },
1795 {"maccus",  "d,s,t",	0x00000468, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d, 0,		N412    },
1796 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		P3      },
1797 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		P3      },
1798 {"madd.d",  "D,R,S,T",	0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,		I4|I33	},
1799 {"madd.s",  "D,R,S,T",	0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,		I4|I33	},
1800 {"madd.ps", "D,R,S,T",	0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,		I5|I33	},
1801 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1	},
1802 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55	},
1803 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
1804 {"madd",    "7,s,t",	0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33	},
1805 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
1806 {"maddp",   "s,t",      0x70000441, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	     0,		SMT	},
1807 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1	},
1808 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55	},
1809 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
1810 {"maddu",   "7,s,t",	0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33	},
1811 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
1812 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,	0,		N411    },
1813 {"max.ob",  "X,Y,Q",	0x78000007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
1814 {"max.ob",  "D,S,T",	0x4ac00007, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
1815 {"max.ob",  "D,S,T[e]",	0x48000007, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
1816 {"max.ob",  "D,S,k",	0x4bc00007, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
1817 {"max.qh",  "X,Y,Q",	0x78200007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
1818 {"mfpc",    "t,P",	0x4000c801, 0xffe0ffc1,	LCD|WR_t|RD_C0,		0,		M1|N5	},
1819 {"mfps",    "t,P",	0x4000c800, 0xffe0ffc1,	LCD|WR_t|RD_C0,		0,		M1|N5	},
1820 {"mftacx",  "d",	0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,		0,		MT32	},
1821 {"mftacx",  "d,*",	0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,		0,		MT32	},
1822 {"mftc0",   "d,+t",	0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,	0,		MT32	},
1823 {"mftc0",   "d,+T",	0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,	0,		MT32	},
1824 {"mftc0",   "d,E,H",	0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,	0,		MT32	},
1825 {"mftc1",   "d,T",	0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,		MT32	},
1826 {"mftc1",   "d,E",	0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,		MT32	},
1827 {"mftc2",   "d,E",	0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,	0,		MT32	},
1828 {"mftdsp",  "d",	0x41100021, 0xffff07ff, TRAP|WR_d,		0,		MT32	},
1829 {"mftgpr",  "d,t",	0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,		0,		MT32	},
1830 {"mfthc1",  "d,T",	0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,		MT32	},
1831 {"mfthc1",  "d,E",	0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,		MT32	},
1832 {"mfthc2",  "d,E",	0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,	0,		MT32	},
1833 {"mfthi",   "d",	0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,		0,		MT32	},
1834 {"mfthi",   "d,*",	0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,		0,		MT32	},
1835 {"mftlo",   "d",	0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,		0,		MT32	},
1836 {"mftlo",   "d,*",	0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,		0,		MT32	},
1837 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,		0,		MT32	},
1838 {"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		I1	},
1839 {"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	0,		I32     },
1840 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	0,		I32     },
1841 {"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	0,		I1	},
1842 {"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	0,		I1	},
1843 {"mfhc1",   "t,S",	0x44600000, 0xffe007ff,	LCD|WR_t|RD_S|FP_D,	0,		I33	},
1844 {"mfhc1",   "t,G",	0x44600000, 0xffe007ff,	LCD|WR_t|RD_S|FP_D,	0,		I33	},
1845 /* mfc2 is at the bottom of the table.  */
1846 /* mfhc2 is at the bottom of the table.  */
1847 /* mfc3 is at the bottom of the table.  */
1848 {"mfdr",    "t,G",	0x7000003d, 0xffe007ff,	LCD|WR_t|RD_C0,		0,		N5      },
1849 {"mfhi",    "d",	0x00000010, 0xffff07ff,	WR_d|RD_HI,		0,		I1	},
1850 {"mfhi",    "d,9",	0x00000010, 0xff9f07ff, WR_d|RD_HI,		0,		D32	},
1851 {"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,		0,		I1	},
1852 {"mflo",    "d,9",	0x00000012, 0xff9f07ff, WR_d|RD_LO,		0,		D32	},
1853 {"mflhxu",  "d",	0x00000052, 0xffff07ff,	WR_d|MOD_HILO,		0,		SMT	},
1854 {"min.ob",  "X,Y,Q",	0x78000006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
1855 {"min.ob",  "D,S,T",	0x4ac00006, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
1856 {"min.ob",  "D,S,T[e]",	0x48000006, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
1857 {"min.ob",  "D,S,k",	0x4bc00006, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
1858 {"min.qh",  "X,Y,Q",	0x78200006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
1859 {"mov.d",   "D,S",	0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
1860 {"mov.s",   "D,S",	0x46000006, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
1861 {"mov.ps",  "D,S",	0x46c00006, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I5|I33	},
1862 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,		I4|I32  },
1863 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		I4|I32	},
1864 {"movf.l",  "D,S,N",	0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		MX|SB1	},
1865 {"movf.l",  "X,Y,N",	0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		MX|SB1	},
1866 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4|I32	},
1867 {"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5|I33	},
1868 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4|I32	},
1869 {"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,		0,		L1	},
1870 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4|I32	},
1871 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
1872 {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
1873 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,		I4|I32	},
1874 {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I5|I33	},
1875 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,		I4|I32	},
1876 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		I4|I32	},
1877 {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		MX|SB1	},
1878 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,		MX|SB1	},
1879 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4|I32	},
1880 {"movt.ps", "D,S,N",	0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5|I33	},
1881 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4|I32	},
1882 {"ffs",     "d,v",	0x0000000a, 0xfc1f07ff,	WR_d|RD_s,		0,		L1	},
1883 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4|I32	},
1884 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
1885 {"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
1886 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,		I4|I32	},
1887 {"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I5|I33	},
1888 {"msac",    "d,s,t",	0x000001d8, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1889 {"msacu",   "d,s,t",	0x000001d9, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1890 {"msachi",  "d,s,t",	0x000003d8, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1891 {"msachiu", "d,s,t",	0x000003d9, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1892 /* move is at the top of the table.  */
1893 {"msgn.qh", "X,Y,Q",	0x78200000, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
1894 {"msub.d",  "D,R,S,T",	0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4|I33	},
1895 {"msub.s",  "D,R,S,T",	0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4|I33	},
1896 {"msub.ps", "D,R,S,T",	0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5|I33	},
1897 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1    	},
1898 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55 },
1899 {"msub",    "7,s,t",	0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33	},
1900 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1	},
1901 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55	},
1902 {"msubu",   "7,s,t",	0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33	},
1903 {"mtpc",    "t,P",	0x4080c801, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
1904 {"mtps",    "t,P",	0x4080c800, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
1905 {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	0,		I1	},
1906 {"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,		I32     },
1907 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,		I32     },
1908 {"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	0,		I1	},
1909 {"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	0,		I1	},
1910 {"mthc1",   "t,S",	0x44e00000, 0xffe007ff,	COD|RD_t|WR_S|FP_D,	0,		I33	},
1911 {"mthc1",   "t,G",	0x44e00000, 0xffe007ff,	COD|RD_t|WR_S|FP_D,	0,		I33	},
1912 /* mtc2 is at the bottom of the table.  */
1913 /* mthc2 is at the bottom of the table.  */
1914 /* mtc3 is at the bottom of the table.  */
1915 {"mtdr",    "t,G",	0x7080003d, 0xffe007ff,	COD|RD_t|WR_C0,		0,		N5	},
1916 {"mthi",    "s",	0x00000011, 0xfc1fffff,	RD_s|WR_HI,		0,		I1	},
1917 {"mthi",    "s,7",	0x00000011, 0xfc1fe7ff, RD_s|WR_HI,		0,		D32	},
1918 {"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,		0,		I1	},
1919 {"mtlo",    "s,7",	0x00000013, 0xfc1fe7ff, RD_s|WR_LO,		0,		D32	},
1920 {"mtlhx",   "s",	0x00000053, 0xfc1fffff,	RD_s|MOD_HILO,		0,		SMT	},
1921 {"mttc0",   "t,G",	0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,		MT32	},
1922 {"mttc0",   "t,+D",	0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,		MT32	},
1923 {"mttc0",   "t,G,H",	0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,		MT32	},
1924 {"mttc1",   "t,S",	0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,		MT32	},
1925 {"mttc1",   "t,G",	0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,		MT32	},
1926 {"mttc2",   "t,g",	0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,		MT32	},
1927 {"mttacx",  "t",	0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,		0,		MT32	},
1928 {"mttacx",  "t,&",	0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,		0,		MT32	},
1929 {"mttdsp",  "t",	0x41808021, 0xffe0ffff, TRAP|RD_t,		0,		MT32	},
1930 {"mttgpr",  "t,d",	0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,		0,		MT32	},
1931 {"mtthc1",  "t,S",	0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,		MT32	},
1932 {"mtthc1",  "t,G",	0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,		MT32	},
1933 {"mtthc2",  "t,g",	0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,		MT32	},
1934 {"mtthi",   "t",	0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,		0,		MT32	},
1935 {"mtthi",   "t,&",	0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,		0,		MT32	},
1936 {"mttlo",   "t",	0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,		0,		MT32	},
1937 {"mttlo",   "t,&",	0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,		0,		MT32	},
1938 {"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,		0,		MT32	},
1939 {"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
1940 {"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
1941 {"mul.ob",  "X,Y,Q",	0x78000030, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
1942 {"mul.ob",  "D,S,T",	0x4ac00030, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
1943 {"mul.ob",  "D,S,T[e]",	0x48000030, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
1944 {"mul.ob",  "D,S,k",	0x4bc00030, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
1945 {"mul.ps",  "D,V,T",	0x46c00002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5|I33	},
1946 {"mul.qh",  "X,Y,Q",	0x78200030, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
1947 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,		I32|P3|N55},
1948 {"mul",     "d,s,t",	0x00000058, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N54	},
1949 {"mul",     "d,v,t",	0,    (int) M_MUL,	INSN_MACRO,		0,		I1	},
1950 {"mul",     "d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,		0,		I1	},
1951 {"mula.ob", "Y,Q",	0x78000033, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
1952 {"mula.ob", "S,T",	0x4ac00033, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1953 {"mula.ob", "S,T[e]",	0x48000033, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1954 {"mula.ob", "S,k",	0x4bc00033, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1955 {"mula.qh", "Y,Q",	0x78200033, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
1956 {"mulhi",   "d,s,t",	0x00000258, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1957 {"mulhiu",  "d,s,t",	0x00000259, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1958 {"mull.ob", "Y,Q",	0x78000433, 0xfc2007ff,	RD_S|RD_T|FP_D, 	WR_MACC,	MX|SB1	},
1959 {"mull.ob", "S,T",	0x4ac00433, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1960 {"mull.ob", "S,T[e]",	0x48000433, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1961 {"mull.ob", "S,k",	0x4bc00433, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1962 {"mull.qh", "Y,Q",	0x78200433, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
1963 {"mulo",    "d,v,t",	0,    (int) M_MULO,	INSN_MACRO,		0,		I1	},
1964 {"mulo",    "d,v,I",	0,    (int) M_MULO_I,	INSN_MACRO,		0,		I1	},
1965 {"mulou",   "d,v,t",	0,    (int) M_MULOU,	INSN_MACRO,		0,		I1	},
1966 {"mulou",   "d,v,I",	0,    (int) M_MULOU_I,	INSN_MACRO,		0,		I1	},
1967 {"mulr.ps", "D,S,T",	0x46c0001a, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		M3D	},
1968 {"muls",    "d,s,t",	0x000000d8, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1969 {"mulsu",   "d,s,t",	0x000000d9, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1970 {"mulshi",  "d,s,t",	0x000002d8, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1971 {"mulshiu", "d,s,t",	0x000002d9, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1972 {"muls.ob", "Y,Q",	0x78000032, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
1973 {"muls.ob", "S,T",	0x4ac00032, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1974 {"muls.ob", "S,T[e]",	0x48000032, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1975 {"muls.ob", "S,k",	0x4bc00032, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1976 {"muls.qh", "Y,Q",	0x78200032, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
1977 {"mulsl.ob", "Y,Q",	0x78000432, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
1978 {"mulsl.ob", "S,T",	0x4ac00432, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1979 {"mulsl.ob", "S,T[e]",	0x48000432, 0xfe2007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1980 {"mulsl.ob", "S,k",	0x4bc00432, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
1981 {"mulsl.qh", "Y,Q",	0x78200432, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
1982 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1	},
1983 {"mult",    "7,s,t",	0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33	},
1984 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
1985 {"multp",   "s,t",	0x00000459, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	0,		SMT	},
1986 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1	},
1987 {"multu",   "7,s,t",	0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33	},
1988 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
1989 {"mulu",    "d,s,t",	0x00000059, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
1990 {"neg",     "d,w",	0x00000022, 0xffe007ff,	WR_d|RD_t,		0,		I1	}, /* sub 0 */
1991 {"negu",    "d,w",	0x00000023, 0xffe007ff,	WR_d|RD_t,		0,		I1	}, /* subu 0 */
1992 {"neg.d",   "D,V",	0x46200007, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
1993 {"neg.s",   "D,V",	0x46000007, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
1994 {"neg.ps",  "D,V",	0x46c00007, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I5|I33	},
1995 {"nmadd.d", "D,R,S,T",	0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4|I33	},
1996 {"nmadd.s", "D,R,S,T",	0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4|I33	},
1997 {"nmadd.ps","D,R,S,T",	0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5|I33	},
1998 {"nmsub.d", "D,R,S,T",	0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4|I33	},
1999 {"nmsub.s", "D,R,S,T",	0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I4|I33	},
2000 {"nmsub.ps","D,R,S,T",	0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I5|I33	},
2001 /* nop is at the start of the table.  */
2002 {"nor",     "d,v,t",	0x00000027, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
2003 {"nor",     "t,r,I",	0,    (int) M_NOR_I,	INSN_MACRO,		0,		I1	},
2004 {"nor.ob",  "X,Y,Q",	0x7800000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2005 {"nor.ob",  "D,S,T",	0x4ac0000f, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2006 {"nor.ob",  "D,S,T[e]",	0x4800000f, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
2007 {"nor.ob",  "D,S,k",	0x4bc0000f, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2008 {"nor.qh",  "X,Y,Q",	0x7820000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2009 {"not",     "d,v",	0x00000027, 0xfc1f07ff,	WR_d|RD_s|RD_t,		0,		I1	},/*nor d,s,0*/
2010 {"or",      "d,v,t",	0x00000025, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
2011 {"or",      "t,r,I",	0,    (int) M_OR_I,	INSN_MACRO,		0,		I1	},
2012 {"or.ob",   "X,Y,Q",	0x7800000e, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2013 {"or.ob",   "D,S,T",	0x4ac0000e, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2014 {"or.ob",   "D,S,T[e]",	0x4800000e, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
2015 {"or.ob",   "D,S,k",	0x4bc0000e, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2016 {"or.qh",   "X,Y,Q",	0x7820000e, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2017 {"ori",     "t,r,i",	0x34000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
2018 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1	},
2019 {"pabsdiffc.ob", "Y,Q",	0x78000035, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	SB1	},
2020 {"pavg.ob", "X,Y,Q",	0x78000008, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1	},
2021 {"pickf.ob", "X,Y,Q",	0x78000002, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2022 {"pickf.ob", "D,S,T",	0x4ac00002, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2023 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
2024 {"pickf.ob", "D,S,k",	0x4bc00002, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2025 {"pickf.qh", "X,Y,Q",	0x78200002, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2026 {"pickt.ob", "X,Y,Q",	0x78000003, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2027 {"pickt.ob", "D,S,T",	0x4ac00003, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2028 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
2029 {"pickt.ob", "D,S,k",	0x4bc00003, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2030 {"pickt.qh", "X,Y,Q",	0x78200003, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2031 {"pll.ps",  "D,V,T",	0x46c0002c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5|I33	},
2032 {"plu.ps",  "D,V,T",	0x46c0002d, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5|I33	},
2033   /* pref and prefx are at the start of the table.  */
2034 {"pul.ps",  "D,V,T",	0x46c0002e, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5|I33	},
2035 {"puu.ps",  "D,V,T",	0x46c0002f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5|I33	},
2036 {"pperm",   "s,t",	0x70000481, 0xfc00ffff,	MOD_HILO|RD_s|RD_t,	0,		SMT	},
2037 {"rach.ob", "X",	0x7a00003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX|SB1	},
2038 {"rach.ob", "D",	0x4a00003f, 0xfffff83f,	WR_D,			0,		N54	},
2039 {"rach.qh", "X",	0x7a20003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX	},
2040 {"racl.ob", "X",	0x7800003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX|SB1	},
2041 {"racl.ob", "D",	0x4800003f, 0xfffff83f,	WR_D,			0,		N54	},
2042 {"racl.qh", "X",	0x7820003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX	},
2043 {"racm.ob", "X",	0x7900003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX|SB1	},
2044 {"racm.ob", "D",	0x4900003f, 0xfffff83f,	WR_D,			0,		N54	},
2045 {"racm.qh", "X",	0x7920003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	MX	},
2046 {"recip.d", "D,S",	0x46200015, 0xffff003f, WR_D|RD_S|FP_D,		0,		I4|I33	},
2047 {"recip.ps","D,S",	0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,		0,		SB1	},
2048 {"recip.s", "D,S",	0x46000015, 0xffff003f, WR_D|RD_S|FP_S,		0,		I4|I33	},
2049 {"recip1.d",  "D,S",	0x4620001d, 0xffff003f,	WR_D|RD_S|FP_D,		0,		M3D	},
2050 {"recip1.ps", "D,S",	0x46c0001d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		M3D	},
2051 {"recip1.s",  "D,S",	0x4600001d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		M3D	},
2052 {"recip2.d",  "D,S,T",	0x4620001c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		M3D	},
2053 {"recip2.ps", "D,S,T",	0x46c0001c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		M3D	},
2054 {"recip2.s",  "D,S,T",	0x4600001c, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		M3D	},
2055 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1	},
2056 {"rem",     "d,v,t",	0,    (int) M_REM_3,	INSN_MACRO,		0,		I1	},
2057 {"rem",     "d,v,I",	0,    (int) M_REM_3I,	INSN_MACRO,		0,		I1	},
2058 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1	},
2059 {"remu",    "d,v,t",	0,    (int) M_REMU_3,	INSN_MACRO,		0,		I1	},
2060 {"remu",    "d,v,I",	0,    (int) M_REMU_3I,	INSN_MACRO,		0,		I1	},
2061 {"rdhwr",   "t,K",	0x7c00003b, 0xffe007ff, WR_t,			0,		I33	},
2062 {"rdpgpr",  "d,w",	0x41400000, 0xffe007ff, WR_d,			0,		I33	},
2063 {"rfe",     "",		0x42000010, 0xffffffff,	0,			0,		I1|T3	},
2064 {"rnas.qh", "X,Q",	0x78200025, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
2065 {"rnau.ob", "X,Q",	0x78000021, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX|SB1	},
2066 {"rnau.qh", "X,Q",	0x78200021, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
2067 {"rnes.qh", "X,Q",	0x78200026, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
2068 {"rneu.ob", "X,Q",	0x78000022, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX|SB1	},
2069 {"rneu.qh", "X,Q",	0x78200022, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
2070 {"rol",     "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,		0,		I1	},
2071 {"rol",     "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		0,		I1	},
2072 {"ror",     "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		0,		I1	},
2073 {"ror",     "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		0,		I1	},
2074 {"ror",	    "d,w,<",	0x00200002, 0xffe0003f,	WR_d|RD_t,		0,		N5|I33|SMT },
2075 {"rorv",    "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		N5|I33|SMT },
2076 {"rotl",    "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,		0,		I33|SMT	},
2077 {"rotl",    "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		0,		I33|SMT	},
2078 {"rotr",    "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		0,		I33|SMT	},
2079 {"rotr",    "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		0,		I33|SMT	},
2080 {"rotrv",   "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		0,		I33|SMT	},
2081 {"round.l.d", "D,S",	0x46200008, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3|I33	},
2082 {"round.l.s", "D,S",	0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I3|I33	},
2083 {"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
2084 {"round.w.s", "D,S",	0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
2085 {"rsqrt.d", "D,S",	0x46200016, 0xffff003f, WR_D|RD_S|FP_D,		0,		I4|I33	},
2086 {"rsqrt.ps","D,S",	0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,		0,		SB1	},
2087 {"rsqrt.s", "D,S",	0x46000016, 0xffff003f, WR_D|RD_S|FP_S,		0,		I4|I33	},
2088 {"rsqrt1.d",  "D,S",	0x4620001e, 0xffff003f,	WR_D|RD_S|FP_D,		0,		M3D	},
2089 {"rsqrt1.ps", "D,S",	0x46c0001e, 0xffff003f,	WR_D|RD_S|FP_S,		0,		M3D	},
2090 {"rsqrt1.s",  "D,S",	0x4600001e, 0xffff003f,	WR_D|RD_S|FP_S,		0,		M3D	},
2091 {"rsqrt2.d",  "D,S,T",	0x4620001f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		M3D	},
2092 {"rsqrt2.ps", "D,S,T",	0x46c0001f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		M3D	},
2093 {"rsqrt2.s",  "D,S,T",	0x4600001f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		M3D	},
2094 {"rzs.qh",  "X,Q",	0x78200024, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
2095 {"rzu.ob",  "X,Q",	0x78000020, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX|SB1	},
2096 {"rzu.ob",  "D,k",	0x4bc00020, 0xffe0f83f,	WR_D|RD_S|RD_T,		0,		N54	},
2097 {"rzu.qh",  "X,Q",	0x78200020, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
2098 {"sb",      "t,o(b)",	0xa0000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
2099 {"sb",      "t,A(b)",	0,    (int) M_SB_AB,	INSN_MACRO,		0,		I1	},
2100 {"sc",	    "t,o(b)",	0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,	0,		I2	},
2101 {"sc",	    "t,A(b)",	0,    (int) M_SC_AB,	INSN_MACRO,		0,		I2	},
2102 {"scd",	    "t,o(b)",	0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,	0,		I3	},
2103 {"scd",	    "t,A(b)",	0,    (int) M_SCD_AB,	INSN_MACRO,		0,		I3	},
2104 {"sd",	    "t,o(b)",	0xfc000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3	},
2105 {"sd",      "t,o(b)",	0,    (int) M_SD_OB,	INSN_MACRO,		0,		I1	},
2106 {"sd",      "t,A(b)",	0,    (int) M_SD_AB,	INSN_MACRO,		0,		I1	},
2107 {"sdbbp",   "",		0x0000000e, 0xffffffff,	TRAP,           	0,		G2	},
2108 {"sdbbp",   "c",	0x0000000e, 0xfc00ffff,	TRAP,			0,		G2	},
2109 {"sdbbp",   "c,q",	0x0000000e, 0xfc00003f,	TRAP,			0,		G2	},
2110 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,           	0,		I32     },
2111 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,           	0,		I32     },
2112 {"sdc1",    "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
2113 {"sdc1",    "E,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
2114 {"sdc1",    "T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		0,		I2	},
2115 {"sdc1",    "E,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		0,		I2	},
2116 {"sdc2",    "E,o(b)",	0xf8000000, 0xfc000000, SM|RD_C2|RD_b,		0,		I2	},
2117 {"sdc2",    "E,A(b)",	0,    (int) M_SDC2_AB,	INSN_MACRO,		0,		I2	},
2118 {"sdc3",    "E,o(b)",	0xfc000000, 0xfc000000, SM|RD_C3|RD_b,		0,		I2	},
2119 {"sdc3",    "E,A(b)",	0,    (int) M_SDC3_AB,	INSN_MACRO,		0,		I2	},
2120 {"s.d",     "T,o(b)",	0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,	0,		I2	},
2121 {"s.d",     "T,o(b)",	0,    (int) M_S_DOB,	INSN_MACRO,		0,		I1	},
2122 {"s.d",     "T,A(b)",	0,    (int) M_S_DAB,	INSN_MACRO,		0,		I1	},
2123 {"sdl",     "t,o(b)",	0xb0000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3	},
2124 {"sdl",     "t,A(b)",	0,    (int) M_SDL_AB,	INSN_MACRO,		0,		I3	},
2125 {"sdr",     "t,o(b)",	0xb4000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I3	},
2126 {"sdr",     "t,A(b)",	0,    (int) M_SDR_AB,	INSN_MACRO,		0,		I3	},
2127 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,	0,		I4|I33	},
2128 {"seb",     "d,w",	0x7c000420, 0xffe007ff,	WR_d|RD_t,		0,		I33	},
2129 {"seh",     "d,w",	0x7c000620, 0xffe007ff,	WR_d|RD_t,		0,		I33	},
2130 {"selsl",   "d,v,t",	0x00000005, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		L1	},
2131 {"selsr",   "d,v,t",	0x00000001, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		L1	},
2132 {"seq",     "d,v,t",	0,    (int) M_SEQ,	INSN_MACRO,		0,		I1	},
2133 {"seq",     "d,v,I",	0,    (int) M_SEQ_I,	INSN_MACRO,		0,		I1	},
2134 {"sge",     "d,v,t",	0,    (int) M_SGE,	INSN_MACRO,		0,		I1	},
2135 {"sge",     "d,v,I",	0,    (int) M_SGE_I,	INSN_MACRO,		0,		I1	},
2136 {"sgeu",    "d,v,t",	0,    (int) M_SGEU,	INSN_MACRO,		0,		I1	},
2137 {"sgeu",    "d,v,I",	0,    (int) M_SGEU_I,	INSN_MACRO,		0,		I1	},
2138 {"sgt",     "d,v,t",	0,    (int) M_SGT,	INSN_MACRO,		0,		I1	},
2139 {"sgt",     "d,v,I",	0,    (int) M_SGT_I,	INSN_MACRO,		0,		I1	},
2140 {"sgtu",    "d,v,t",	0,    (int) M_SGTU,	INSN_MACRO,		0,		I1	},
2141 {"sgtu",    "d,v,I",	0,    (int) M_SGTU_I,	INSN_MACRO,		0,		I1	},
2142 {"sh",      "t,o(b)",	0xa4000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
2143 {"sh",      "t,A(b)",	0,    (int) M_SH_AB,	INSN_MACRO,		0,		I1	},
2144 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2145 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2146 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54	},
2147 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2148 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2149 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54	},
2150 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2151 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2152 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54	},
2153 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2154 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54	},
2155 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2156 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2157 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2158 {"sle",     "d,v,t",	0,    (int) M_SLE,	INSN_MACRO,		0,		I1	},
2159 {"sle",     "d,v,I",	0,    (int) M_SLE_I,	INSN_MACRO,		0,		I1	},
2160 {"sleu",    "d,v,t",	0,    (int) M_SLEU,	INSN_MACRO,		0,		I1	},
2161 {"sleu",    "d,v,I",	0,    (int) M_SLEU_I,	INSN_MACRO,		0,		I1	},
2162 {"sllv",    "d,t,s",	0x00000004, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	},
2163 {"sll",     "d,w,s",	0x00000004, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	}, /* sllv */
2164 {"sll",     "d,w,<",	0x00000000, 0xffe0003f,	WR_d|RD_t,		0,		I1	},
2165 {"sll.ob",  "X,Y,Q",	0x78000010, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2166 {"sll.ob",  "D,S,T[e]",	0x48000010, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
2167 {"sll.ob",  "D,S,k",	0x4bc00010, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2168 {"sll.qh",  "X,Y,Q",	0x78200010, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2169 {"slt",     "d,v,t",	0x0000002a, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
2170 {"slt",     "d,v,I",	0,    (int) M_SLT_I,	INSN_MACRO,		0,		I1	},
2171 {"slti",    "t,r,j",	0x28000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
2172 {"sltiu",   "t,r,j",	0x2c000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
2173 {"sltu",    "d,v,t",	0x0000002b, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
2174 {"sltu",    "d,v,I",	0,    (int) M_SLTU_I,	INSN_MACRO,		0,		I1	},
2175 {"sne",     "d,v,t",	0,    (int) M_SNE,	INSN_MACRO,		0,		I1	},
2176 {"sne",     "d,v,I",	0,    (int) M_SNE_I,	INSN_MACRO,		0,		I1	},
2177 {"sqrt.d",  "D,S",	0x46200004, 0xffff003f, WR_D|RD_S|FP_D,		0,		I2	},
2178 {"sqrt.s",  "D,S",	0x46000004, 0xffff003f, WR_D|RD_S|FP_S,		0,		I2	},
2179 {"sqrt.ps", "D,S",	0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,		0,		SB1	},
2180 {"srav",    "d,t,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	},
2181 {"sra",     "d,w,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	}, /* srav */
2182 {"sra",     "d,w,<",	0x00000003, 0xffe0003f,	WR_d|RD_t,		0,		I1	},
2183 {"sra.qh",  "X,Y,Q",	0x78200013, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2184 {"srlv",    "d,t,s",	0x00000006, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	},
2185 {"srl",     "d,w,s",	0x00000006, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	}, /* srlv */
2186 {"srl",     "d,w,<",	0x00000002, 0xffe0003f,	WR_d|RD_t,		0,		I1	},
2187 {"srl.ob",  "X,Y,Q",	0x78000012, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2188 {"srl.ob",  "D,S,T[e]",	0x48000012, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
2189 {"srl.ob",  "D,S,k",	0x4bc00012, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2190 {"srl.qh",  "X,Y,Q",	0x78200012, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2191 /* ssnop is at the start of the table.  */
2192 {"standby", "",         0x42000021, 0xffffffff,	0,			0,		V1	},
2193 {"sub",     "d,v,t",	0x00000022, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
2194 {"sub",     "d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,		0,		I1	},
2195 {"sub.d",   "D,V,T",	0x46200001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
2196 {"sub.s",   "D,V,T",	0x46000001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
2197 {"sub.ob",  "X,Y,Q",	0x7800000a, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2198 {"sub.ob",  "D,S,T",	0x4ac0000a, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2199 {"sub.ob",  "D,S,T[e]",	0x4800000a, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
2200 {"sub.ob",  "D,S,k",	0x4bc0000a, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2201 {"sub.ps",  "D,V,T",	0x46c00001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5|I33	},
2202 {"sub.qh",  "X,Y,Q",	0x7820000a, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2203 {"suba.ob", "Y,Q",	0x78000036, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
2204 {"suba.qh", "Y,Q",	0x78200036, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
2205 {"subl.ob", "Y,Q",	0x78000436, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
2206 {"subl.qh", "Y,Q",	0x78200436, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
2207 {"subu",    "d,v,t",	0x00000023, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
2208 {"subu",    "d,v,I",	0,    (int) M_SUBU_I,	INSN_MACRO,		0,		I1	},
2209 {"suspend", "",         0x42000022, 0xffffffff,	0,			0,		V1	},
2210 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,	0,		I5|I33|N55},
2211 {"sw",      "t,o(b)",	0xac000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
2212 {"sw",      "t,A(b)",	0,    (int) M_SW_AB,	INSN_MACRO,		0,		I1	},
2213 {"swc0",    "E,o(b)",	0xe0000000, 0xfc000000,	SM|RD_C0|RD_b,		0,		I1	},
2214 {"swc0",    "E,A(b)",	0,    (int) M_SWC0_AB,	INSN_MACRO,		0,		I1	},
2215 {"swc1",    "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1	},
2216 {"swc1",    "E,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1	},
2217 {"swc1",    "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		0,		I1	},
2218 {"swc1",    "E,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		0,		I1	},
2219 {"s.s",     "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1	}, /* swc1 */
2220 {"s.s",     "T,A(b)",	0,    (int) M_SWC1_AB,	INSN_MACRO,		0,		I1	},
2221 {"swc2",    "E,o(b)",	0xe8000000, 0xfc000000,	SM|RD_C2|RD_b,		0,		I1	},
2222 {"swc2",    "E,A(b)",	0,    (int) M_SWC2_AB,	INSN_MACRO,		0,		I1	},
2223 {"swc3",    "E,o(b)",	0xec000000, 0xfc000000,	SM|RD_C3|RD_b,		0,		I1	},
2224 {"swc3",    "E,A(b)",	0,    (int) M_SWC3_AB,	INSN_MACRO,		0,		I1	},
2225 {"swl",     "t,o(b)",	0xa8000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
2226 {"swl",     "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I1	},
2227 {"scache",  "t,o(b)",	0xa8000000, 0xfc000000,	RD_t|RD_b,		0,		I2	}, /* same */
2228 {"scache",  "t,A(b)",	0,    (int) M_SWL_AB,	INSN_MACRO,		0,		I2	}, /* as swl */
2229 {"swr",     "t,o(b)",	0xb8000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
2230 {"swr",     "t,A(b)",	0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I1	},
2231 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000,	RD_t|RD_b,		0,		I2	}, /* same */
2232 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,	INSN_MACRO,		0,		I2	}, /* as swr */
2233 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,	0,		I4|I33	},
2234 {"sync",    "",		0x0000000f, 0xffffffff,	INSN_SYNC,		0,		I2|G1	},
2235 {"sync.p",  "",		0x0000040f, 0xffffffff,	INSN_SYNC,		0,		I2	},
2236 {"sync.l",  "",		0x0000000f, 0xffffffff,	INSN_SYNC,		0,		I2	},
2237 {"synci",   "o(b)",	0x041f0000, 0xfc1f0000,	SM|RD_b,		0,		I33	},
2238 {"syscall", "",		0x0000000c, 0xffffffff,	TRAP,			0,		I1	},
2239 {"syscall", "B",	0x0000000c, 0xfc00003f,	TRAP,			0,		I1	},
2240 {"teqi",    "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
2241 {"teq",	    "s,t",	0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2	},
2242 {"teq",	    "s,t,q",	0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2	},
2243 {"teq",     "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	}, /* teqi */
2244 {"teq",     "s,I",	0,    (int) M_TEQ_I,	INSN_MACRO,		0,		I2	},
2245 {"tgei",    "s,j",	0x04080000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
2246 {"tge",	    "s,t",	0x00000030, 0xfc00ffff,	RD_s|RD_t|TRAP,		0,		I2	},
2247 {"tge",	    "s,t,q",	0x00000030, 0xfc00003f,	RD_s|RD_t|TRAP,		0,		I2	},
2248 {"tge",     "s,j",	0x04080000, 0xfc1f0000, RD_s|TRAP,		0,		I2	}, /* tgei */
2249 {"tge",	    "s,I",	0,    (int) M_TGE_I,    INSN_MACRO,		0,		I2	},
2250 {"tgeiu",   "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
2251 {"tgeu",    "s,t",	0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2	},
2252 {"tgeu",    "s,t,q",	0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2	},
2253 {"tgeu",    "s,j",	0x04090000, 0xfc1f0000, RD_s|TRAP,		0,		I2	}, /* tgeiu */
2254 {"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,		0,		I2	},
2255 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,       	0,		I1   	},
2256 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,       	0,		I1   	},
2257 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,       	0,		I1   	},
2258 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,       	0,		I1   	},
2259 {"tlti",    "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,		0,		I2	},
2260 {"tlt",     "s,t",	0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2	},
2261 {"tlt",     "s,t,q",	0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2	},
2262 {"tlt",     "s,j",	0x040a0000, 0xfc1f0000,	RD_s|TRAP,		0,		I2	}, /* tlti */
2263 {"tlt",     "s,I",	0,    (int) M_TLT_I,	INSN_MACRO,		0,		I2	},
2264 {"tltiu",   "s,j",	0x040b0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
2265 {"tltu",    "s,t",	0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2	},
2266 {"tltu",    "s,t,q",	0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2	},
2267 {"tltu",    "s,j",	0x040b0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	}, /* tltiu */
2268 {"tltu",    "s,I",	0,    (int) M_TLTU_I,	INSN_MACRO,		0,		I2	},
2269 {"tnei",    "s,j",	0x040e0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	},
2270 {"tne",     "s,t",	0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,		0,		I2	},
2271 {"tne",     "s,t,q",	0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,		0,		I2	},
2272 {"tne",     "s,j",	0x040e0000, 0xfc1f0000, RD_s|TRAP,		0,		I2	}, /* tnei */
2273 {"tne",     "s,I",	0,    (int) M_TNE_I,	INSN_MACRO,		0,		I2	},
2274 {"trunc.l.d", "D,S",	0x46200009, 0xffff003f, WR_D|RD_S|FP_D,		0,		I3|I33	},
2275 {"trunc.l.s", "D,S",	0x46000009, 0xffff003f,	WR_D|RD_S|FP_S|FP_D,	0,		I3|I33	},
2276 {"trunc.w.d", "D,S",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
2277 {"trunc.w.d", "D,S,x",	0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,	0,		I2	},
2278 {"trunc.w.d", "D,S,t",	0,    (int) M_TRUNCWD,	INSN_MACRO,		0,		I1	},
2279 {"trunc.w.s", "D,S",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I2	},
2280 {"trunc.w.s", "D,S,x",	0x4600000d, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I2	},
2281 {"trunc.w.s", "D,S,t",	0,    (int) M_TRUNCWS,	INSN_MACRO,		0,		I1	},
2282 {"uld",     "t,o(b)",	0,    (int) M_ULD,	INSN_MACRO,		0,		I3	},
2283 {"uld",     "t,A(b)",	0,    (int) M_ULD_A,	INSN_MACRO,		0,		I3	},
2284 {"ulh",     "t,o(b)",	0,    (int) M_ULH,	INSN_MACRO,		0,		I1	},
2285 {"ulh",     "t,A(b)",	0,    (int) M_ULH_A,	INSN_MACRO,		0,		I1	},
2286 {"ulhu",    "t,o(b)",	0,    (int) M_ULHU,	INSN_MACRO,		0,		I1	},
2287 {"ulhu",    "t,A(b)",	0,    (int) M_ULHU_A,	INSN_MACRO,		0,		I1	},
2288 {"ulw",     "t,o(b)",	0,    (int) M_ULW,	INSN_MACRO,		0,		I1	},
2289 {"ulw",     "t,A(b)",	0,    (int) M_ULW_A,	INSN_MACRO,		0,		I1	},
2290 {"usd",     "t,o(b)",	0,    (int) M_USD,	INSN_MACRO,		0,		I3	},
2291 {"usd",     "t,A(b)",	0,    (int) M_USD_A,	INSN_MACRO,		0,		I3	},
2292 {"ush",     "t,o(b)",	0,    (int) M_USH,	INSN_MACRO,		0,		I1	},
2293 {"ush",     "t,A(b)",	0,    (int) M_USH_A,	INSN_MACRO,		0,		I1	},
2294 {"usw",     "t,o(b)",	0,    (int) M_USW,	INSN_MACRO,		0,		I1	},
2295 {"usw",     "t,A(b)",	0,    (int) M_USW_A,	INSN_MACRO,		0,		I1	},
2296 {"wach.ob", "Y",	0x7a00003e, 0xffff07ff,	RD_S|FP_D,		WR_MACC,	MX|SB1	},
2297 {"wach.ob", "S",	0x4a00003e, 0xffff07ff,	RD_S,			0,		N54	},
2298 {"wach.qh", "Y",	0x7a20003e, 0xffff07ff,	RD_S|FP_D,		WR_MACC,	MX	},
2299 {"wacl.ob", "Y,Z",	0x7800003e, 0xffe007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX|SB1	},
2300 {"wacl.ob", "S,T",	0x4800003e, 0xffe007ff,	RD_S|RD_T,		0,		N54	},
2301 {"wacl.qh", "Y,Z",	0x7820003e, 0xffe007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
2302 {"wait",    "",         0x42000020, 0xffffffff, TRAP,   		0,		I3|I32	},
2303 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,   		0,		I32|N55	},
2304 {"waiti",   "",		0x42000020, 0xffffffff,	TRAP,			0,		L1	},
2305 {"wrpgpr",  "d,w",	0x41c00000, 0xffe007ff, RD_t,			0,		I33	},
2306 {"wsbh",    "d,w",	0x7c0000a0, 0xffe007ff,	WR_d|RD_t,		0,		I33	},
2307 {"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
2308 {"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,		0,		I1	},
2309 {"xor.ob",  "X,Y,Q",	0x7800000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
2310 {"xor.ob",  "D,S,T",	0x4ac0000d, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2311 {"xor.ob",  "D,S,T[e]",	0x4800000d, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
2312 {"xor.ob",  "D,S,k",	0x4bc0000d, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
2313 {"xor.qh",  "X,Y,Q",	0x7820000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
2314 {"xori",    "t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
2315 {"yield",   "s",	0x7c000009, 0xfc1fffff, TRAP|RD_s,		0,		MT32	},
2316 {"yield",   "d,s",	0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s,		0,		MT32	},
2317 
2318 /* User Defined Instruction.  */
2319 {"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2320 {"udi0",     "s,t,+2",	0x70000010, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2321 {"udi0",     "s,+3",	0x70000010, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2322 {"udi0",     "+4",	0x70000010, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2323 {"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2324 {"udi1",     "s,t,+2",	0x70000011, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2325 {"udi1",     "s,+3",	0x70000011, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2326 {"udi1",     "+4",	0x70000011, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2327 {"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2328 {"udi2",     "s,t,+2",	0x70000012, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2329 {"udi2",     "s,+3",	0x70000012, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2330 {"udi2",     "+4",	0x70000012, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2331 {"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2332 {"udi3",     "s,t,+2",	0x70000013, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2333 {"udi3",     "s,+3",	0x70000013, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2334 {"udi3",     "+4",	0x70000013, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2335 {"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2336 {"udi4",     "s,t,+2",	0x70000014, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2337 {"udi4",     "s,+3",	0x70000014, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2338 {"udi4",     "+4",	0x70000014, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2339 {"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2340 {"udi5",     "s,t,+2",	0x70000015, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2341 {"udi5",     "s,+3",	0x70000015, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2342 {"udi5",     "+4",	0x70000015, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2343 {"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2344 {"udi6",     "s,t,+2",	0x70000016, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2345 {"udi6",     "s,+3",	0x70000016, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2346 {"udi6",     "+4",	0x70000016, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2347 {"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2348 {"udi7",     "s,t,+2",	0x70000017, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2349 {"udi7",     "s,+3",	0x70000017, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2350 {"udi7",     "+4",	0x70000017, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2351 {"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2352 {"udi8",     "s,t,+2",	0x70000018, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2353 {"udi8",     "s,+3",	0x70000018, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2354 {"udi8",     "+4",	0x70000018, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2355 {"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2356 {"udi9",      "s,t,+2",	0x70000019, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2357 {"udi9",     "s,+3",	0x70000019, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2358 {"udi9",     "+4",	0x70000019, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2359 {"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2360 {"udi10",    "s,t,+2",	0x7000001a, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2361 {"udi10",    "s,+3",	0x7000001a, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2362 {"udi10",    "+4",	0x7000001a, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2363 {"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2364 {"udi11",    "s,t,+2",	0x7000001b, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2365 {"udi11",    "s,+3",	0x7000001b, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2366 {"udi11",    "+4",	0x7000001b, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2367 {"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2368 {"udi12",    "s,t,+2",	0x7000001c, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2369 {"udi12",    "s,+3",	0x7000001c, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2370 {"udi12",    "+4",	0x7000001c, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2371 {"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2372 {"udi13",    "s,t,+2",	0x7000001d, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2373 {"udi13",    "s,+3",	0x7000001d, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2374 {"udi13",    "+4",	0x7000001d, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2375 {"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2376 {"udi14",    "s,t,+2",	0x7000001e, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2377 {"udi14",    "s,+3",	0x7000001e, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2378 {"udi14",    "+4",	0x7000001e, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2379 {"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2380 {"udi15",    "s,t,+2",	0x7000001f, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2381 {"udi15",    "s,+3",	0x7000001f, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2382 {"udi15",    "+4",	0x7000001f, 0xfc00003f,	WR_d|RD_s|RD_t,		0,		I33	},
2383 
2384 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
2385    instructions so they are here for the latters to take precedence.  */
2386 {"bc2f",    "p",	0x49000000, 0xffff0000,	CBD|RD_CC,		0,		I1	},
2387 {"bc2f",    "N,p",	0x49000000, 0xffe30000,	CBD|RD_CC,		0,		I32	},
2388 {"bc2fl",   "p",	0x49020000, 0xffff0000,	CBL|RD_CC,		0,		I2|T3	},
2389 {"bc2fl",   "N,p",	0x49020000, 0xffe30000,	CBL|RD_CC,		0,		I32	},
2390 {"bc2t",    "p",	0x49010000, 0xffff0000,