xref: /illumos-kvm-cmd/hw/sh7750.c (revision 68396ea9)
1 /*
2  * SH7750 device
3  *
4  * Copyright (c) 2007 Magnus Damm
5  * Copyright (c) 2005 Samuel Tardieu
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 #include <stdio.h>
26 #include "hw.h"
27 #include "sh.h"
28 #include "sysemu.h"
29 #include "sh7750_regs.h"
30 #include "sh7750_regnames.h"
31 #include "sh_intc.h"
32 #include "exec-all.h"
33 #include "cpu.h"
34 
35 #define NB_DEVICES 4
36 
37 typedef struct SH7750State {
38     /* CPU */
39     CPUSH4State *cpu;
40     /* Peripheral frequency in Hz */
41     uint32_t periph_freq;
42     /* SDRAM controller */
43     uint32_t bcr1;
44     uint16_t bcr2;
45     uint16_t bcr3;
46     uint32_t bcr4;
47     uint16_t rfcr;
48     /* PCMCIA controller */
49     uint16_t pcr;
50     /* IO ports */
51     uint16_t gpioic;
52     uint32_t pctra;
53     uint32_t pctrb;
54     uint16_t portdira;		/* Cached */
55     uint16_t portpullupa;	/* Cached */
56     uint16_t portdirb;		/* Cached */
57     uint16_t portpullupb;	/* Cached */
58     uint16_t pdtra;
59     uint16_t pdtrb;
60     uint16_t periph_pdtra;	/* Imposed by the peripherals */
61     uint16_t periph_portdira;	/* Direction seen from the peripherals */
62     uint16_t periph_pdtrb;	/* Imposed by the peripherals */
63     uint16_t periph_portdirb;	/* Direction seen from the peripherals */
64     sh7750_io_device *devices[NB_DEVICES];	/* External peripherals */
65 
66     /* Cache */
67     uint32_t ccr;
68 
69     struct intc_desc intc;
70 } SH7750State;
71 
has_bcr3_and_bcr4(SH7750State * s)72 static inline int has_bcr3_and_bcr4(SH7750State * s)
73 {
74 	return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
75 }
76 /**********************************************************************
77  I/O ports
78 **********************************************************************/
79 
sh7750_register_io_device(SH7750State * s,sh7750_io_device * device)80 int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
81 {
82     int i;
83 
84     for (i = 0; i < NB_DEVICES; i++) {
85 	if (s->devices[i] == NULL) {
86 	    s->devices[i] = device;
87 	    return 0;
88 	}
89     }
90     return -1;
91 }
92 
portdir(uint32_t v)93 static uint16_t portdir(uint32_t v)
94 {
95 #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
96     return
97 	EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
98 	EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
99 	EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
100 	EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
101 	EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
102 	EVENPORTMASK(0);
103 }
104 
portpullup(uint32_t v)105 static uint16_t portpullup(uint32_t v)
106 {
107 #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
108     return
109 	ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
110 	ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
111 	ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
112 	ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
113 	ODDPORTMASK(1) | ODDPORTMASK(0);
114 }
115 
porta_lines(SH7750State * s)116 static uint16_t porta_lines(SH7750State * s)
117 {
118     return (s->portdira & s->pdtra) |	/* CPU */
119 	(s->periph_portdira & s->periph_pdtra) |	/* Peripherals */
120 	(~(s->portdira | s->periph_portdira) & s->portpullupa);	/* Pullups */
121 }
122 
portb_lines(SH7750State * s)123 static uint16_t portb_lines(SH7750State * s)
124 {
125     return (s->portdirb & s->pdtrb) |	/* CPU */
126 	(s->periph_portdirb & s->periph_pdtrb) |	/* Peripherals */
127 	(~(s->portdirb | s->periph_portdirb) & s->portpullupb);	/* Pullups */
128 }
129 
gen_port_interrupts(SH7750State * s)130 static void gen_port_interrupts(SH7750State * s)
131 {
132     /* XXXXX interrupts not generated */
133 }
134 
porta_changed(SH7750State * s,uint16_t prev)135 static void porta_changed(SH7750State * s, uint16_t prev)
136 {
137     uint16_t currenta, changes;
138     int i, r = 0;
139 
140 #if 0
141     fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
142 	    prev, porta_lines(s));
143     fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
144 #endif
145     currenta = porta_lines(s);
146     if (currenta == prev)
147 	return;
148     changes = currenta ^ prev;
149 
150     for (i = 0; i < NB_DEVICES; i++) {
151 	if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
152 	    r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
153 					       &s->periph_pdtra,
154 					       &s->periph_portdira,
155 					       &s->periph_pdtrb,
156 					       &s->periph_portdirb);
157 	}
158     }
159 
160     if (r)
161 	gen_port_interrupts(s);
162 }
163 
portb_changed(SH7750State * s,uint16_t prev)164 static void portb_changed(SH7750State * s, uint16_t prev)
165 {
166     uint16_t currentb, changes;
167     int i, r = 0;
168 
169     currentb = portb_lines(s);
170     if (currentb == prev)
171 	return;
172     changes = currentb ^ prev;
173 
174     for (i = 0; i < NB_DEVICES; i++) {
175 	if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
176 	    r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
177 					       &s->periph_pdtra,
178 					       &s->periph_portdira,
179 					       &s->periph_pdtrb,
180 					       &s->periph_portdirb);
181 	}
182     }
183 
184     if (r)
185 	gen_port_interrupts(s);
186 }
187 
188 /**********************************************************************
189  Memory
190 **********************************************************************/
191 
error_access(const char * kind,target_phys_addr_t addr)192 static void error_access(const char *kind, target_phys_addr_t addr)
193 {
194     fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
195 	    kind, regname(addr), addr);
196 }
197 
ignore_access(const char * kind,target_phys_addr_t addr)198 static void ignore_access(const char *kind, target_phys_addr_t addr)
199 {
200     fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
201 	    kind, regname(addr), addr);
202 }
203 
sh7750_mem_readb(void * opaque,target_phys_addr_t addr)204 static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
205 {
206     switch (addr) {
207     default:
208 	error_access("byte read", addr);
209         abort();
210     }
211 }
212 
sh7750_mem_readw(void * opaque,target_phys_addr_t addr)213 static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
214 {
215     SH7750State *s = opaque;
216 
217     switch (addr) {
218     case SH7750_BCR2_A7:
219 	return s->bcr2;
220     case SH7750_BCR3_A7:
221 	if(!has_bcr3_and_bcr4(s))
222 	    error_access("word read", addr);
223 	return s->bcr3;
224     case SH7750_FRQCR_A7:
225 	return 0;
226     case SH7750_PCR_A7:
227 	return s->pcr;
228     case SH7750_RFCR_A7:
229 	fprintf(stderr,
230 		"Read access to refresh count register, incrementing\n");
231 	return s->rfcr++;
232     case SH7750_PDTRA_A7:
233 	return porta_lines(s);
234     case SH7750_PDTRB_A7:
235 	return portb_lines(s);
236     case SH7750_RTCOR_A7:
237     case SH7750_RTCNT_A7:
238     case SH7750_RTCSR_A7:
239 	ignore_access("word read", addr);
240 	return 0;
241     default:
242 	error_access("word read", addr);
243         abort();
244     }
245 }
246 
sh7750_mem_readl(void * opaque,target_phys_addr_t addr)247 static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
248 {
249     SH7750State *s = opaque;
250 
251     switch (addr) {
252     case SH7750_BCR1_A7:
253 	return s->bcr1;
254     case SH7750_BCR4_A7:
255 	if(!has_bcr3_and_bcr4(s))
256 	    error_access("long read", addr);
257 	return s->bcr4;
258     case SH7750_WCR1_A7:
259     case SH7750_WCR2_A7:
260     case SH7750_WCR3_A7:
261     case SH7750_MCR_A7:
262         ignore_access("long read", addr);
263         return 0;
264     case SH7750_MMUCR_A7:
265 	return s->cpu->mmucr;
266     case SH7750_PTEH_A7:
267 	return s->cpu->pteh;
268     case SH7750_PTEL_A7:
269 	return s->cpu->ptel;
270     case SH7750_TTB_A7:
271 	return s->cpu->ttb;
272     case SH7750_TEA_A7:
273 	return s->cpu->tea;
274     case SH7750_TRA_A7:
275 	return s->cpu->tra;
276     case SH7750_EXPEVT_A7:
277 	return s->cpu->expevt;
278     case SH7750_INTEVT_A7:
279 	return s->cpu->intevt;
280     case SH7750_CCR_A7:
281 	return s->ccr;
282     case 0x1f000030:		/* Processor version */
283 	return s->cpu->pvr;
284     case 0x1f000040:		/* Cache version */
285 	return s->cpu->cvr;
286     case 0x1f000044:		/* Processor revision */
287 	return s->cpu->prr;
288     default:
289 	error_access("long read", addr);
290         abort();
291     }
292 }
293 
294 #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
295 			&& a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
sh7750_mem_writeb(void * opaque,target_phys_addr_t addr,uint32_t mem_value)296 static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
297 			      uint32_t mem_value)
298 {
299 
300     if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
301 	ignore_access("byte write", addr);
302 	return;
303     }
304 
305     error_access("byte write", addr);
306     abort();
307 }
308 
sh7750_mem_writew(void * opaque,target_phys_addr_t addr,uint32_t mem_value)309 static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
310 			      uint32_t mem_value)
311 {
312     SH7750State *s = opaque;
313     uint16_t temp;
314 
315     switch (addr) {
316 	/* SDRAM controller */
317     case SH7750_BCR2_A7:
318         s->bcr2 = mem_value;
319         return;
320     case SH7750_BCR3_A7:
321 	if(!has_bcr3_and_bcr4(s))
322 	    error_access("word write", addr);
323 	s->bcr3 = mem_value;
324 	return;
325     case SH7750_PCR_A7:
326 	s->pcr = mem_value;
327 	return;
328     case SH7750_RTCNT_A7:
329     case SH7750_RTCOR_A7:
330     case SH7750_RTCSR_A7:
331 	ignore_access("word write", addr);
332 	return;
333 	/* IO ports */
334     case SH7750_PDTRA_A7:
335 	temp = porta_lines(s);
336 	s->pdtra = mem_value;
337 	porta_changed(s, temp);
338 	return;
339     case SH7750_PDTRB_A7:
340 	temp = portb_lines(s);
341 	s->pdtrb = mem_value;
342 	portb_changed(s, temp);
343 	return;
344     case SH7750_RFCR_A7:
345 	fprintf(stderr, "Write access to refresh count register\n");
346 	s->rfcr = mem_value;
347 	return;
348     case SH7750_GPIOIC_A7:
349 	s->gpioic = mem_value;
350 	if (mem_value != 0) {
351 	    fprintf(stderr, "I/O interrupts not implemented\n");
352             abort();
353 	}
354 	return;
355     default:
356 	error_access("word write", addr);
357         abort();
358     }
359 }
360 
sh7750_mem_writel(void * opaque,target_phys_addr_t addr,uint32_t mem_value)361 static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
362 			      uint32_t mem_value)
363 {
364     SH7750State *s = opaque;
365     uint16_t temp;
366 
367     switch (addr) {
368 	/* SDRAM controller */
369     case SH7750_BCR1_A7:
370         s->bcr1 = mem_value;
371         return;
372     case SH7750_BCR4_A7:
373 	if(!has_bcr3_and_bcr4(s))
374 	    error_access("long write", addr);
375 	s->bcr4 = mem_value;
376 	return;
377     case SH7750_WCR1_A7:
378     case SH7750_WCR2_A7:
379     case SH7750_WCR3_A7:
380     case SH7750_MCR_A7:
381 	ignore_access("long write", addr);
382 	return;
383 	/* IO ports */
384     case SH7750_PCTRA_A7:
385 	temp = porta_lines(s);
386 	s->pctra = mem_value;
387 	s->portdira = portdir(mem_value);
388 	s->portpullupa = portpullup(mem_value);
389 	porta_changed(s, temp);
390 	return;
391     case SH7750_PCTRB_A7:
392 	temp = portb_lines(s);
393 	s->pctrb = mem_value;
394 	s->portdirb = portdir(mem_value);
395 	s->portpullupb = portpullup(mem_value);
396 	portb_changed(s, temp);
397 	return;
398     case SH7750_MMUCR_A7:
399         if (mem_value & MMUCR_TI) {
400             cpu_sh4_invalidate_tlb(s->cpu);
401         }
402         s->cpu->mmucr = mem_value & ~MMUCR_TI;
403         return;
404     case SH7750_PTEH_A7:
405         /* If asid changes, clear all registered tlb entries. */
406 	if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
407 	    tlb_flush(s->cpu, 1);
408 	s->cpu->pteh = mem_value;
409 	return;
410     case SH7750_PTEL_A7:
411 	s->cpu->ptel = mem_value;
412 	return;
413     case SH7750_PTEA_A7:
414 	s->cpu->ptea = mem_value & 0x0000000f;
415 	return;
416     case SH7750_TTB_A7:
417 	s->cpu->ttb = mem_value;
418 	return;
419     case SH7750_TEA_A7:
420 	s->cpu->tea = mem_value;
421 	return;
422     case SH7750_TRA_A7:
423 	s->cpu->tra = mem_value & 0x000007ff;
424 	return;
425     case SH7750_EXPEVT_A7:
426 	s->cpu->expevt = mem_value & 0x000007ff;
427 	return;
428     case SH7750_INTEVT_A7:
429 	s->cpu->intevt = mem_value & 0x000007ff;
430 	return;
431     case SH7750_CCR_A7:
432 	s->ccr = mem_value;
433 	return;
434     default:
435 	error_access("long write", addr);
436         abort();
437     }
438 }
439 
440 static CPUReadMemoryFunc * const sh7750_mem_read[] = {
441     sh7750_mem_readb,
442     sh7750_mem_readw,
443     sh7750_mem_readl
444 };
445 
446 static CPUWriteMemoryFunc * const sh7750_mem_write[] = {
447     sh7750_mem_writeb,
448     sh7750_mem_writew,
449     sh7750_mem_writel
450 };
451 
452 /* sh775x interrupt controller tables for sh_intc.c
453  * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
454  */
455 
456 enum {
457 	UNUSED = 0,
458 
459 	/* interrupt sources */
460 	IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7,
461 	IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E,
462 	IRL0, IRL1, IRL2, IRL3,
463 	HUDI, GPIOI,
464 	DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
465 	DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
466 	DMAC_DMAE,
467 	PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
468 	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
469 	TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
470 	RTC_ATI, RTC_PRI, RTC_CUI,
471 	SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
472 	SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
473 	WDT,
474 	REF_RCMI, REF_ROVI,
475 
476 	/* interrupt groups */
477 	DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
478 	/* irl bundle */
479 	IRL,
480 
481 	NR_SOURCES,
482 };
483 
484 static struct intc_vect vectors[] = {
485 	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
486 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
487 	INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
488 	INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
489 	INTC_VECT(RTC_CUI, 0x4c0),
490 	INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
491 	INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
492 	INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
493 	INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
494 	INTC_VECT(WDT, 0x560),
495 	INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
496 };
497 
498 static struct intc_group groups[] = {
499 	INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
500 	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
501 	INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
502 	INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
503 	INTC_GROUP(REF, REF_RCMI, REF_ROVI),
504 };
505 
506 static struct intc_prio_reg prio_registers[] = {
507 	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
508 	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
509 	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
510 	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
511 	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
512 						 TMU4, TMU3,
513 						 PCIC1, PCIC0_PCISERR } },
514 };
515 
516 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
517 
518 static struct intc_vect vectors_dma4[] = {
519 	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
520 	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
521 	INTC_VECT(DMAC_DMAE, 0x6c0),
522 };
523 
524 static struct intc_group groups_dma4[] = {
525 	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
526 		   DMAC_DMTE3, DMAC_DMAE),
527 };
528 
529 /* SH7750R and SH7751R both have 8-channel DMA controllers */
530 
531 static struct intc_vect vectors_dma8[] = {
532 	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
533 	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
534 	INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
535 	INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
536 	INTC_VECT(DMAC_DMAE, 0x6c0),
537 };
538 
539 static struct intc_group groups_dma8[] = {
540 	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
541 		   DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
542 		   DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
543 };
544 
545 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
546 
547 static struct intc_vect vectors_tmu34[] = {
548 	INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
549 };
550 
551 static struct intc_mask_reg mask_registers[] = {
552 	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
553 	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
554 	    0, 0, 0, 0, 0, 0, TMU4, TMU3,
555 	    PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
556 	    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
557 	    PCIC1_PCIDMA3, PCIC0_PCISERR } },
558 };
559 
560 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
561 
562 static struct intc_vect vectors_irlm[] = {
563 	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
564 	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
565 };
566 
567 /* SH7751 and SH7751R both have PCI */
568 
569 static struct intc_vect vectors_pci[] = {
570 	INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
571 	INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
572 	INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
573 	INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
574 };
575 
576 static struct intc_group groups_pci[] = {
577 	INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
578 		   PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
579 };
580 
581 static struct intc_vect vectors_irl[] = {
582 	INTC_VECT(IRL_0, 0x200),
583 	INTC_VECT(IRL_1, 0x220),
584 	INTC_VECT(IRL_2, 0x240),
585 	INTC_VECT(IRL_3, 0x260),
586 	INTC_VECT(IRL_4, 0x280),
587 	INTC_VECT(IRL_5, 0x2a0),
588 	INTC_VECT(IRL_6, 0x2c0),
589 	INTC_VECT(IRL_7, 0x2e0),
590 	INTC_VECT(IRL_8, 0x300),
591 	INTC_VECT(IRL_9, 0x320),
592 	INTC_VECT(IRL_A, 0x340),
593 	INTC_VECT(IRL_B, 0x360),
594 	INTC_VECT(IRL_C, 0x380),
595 	INTC_VECT(IRL_D, 0x3a0),
596 	INTC_VECT(IRL_E, 0x3c0),
597 };
598 
599 static struct intc_group groups_irl[] = {
600 	INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6,
601 		IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
602 };
603 
604 /**********************************************************************
605  Memory mapped cache and TLB
606 **********************************************************************/
607 
608 #define MM_REGION_MASK   0x07000000
609 #define MM_ICACHE_ADDR   (0)
610 #define MM_ICACHE_DATA   (1)
611 #define MM_ITLB_ADDR     (2)
612 #define MM_ITLB_DATA     (3)
613 #define MM_OCACHE_ADDR   (4)
614 #define MM_OCACHE_DATA   (5)
615 #define MM_UTLB_ADDR     (6)
616 #define MM_UTLB_DATA     (7)
617 #define MM_REGION_TYPE(addr)  ((addr & MM_REGION_MASK) >> 24)
618 
invalid_read(void * opaque,target_phys_addr_t addr)619 static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
620 {
621     abort();
622 
623     return 0;
624 }
625 
sh7750_mmct_readl(void * opaque,target_phys_addr_t addr)626 static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
627 {
628     SH7750State *s = opaque;
629     uint32_t ret = 0;
630 
631     switch (MM_REGION_TYPE(addr)) {
632     case MM_ICACHE_ADDR:
633     case MM_ICACHE_DATA:
634         /* do nothing */
635 	break;
636     case MM_ITLB_ADDR:
637         ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr);
638         break;
639     case MM_ITLB_DATA:
640         ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr);
641         break;
642     case MM_OCACHE_ADDR:
643     case MM_OCACHE_DATA:
644         /* do nothing */
645 	break;
646     case MM_UTLB_ADDR:
647         ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr);
648         break;
649     case MM_UTLB_DATA:
650         ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr);
651         break;
652     default:
653         abort();
654     }
655 
656     return ret;
657 }
658 
invalid_write(void * opaque,target_phys_addr_t addr,uint32_t mem_value)659 static void invalid_write(void *opaque, target_phys_addr_t addr,
660 			  uint32_t mem_value)
661 {
662     abort();
663 }
664 
sh7750_mmct_writel(void * opaque,target_phys_addr_t addr,uint32_t mem_value)665 static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
666 				uint32_t mem_value)
667 {
668     SH7750State *s = opaque;
669 
670     switch (MM_REGION_TYPE(addr)) {
671     case MM_ICACHE_ADDR:
672     case MM_ICACHE_DATA:
673         /* do nothing */
674 	break;
675     case MM_ITLB_ADDR:
676         cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value);
677         break;
678     case MM_ITLB_DATA:
679         cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value);
680         abort();
681 	break;
682     case MM_OCACHE_ADDR:
683     case MM_OCACHE_DATA:
684         /* do nothing */
685 	break;
686     case MM_UTLB_ADDR:
687         cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value);
688 	break;
689     case MM_UTLB_DATA:
690         cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value);
691 	break;
692     default:
693         abort();
694 	break;
695     }
696 }
697 
698 static CPUReadMemoryFunc * const sh7750_mmct_read[] = {
699     invalid_read,
700     invalid_read,
701     sh7750_mmct_readl
702 };
703 
704 static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
705     invalid_write,
706     invalid_write,
707     sh7750_mmct_writel
708 };
709 
sh7750_init(CPUSH4State * cpu)710 SH7750State *sh7750_init(CPUSH4State * cpu)
711 {
712     SH7750State *s;
713     int sh7750_io_memory;
714     int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
715 
716     s = qemu_mallocz(sizeof(SH7750State));
717     s->cpu = cpu;
718     s->periph_freq = 60000000;	/* 60MHz */
719     sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read,
720 					      sh7750_mem_write, s,
721                                               DEVICE_NATIVE_ENDIAN);
722     cpu_register_physical_memory_offset(0x1f000000, 0x1000,
723                                         sh7750_io_memory, 0x1f000000);
724     cpu_register_physical_memory_offset(0xff000000, 0x1000,
725                                         sh7750_io_memory, 0x1f000000);
726     cpu_register_physical_memory_offset(0x1f800000, 0x1000,
727                                         sh7750_io_memory, 0x1f800000);
728     cpu_register_physical_memory_offset(0xff800000, 0x1000,
729                                         sh7750_io_memory, 0x1f800000);
730     cpu_register_physical_memory_offset(0x1fc00000, 0x1000,
731                                         sh7750_io_memory, 0x1fc00000);
732     cpu_register_physical_memory_offset(0xffc00000, 0x1000,
733                                         sh7750_io_memory, 0x1fc00000);
734 
735     sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read,
736 						     sh7750_mmct_write, s,
737                                                      DEVICE_NATIVE_ENDIAN);
738     cpu_register_physical_memory(0xf0000000, 0x08000000,
739 				 sh7750_mm_cache_and_tlb);
740 
741     sh_intc_init(&s->intc, NR_SOURCES,
742 		 _INTC_ARRAY(mask_registers),
743 		 _INTC_ARRAY(prio_registers));
744 
745     sh_intc_register_sources(&s->intc,
746 			     _INTC_ARRAY(vectors),
747 			     _INTC_ARRAY(groups));
748 
749     cpu->intc_handle = &s->intc;
750 
751     sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
752 		   s->intc.irqs[SCI1_ERI],
753 		   s->intc.irqs[SCI1_RXI],
754 		   s->intc.irqs[SCI1_TXI],
755 		   s->intc.irqs[SCI1_TEI],
756 		   NULL);
757     sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
758 		   s->periph_freq, serial_hds[1],
759 		   s->intc.irqs[SCIF_ERI],
760 		   s->intc.irqs[SCIF_RXI],
761 		   s->intc.irqs[SCIF_TXI],
762 		   NULL,
763 		   s->intc.irqs[SCIF_BRI]);
764 
765     tmu012_init(0x1fd80000,
766 		TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
767 		s->periph_freq,
768 		s->intc.irqs[TMU0],
769 		s->intc.irqs[TMU1],
770 		s->intc.irqs[TMU2_TUNI],
771 		s->intc.irqs[TMU2_TICPI]);
772 
773     if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
774         sh_intc_register_sources(&s->intc,
775 				 _INTC_ARRAY(vectors_dma4),
776 				 _INTC_ARRAY(groups_dma4));
777     }
778 
779     if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
780         sh_intc_register_sources(&s->intc,
781 				 _INTC_ARRAY(vectors_dma8),
782 				 _INTC_ARRAY(groups_dma8));
783     }
784 
785     if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
786         sh_intc_register_sources(&s->intc,
787 				 _INTC_ARRAY(vectors_tmu34),
788 				 NULL, 0);
789         tmu012_init(0x1e100000, 0, s->periph_freq,
790 		    s->intc.irqs[TMU3],
791 		    s->intc.irqs[TMU4],
792 		    NULL, NULL);
793     }
794 
795     if (cpu->id & (SH_CPU_SH7751_ALL)) {
796         sh_intc_register_sources(&s->intc,
797 				 _INTC_ARRAY(vectors_pci),
798 				 _INTC_ARRAY(groups_pci));
799     }
800 
801     if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
802         sh_intc_register_sources(&s->intc,
803 				 _INTC_ARRAY(vectors_irlm),
804 				 NULL, 0);
805     }
806 
807     sh_intc_register_sources(&s->intc,
808 				_INTC_ARRAY(vectors_irl),
809 				_INTC_ARRAY(groups_irl));
810     return s;
811 }
812 
sh7750_irl(SH7750State * s)813 qemu_irq sh7750_irl(SH7750State *s)
814 {
815     sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */
816     return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
817                                1)[0];
818 }
819