xref: /illumos-kvm-cmd/hw/rtl8139.c (revision 3d466c18)
1 /**
2  * QEMU RTL8139 emulation
3  *
4  * Copyright (c) 2006 Igor Kovalenko
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23 
24  * Modifications:
25  *  2006-Jan-28  Mark Malakanov :   TSAD and CSCR implementation (for Windows driver)
26  *
27  *  2006-Apr-28  Juergen Lock   :   EEPROM emulation changes for FreeBSD driver
28  *                                  HW revision ID changes for FreeBSD driver
29  *
30  *  2006-Jul-01  Igor Kovalenko :   Implemented loopback mode for FreeBSD driver
31  *                                  Corrected packet transfer reassembly routine for 8139C+ mode
32  *                                  Rearranged debugging print statements
33  *                                  Implemented PCI timer interrupt (disabled by default)
34  *                                  Implemented Tally Counters, increased VM load/save version
35  *                                  Implemented IP/TCP/UDP checksum task offloading
36  *
37  *  2006-Jul-04  Igor Kovalenko :   Implemented TCP segmentation offloading
38  *                                  Fixed MTU=1500 for produced ethernet frames
39  *
40  *  2006-Jul-09  Igor Kovalenko :   Fixed TCP header length calculation while processing
41  *                                  segmentation offloading
42  *                                  Removed slirp.h dependency
43  *                                  Added rx/tx buffer reset when enabling rx/tx operation
44  *
45  *  2010-Feb-04  Frediano Ziglio:   Rewrote timer support using QEMU timer only
46  *                                  when strictly needed (required for for
47  *                                  Darwin)
48  */
49 
50 #include "hw.h"
51 #include "pci.h"
52 #include "qemu-timer.h"
53 #include "net.h"
54 #include "loader.h"
55 #include "sysemu.h"
56 
57 /* debug RTL8139 card */
58 //#define DEBUG_RTL8139 1
59 
60 #define PCI_FREQUENCY 33000000L
61 
62 /* debug RTL8139 card C+ mode only */
63 //#define DEBUG_RTL8139CP 1
64 
65 /* Calculate CRCs properly on Rx packets */
66 #define RTL8139_CALCULATE_RXCRC 1
67 
68 #if defined(RTL8139_CALCULATE_RXCRC)
69 /* For crc32 */
70 #include <zlib.h>
71 #endif
72 
73 #define SET_MASKED(input, mask, curr) \
74     ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
75 
76 /* arg % size for size which is a power of 2 */
77 #define MOD2(input, size) \
78     ( ( input ) & ( size - 1 )  )
79 
80 #if defined (DEBUG_RTL8139)
81 #  define DEBUG_PRINT(x) do { printf x ; } while (0)
82 #  define DPRINTF(fmt, ...) \
83     do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
84 #else
85 #  define DEBUG_PRINT(x)
DPRINTF(const char * fmt,...)86 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
87 {
88     return 0;
89 }
90 #endif
91 
92 #define	DMA_ADDR_FMT	TARGET_FMT_plx
93 
94 /* Symbolic offsets to registers. */
95 enum RTL8139_registers {
96     MAC0 = 0,        /* Ethernet hardware address. */
97     MAR0 = 8,        /* Multicast filter. */
98     TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
99                      /* Dump Tally Conter control register(64bit). C+ mode only */
100     TxAddr0 = 0x20,  /* Tx descriptors (also four 32bit). */
101     RxBuf = 0x30,
102     ChipCmd = 0x37,
103     RxBufPtr = 0x38,
104     RxBufAddr = 0x3A,
105     IntrMask = 0x3C,
106     IntrStatus = 0x3E,
107     TxConfig = 0x40,
108     RxConfig = 0x44,
109     Timer = 0x48,        /* A general-purpose counter. */
110     RxMissed = 0x4C,    /* 24 bits valid, write clears. */
111     Cfg9346 = 0x50,
112     Config0 = 0x51,
113     Config1 = 0x52,
114     FlashReg = 0x54,
115     MediaStatus = 0x58,
116     Config3 = 0x59,
117     Config4 = 0x5A,        /* absent on RTL-8139A */
118     HltClk = 0x5B,
119     MultiIntr = 0x5C,
120     PCIRevisionID = 0x5E,
121     TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
122     BasicModeCtrl = 0x62,
123     BasicModeStatus = 0x64,
124     NWayAdvert = 0x66,
125     NWayLPAR = 0x68,
126     NWayExpansion = 0x6A,
127     /* Undocumented registers, but required for proper operation. */
128     FIFOTMS = 0x70,        /* FIFO Control and test. */
129     CSCR = 0x74,        /* Chip Status and Configuration Register. */
130     PARA78 = 0x78,
131     PARA7c = 0x7c,        /* Magic transceiver parameter register. */
132     Config5 = 0xD8,        /* absent on RTL-8139A */
133     /* C+ mode */
134     TxPoll        = 0xD9,    /* Tell chip to check Tx descriptors for work */
135     RxMaxSize    = 0xDA, /* Max size of an Rx packet (8169 only) */
136     CpCmd        = 0xE0, /* C+ Command register (C+ mode only) */
137     IntrMitigate    = 0xE2,    /* rx/tx interrupt mitigation control */
138     RxRingAddrLO    = 0xE4, /* 64-bit start addr of Rx ring */
139     RxRingAddrHI    = 0xE8, /* 64-bit start addr of Rx ring */
140     TxThresh    = 0xEC, /* Early Tx threshold */
141 };
142 
143 enum ClearBitMasks {
144     MultiIntrClear = 0xF000,
145     ChipCmdClear = 0xE2,
146     Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
147 };
148 
149 enum ChipCmdBits {
150     CmdReset = 0x10,
151     CmdRxEnb = 0x08,
152     CmdTxEnb = 0x04,
153     RxBufEmpty = 0x01,
154 };
155 
156 /* C+ mode */
157 enum CplusCmdBits {
158     CPlusRxVLAN   = 0x0040, /* enable receive VLAN detagging */
159     CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
160     CPlusRxEnb    = 0x0002,
161     CPlusTxEnb    = 0x0001,
162 };
163 
164 /* Interrupt register bits, using my own meaningful names. */
165 enum IntrStatusBits {
166     PCIErr = 0x8000,
167     PCSTimeout = 0x4000,
168     RxFIFOOver = 0x40,
169     RxUnderrun = 0x20,
170     RxOverflow = 0x10,
171     TxErr = 0x08,
172     TxOK = 0x04,
173     RxErr = 0x02,
174     RxOK = 0x01,
175 
176     RxAckBits = RxFIFOOver | RxOverflow | RxOK,
177 };
178 
179 enum TxStatusBits {
180     TxHostOwns = 0x2000,
181     TxUnderrun = 0x4000,
182     TxStatOK = 0x8000,
183     TxOutOfWindow = 0x20000000,
184     TxAborted = 0x40000000,
185     TxCarrierLost = 0x80000000,
186 };
187 enum RxStatusBits {
188     RxMulticast = 0x8000,
189     RxPhysical = 0x4000,
190     RxBroadcast = 0x2000,
191     RxBadSymbol = 0x0020,
192     RxRunt = 0x0010,
193     RxTooLong = 0x0008,
194     RxCRCErr = 0x0004,
195     RxBadAlign = 0x0002,
196     RxStatusOK = 0x0001,
197 };
198 
199 /* Bits in RxConfig. */
200 enum rx_mode_bits {
201     AcceptErr = 0x20,
202     AcceptRunt = 0x10,
203     AcceptBroadcast = 0x08,
204     AcceptMulticast = 0x04,
205     AcceptMyPhys = 0x02,
206     AcceptAllPhys = 0x01,
207 };
208 
209 /* Bits in TxConfig. */
210 enum tx_config_bits {
211 
212         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
213         TxIFGShift = 24,
214         TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */
215         TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */
216         TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */
217         TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */
218 
219     TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
220     TxCRC = (1 << 16),    /* DISABLE appending CRC to end of Tx packets */
221     TxClearAbt = (1 << 0),    /* Clear abort (WO) */
222     TxDMAShift = 8,        /* DMA burst value (0-7) is shifted this many bits */
223     TxRetryShift = 4,    /* TXRR value (0-15) is shifted this many bits */
224 
225     TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
226 };
227 
228 
229 /* Transmit Status of All Descriptors (TSAD) Register */
230 enum TSAD_bits {
231  TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
232  TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
233  TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
234  TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
235  TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
236  TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
237  TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
238  TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
239  TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
240  TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
241  TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
242  TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
243  TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
244  TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
245  TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
246  TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
247 };
248 
249 
250 /* Bits in Config1 */
251 enum Config1Bits {
252     Cfg1_PM_Enable = 0x01,
253     Cfg1_VPD_Enable = 0x02,
254     Cfg1_PIO = 0x04,
255     Cfg1_MMIO = 0x08,
256     LWAKE = 0x10,        /* not on 8139, 8139A */
257     Cfg1_Driver_Load = 0x20,
258     Cfg1_LED0 = 0x40,
259     Cfg1_LED1 = 0x80,
260     SLEEP = (1 << 1),    /* only on 8139, 8139A */
261     PWRDN = (1 << 0),    /* only on 8139, 8139A */
262 };
263 
264 /* Bits in Config3 */
265 enum Config3Bits {
266     Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */
267     Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
268     Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
269     Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */
270     Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */
271     Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
272     Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */
273     Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
274 };
275 
276 /* Bits in Config4 */
277 enum Config4Bits {
278     LWPTN = (1 << 2),    /* not on 8139, 8139A */
279 };
280 
281 /* Bits in Config5 */
282 enum Config5Bits {
283     Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */
284     Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */
285     Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */
286     Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
287     Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */
288     Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */
289     Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */
290 };
291 
292 enum RxConfigBits {
293     /* rx fifo threshold */
294     RxCfgFIFOShift = 13,
295     RxCfgFIFONone = (7 << RxCfgFIFOShift),
296 
297     /* Max DMA burst */
298     RxCfgDMAShift = 8,
299     RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
300 
301     /* rx ring buffer length */
302     RxCfgRcv8K = 0,
303     RxCfgRcv16K = (1 << 11),
304     RxCfgRcv32K = (1 << 12),
305     RxCfgRcv64K = (1 << 11) | (1 << 12),
306 
307     /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
308     RxNoWrap = (1 << 7),
309 };
310 
311 /* Twister tuning parameters from RealTek.
312    Completely undocumented, but required to tune bad links on some boards. */
313 /*
314 enum CSCRBits {
315     CSCR_LinkOKBit = 0x0400,
316     CSCR_LinkChangeBit = 0x0800,
317     CSCR_LinkStatusBits = 0x0f000,
318     CSCR_LinkDownOffCmd = 0x003c0,
319     CSCR_LinkDownCmd = 0x0f3c0,
320 */
321 enum CSCRBits {
322     CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
323     CSCR_LD  = 1<<9,  /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
324     CSCR_HEART_BIT = 1<<8,  /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
325     CSCR_JBEN = 1<<7,  /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
326     CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
327     CSCR_F_Connect  = 1<<5,  /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
328     CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
329     CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
330     CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
331 };
332 
333 enum Cfg9346Bits {
334     Cfg9346_Lock = 0x00,
335     Cfg9346_Unlock = 0xC0,
336 };
337 
338 typedef enum {
339     CH_8139 = 0,
340     CH_8139_K,
341     CH_8139A,
342     CH_8139A_G,
343     CH_8139B,
344     CH_8130,
345     CH_8139C,
346     CH_8100,
347     CH_8100B_8139D,
348     CH_8101,
349 } chip_t;
350 
351 enum chip_flags {
352     HasHltClk = (1 << 0),
353     HasLWake = (1 << 1),
354 };
355 
356 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
357     (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
358 #define HW_REVID_MASK    HW_REVID(1, 1, 1, 1, 1, 1, 1)
359 
360 #define RTL8139_PCI_REVID_8139      0x10
361 #define RTL8139_PCI_REVID_8139CPLUS 0x20
362 
363 #define RTL8139_PCI_REVID           RTL8139_PCI_REVID_8139CPLUS
364 
365 /* Size is 64 * 16bit words */
366 #define EEPROM_9346_ADDR_BITS 6
367 #define EEPROM_9346_SIZE  (1 << EEPROM_9346_ADDR_BITS)
368 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
369 
370 enum Chip9346Operation
371 {
372     Chip9346_op_mask = 0xc0,          /* 10 zzzzzz */
373     Chip9346_op_read = 0x80,          /* 10 AAAAAA */
374     Chip9346_op_write = 0x40,         /* 01 AAAAAA D(15)..D(0) */
375     Chip9346_op_ext_mask = 0xf0,      /* 11 zzzzzz */
376     Chip9346_op_write_enable = 0x30,  /* 00 11zzzz */
377     Chip9346_op_write_all = 0x10,     /* 00 01zzzz */
378     Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
379 };
380 
381 enum Chip9346Mode
382 {
383     Chip9346_none = 0,
384     Chip9346_enter_command_mode,
385     Chip9346_read_command,
386     Chip9346_data_read,      /* from output register */
387     Chip9346_data_write,     /* to input register, then to contents at specified address */
388     Chip9346_data_write_all, /* to input register, then filling contents */
389 };
390 
391 typedef struct EEprom9346
392 {
393     uint16_t contents[EEPROM_9346_SIZE];
394     int      mode;
395     uint32_t tick;
396     uint8_t  address;
397     uint16_t input;
398     uint16_t output;
399 
400     uint8_t eecs;
401     uint8_t eesk;
402     uint8_t eedi;
403     uint8_t eedo;
404 } EEprom9346;
405 
406 typedef struct RTL8139TallyCounters
407 {
408     /* Tally counters */
409     uint64_t   TxOk;
410     uint64_t   RxOk;
411     uint64_t   TxERR;
412     uint32_t   RxERR;
413     uint16_t   MissPkt;
414     uint16_t   FAE;
415     uint32_t   Tx1Col;
416     uint32_t   TxMCol;
417     uint64_t   RxOkPhy;
418     uint64_t   RxOkBrd;
419     uint32_t   RxOkMul;
420     uint16_t   TxAbt;
421     uint16_t   TxUndrn;
422 } RTL8139TallyCounters;
423 
424 /* Clears all tally counters */
425 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
426 
427 /* Writes tally counters to specified physical memory address */
428 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
429 
430 typedef struct RTL8139State {
431     PCIDevice dev;
432     uint8_t phys[8]; /* mac address */
433     uint8_t mult[8]; /* multicast mask array */
434 
435     uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
436     uint32_t TxAddr[4];   /* TxAddr0 */
437     uint32_t RxBuf;       /* Receive buffer */
438     uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
439     uint32_t RxBufPtr;
440     uint32_t RxBufAddr;
441 
442     uint16_t IntrStatus;
443     uint16_t IntrMask;
444 
445     uint32_t TxConfig;
446     uint32_t RxConfig;
447     uint32_t RxMissed;
448 
449     uint16_t CSCR;
450 
451     uint8_t  Cfg9346;
452     uint8_t  Config0;
453     uint8_t  Config1;
454     uint8_t  Config3;
455     uint8_t  Config4;
456     uint8_t  Config5;
457 
458     uint8_t  clock_enabled;
459     uint8_t  bChipCmdState;
460 
461     uint16_t MultiIntr;
462 
463     uint16_t BasicModeCtrl;
464     uint16_t BasicModeStatus;
465     uint16_t NWayAdvert;
466     uint16_t NWayLPAR;
467     uint16_t NWayExpansion;
468 
469     uint16_t CpCmd;
470     uint8_t  TxThresh;
471 
472     NICState *nic;
473     NICConf conf;
474     int rtl8139_mmio_io_addr;
475 
476     /* C ring mode */
477     uint32_t   currTxDesc;
478 
479     /* C+ mode */
480     uint32_t   cplus_enabled;
481 
482     uint32_t   currCPlusRxDesc;
483     uint32_t   currCPlusTxDesc;
484 
485     uint32_t   RxRingAddrLO;
486     uint32_t   RxRingAddrHI;
487 
488     EEprom9346 eeprom;
489 
490     uint32_t   TCTR;
491     uint32_t   TimerInt;
492     int64_t    TCTR_base;
493 
494     /* Tally counters */
495     RTL8139TallyCounters tally_counters;
496 
497     /* Non-persistent data */
498     uint8_t   *cplus_txbuffer;
499     int        cplus_txbuffer_len;
500     int        cplus_txbuffer_offset;
501 
502     /* PCI interrupt timer */
503     QEMUTimer *timer;
504     int64_t TimerExpire;
505 
506     /* Support migration to/from old versions */
507     int rtl8139_mmio_io_addr_dummy;
508 } RTL8139State;
509 
510 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
511 
prom9346_decode_command(EEprom9346 * eeprom,uint8_t command)512 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
513 {
514     DPRINTF("eeprom command 0x%02x\n", command);
515 
516     switch (command & Chip9346_op_mask)
517     {
518         case Chip9346_op_read:
519         {
520             eeprom->address = command & EEPROM_9346_ADDR_MASK;
521             eeprom->output = eeprom->contents[eeprom->address];
522             eeprom->eedo = 0;
523             eeprom->tick = 0;
524             eeprom->mode = Chip9346_data_read;
525             DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
526                 eeprom->address, eeprom->output);
527         }
528         break;
529 
530         case Chip9346_op_write:
531         {
532             eeprom->address = command & EEPROM_9346_ADDR_MASK;
533             eeprom->input = 0;
534             eeprom->tick = 0;
535             eeprom->mode = Chip9346_none; /* Chip9346_data_write */
536             DPRINTF("eeprom begin write to address 0x%02x\n",
537                 eeprom->address);
538         }
539         break;
540         default:
541             eeprom->mode = Chip9346_none;
542             switch (command & Chip9346_op_ext_mask)
543             {
544                 case Chip9346_op_write_enable:
545                     DPRINTF("eeprom write enabled\n");
546                     break;
547                 case Chip9346_op_write_all:
548                     DPRINTF("eeprom begin write all\n");
549                     break;
550                 case Chip9346_op_write_disable:
551                     DPRINTF("eeprom write disabled\n");
552                     break;
553             }
554             break;
555     }
556 }
557 
prom9346_shift_clock(EEprom9346 * eeprom)558 static void prom9346_shift_clock(EEprom9346 *eeprom)
559 {
560     int bit = eeprom->eedi?1:0;
561 
562     ++ eeprom->tick;
563 
564     DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
565         eeprom->eedo);
566 
567     switch (eeprom->mode)
568     {
569         case Chip9346_enter_command_mode:
570             if (bit)
571             {
572                 eeprom->mode = Chip9346_read_command;
573                 eeprom->tick = 0;
574                 eeprom->input = 0;
575                 DPRINTF("eeprom: +++ synchronized, begin command read\n");
576             }
577             break;
578 
579         case Chip9346_read_command:
580             eeprom->input = (eeprom->input << 1) | (bit & 1);
581             if (eeprom->tick == 8)
582             {
583                 prom9346_decode_command(eeprom, eeprom->input & 0xff);
584             }
585             break;
586 
587         case Chip9346_data_read:
588             eeprom->eedo = (eeprom->output & 0x8000)?1:0;
589             eeprom->output <<= 1;
590             if (eeprom->tick == 16)
591             {
592 #if 1
593         // the FreeBSD drivers (rl and re) don't explicitly toggle
594         // CS between reads (or does setting Cfg9346 to 0 count too?),
595         // so we need to enter wait-for-command state here
596                 eeprom->mode = Chip9346_enter_command_mode;
597                 eeprom->input = 0;
598                 eeprom->tick = 0;
599 
600                 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
601 #else
602         // original behaviour
603                 ++eeprom->address;
604                 eeprom->address &= EEPROM_9346_ADDR_MASK;
605                 eeprom->output = eeprom->contents[eeprom->address];
606                 eeprom->tick = 0;
607 
608                 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
609                     eeprom->address, eeprom->output);
610 #endif
611             }
612             break;
613 
614         case Chip9346_data_write:
615             eeprom->input = (eeprom->input << 1) | (bit & 1);
616             if (eeprom->tick == 16)
617             {
618                 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
619                     eeprom->address, eeprom->input);
620 
621                 eeprom->contents[eeprom->address] = eeprom->input;
622                 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
623                 eeprom->tick = 0;
624                 eeprom->input = 0;
625             }
626             break;
627 
628         case Chip9346_data_write_all:
629             eeprom->input = (eeprom->input << 1) | (bit & 1);
630             if (eeprom->tick == 16)
631             {
632                 int i;
633                 for (i = 0; i < EEPROM_9346_SIZE; i++)
634                 {
635                     eeprom->contents[i] = eeprom->input;
636                 }
637                 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
638 
639                 eeprom->mode = Chip9346_enter_command_mode;
640                 eeprom->tick = 0;
641                 eeprom->input = 0;
642             }
643             break;
644 
645         default:
646             break;
647     }
648 }
649 
prom9346_get_wire(RTL8139State * s)650 static int prom9346_get_wire(RTL8139State *s)
651 {
652     EEprom9346 *eeprom = &s->eeprom;
653     if (!eeprom->eecs)
654         return 0;
655 
656     return eeprom->eedo;
657 }
658 
659 /* FIXME: This should be merged into/replaced by eeprom93xx.c.  */
prom9346_set_wire(RTL8139State * s,int eecs,int eesk,int eedi)660 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
661 {
662     EEprom9346 *eeprom = &s->eeprom;
663     uint8_t old_eecs = eeprom->eecs;
664     uint8_t old_eesk = eeprom->eesk;
665 
666     eeprom->eecs = eecs;
667     eeprom->eesk = eesk;
668     eeprom->eedi = eedi;
669 
670     DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
671         eeprom->eesk, eeprom->eedi, eeprom->eedo);
672 
673     if (!old_eecs && eecs)
674     {
675         /* Synchronize start */
676         eeprom->tick = 0;
677         eeprom->input = 0;
678         eeprom->output = 0;
679         eeprom->mode = Chip9346_enter_command_mode;
680 
681         DPRINTF("=== eeprom: begin access, enter command mode\n");
682     }
683 
684     if (!eecs)
685     {
686         DPRINTF("=== eeprom: end access\n");
687         return;
688     }
689 
690     if (!old_eesk && eesk)
691     {
692         /* SK front rules */
693         prom9346_shift_clock(eeprom);
694     }
695 }
696 
rtl8139_update_irq(RTL8139State * s)697 static void rtl8139_update_irq(RTL8139State *s)
698 {
699     int isr;
700     isr = (s->IntrStatus & s->IntrMask) & 0xffff;
701 
702     DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
703         s->IntrMask);
704 
705     qemu_set_irq(s->dev.irq[0], (isr != 0));
706 }
707 
708 #define POLYNOMIAL 0x04c11db6
709 
710 /* From FreeBSD */
711 /* XXX: optimize */
compute_mcast_idx(const uint8_t * ep)712 static int compute_mcast_idx(const uint8_t *ep)
713 {
714     uint32_t crc;
715     int carry, i, j;
716     uint8_t b;
717 
718     crc = 0xffffffff;
719     for (i = 0; i < 6; i++) {
720         b = *ep++;
721         for (j = 0; j < 8; j++) {
722             carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
723             crc <<= 1;
724             b >>= 1;
725             if (carry)
726                 crc = ((crc ^ POLYNOMIAL) | carry);
727         }
728     }
729     return (crc >> 26);
730 }
731 
rtl8139_RxWrap(RTL8139State * s)732 static int rtl8139_RxWrap(RTL8139State *s)
733 {
734     /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
735     return (s->RxConfig & (1 << 7));
736 }
737 
rtl8139_receiver_enabled(RTL8139State * s)738 static int rtl8139_receiver_enabled(RTL8139State *s)
739 {
740     return s->bChipCmdState & CmdRxEnb;
741 }
742 
rtl8139_transmitter_enabled(RTL8139State * s)743 static int rtl8139_transmitter_enabled(RTL8139State *s)
744 {
745     return s->bChipCmdState & CmdTxEnb;
746 }
747 
rtl8139_cp_receiver_enabled(RTL8139State * s)748 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
749 {
750     return s->CpCmd & CPlusRxEnb;
751 }
752 
rtl8139_cp_transmitter_enabled(RTL8139State * s)753 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
754 {
755     return s->CpCmd & CPlusTxEnb;
756 }
757 
rtl8139_write_buffer(RTL8139State * s,const void * buf,int size)758 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
759 {
760     if (s->RxBufAddr + size > s->RxBufferSize)
761     {
762         int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
763 
764         /* write packet data */
765         if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
766         {
767             DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
768 
769             if (size > wrapped)
770             {
771                 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
772                                            buf, size-wrapped );
773             }
774 
775             /* reset buffer pointer */
776             s->RxBufAddr = 0;
777 
778             cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
779                                        buf + (size-wrapped), wrapped );
780 
781             s->RxBufAddr = wrapped;
782 
783             return;
784         }
785     }
786 
787     /* non-wrapping path or overwrapping enabled */
788     cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
789 
790     s->RxBufAddr += size;
791 }
792 
793 #define MIN_BUF_SIZE 60
rtl8139_addr64(uint32_t low,uint32_t high)794 static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
795 {
796 #if TARGET_PHYS_ADDR_BITS > 32
797     return low | ((target_phys_addr_t)high << 32);
798 #else
799     return low;
800 #endif
801 }
802 
rtl8139_can_receive(VLANClientState * nc)803 static int rtl8139_can_receive(VLANClientState *nc)
804 {
805     RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
806     int avail;
807 
808     /* Receive (drop) packets if card is disabled.  */
809     if (!s->clock_enabled)
810       return 1;
811     if (!rtl8139_receiver_enabled(s))
812       return 1;
813 
814     if (rtl8139_cp_receiver_enabled(s)) {
815         /* ??? Flow control not implemented in c+ mode.
816            This is a hack to work around slirp deficiencies anyway.  */
817         return 1;
818     } else {
819         avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
820                      s->RxBufferSize);
821         return (avail == 0 || avail >= 1514);
822     }
823 }
824 
rtl8139_do_receive(VLANClientState * nc,const uint8_t * buf,size_t size_,int do_interrupt)825 static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
826 {
827     RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
828     int size = size_;
829 
830     uint32_t packet_header = 0;
831 
832     uint8_t buf1[60];
833     static const uint8_t broadcast_macaddr[6] =
834         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
835 
836     DPRINTF(">>> received len=%d\n", size);
837 
838     /* test if board clock is stopped */
839     if (!s->clock_enabled)
840     {
841         DPRINTF("stopped ==========================\n");
842         return -1;
843     }
844 
845     /* first check if receiver is enabled */
846 
847     if (!rtl8139_receiver_enabled(s))
848     {
849         DPRINTF("receiver disabled ================\n");
850         return -1;
851     }
852 
853     /* XXX: check this */
854     if (s->RxConfig & AcceptAllPhys) {
855         /* promiscuous: receive all */
856         DPRINTF(">>> packet received in promiscuous mode\n");
857 
858     } else {
859         if (!memcmp(buf,  broadcast_macaddr, 6)) {
860             /* broadcast address */
861             if (!(s->RxConfig & AcceptBroadcast))
862             {
863                 DPRINTF(">>> broadcast packet rejected\n");
864 
865                 /* update tally counter */
866                 ++s->tally_counters.RxERR;
867 
868                 return size;
869             }
870 
871             packet_header |= RxBroadcast;
872 
873             DPRINTF(">>> broadcast packet received\n");
874 
875             /* update tally counter */
876             ++s->tally_counters.RxOkBrd;
877 
878         } else if (buf[0] & 0x01) {
879             /* multicast */
880             if (!(s->RxConfig & AcceptMulticast))
881             {
882                 DPRINTF(">>> multicast packet rejected\n");
883 
884                 /* update tally counter */
885                 ++s->tally_counters.RxERR;
886 
887                 return size;
888             }
889 
890             int mcast_idx = compute_mcast_idx(buf);
891 
892             if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
893             {
894                 DPRINTF(">>> multicast address mismatch\n");
895 
896                 /* update tally counter */
897                 ++s->tally_counters.RxERR;
898 
899                 return size;
900             }
901 
902             packet_header |= RxMulticast;
903 
904             DPRINTF(">>> multicast packet received\n");
905 
906             /* update tally counter */
907             ++s->tally_counters.RxOkMul;
908 
909         } else if (s->phys[0] == buf[0] &&
910                    s->phys[1] == buf[1] &&
911                    s->phys[2] == buf[2] &&
912                    s->phys[3] == buf[3] &&
913                    s->phys[4] == buf[4] &&
914                    s->phys[5] == buf[5]) {
915             /* match */
916             if (!(s->RxConfig & AcceptMyPhys))
917             {
918                 DPRINTF(">>> rejecting physical address matching packet\n");
919 
920                 /* update tally counter */
921                 ++s->tally_counters.RxERR;
922 
923                 return size;
924             }
925 
926             packet_header |= RxPhysical;
927 
928             DPRINTF(">>> physical address matching packet received\n");
929 
930             /* update tally counter */
931             ++s->tally_counters.RxOkPhy;
932 
933         } else {
934 
935             DPRINTF(">>> unknown packet\n");
936 
937             /* update tally counter */
938             ++s->tally_counters.RxERR;
939 
940             return size;
941         }
942     }
943 
944     /* if too small buffer, then expand it */
945     if (size < MIN_BUF_SIZE) {
946         memcpy(buf1, buf, size);
947         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
948         buf = buf1;
949         size = MIN_BUF_SIZE;
950     }
951 
952     if (rtl8139_cp_receiver_enabled(s))
953     {
954         DPRINTF("in C+ Rx mode ================\n");
955 
956         /* begin C+ receiver mode */
957 
958 /* w0 ownership flag */
959 #define CP_RX_OWN (1<<31)
960 /* w0 end of ring flag */
961 #define CP_RX_EOR (1<<30)
962 /* w0 bits 0...12 : buffer size */
963 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
964 /* w1 tag available flag */
965 #define CP_RX_TAVA (1<<16)
966 /* w1 bits 0...15 : VLAN tag */
967 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
968 /* w2 low  32bit of Rx buffer ptr */
969 /* w3 high 32bit of Rx buffer ptr */
970 
971         int descriptor = s->currCPlusRxDesc;
972         target_phys_addr_t cplus_rx_ring_desc;
973 
974         cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
975         cplus_rx_ring_desc += 16 * descriptor;
976 
977         DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
978             "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
979             s->RxRingAddrLO, cplus_rx_ring_desc);
980 
981         uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
982 
983         cpu_physical_memory_read(cplus_rx_ring_desc,    (uint8_t *)&val, 4);
984         rxdw0 = le32_to_cpu(val);
985         cpu_physical_memory_read(cplus_rx_ring_desc+4,  (uint8_t *)&val, 4);
986         rxdw1 = le32_to_cpu(val);
987         cpu_physical_memory_read(cplus_rx_ring_desc+8,  (uint8_t *)&val, 4);
988         rxbufLO = le32_to_cpu(val);
989         cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
990         rxbufHI = le32_to_cpu(val);
991 
992         DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
993             descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
994 
995         if (!(rxdw0 & CP_RX_OWN))
996         {
997             DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
998                 descriptor);
999 
1000             s->IntrStatus |= RxOverflow;
1001             ++s->RxMissed;
1002 
1003             /* update tally counter */
1004             ++s->tally_counters.RxERR;
1005             ++s->tally_counters.MissPkt;
1006 
1007             rtl8139_update_irq(s);
1008             return size_;
1009         }
1010 
1011         uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1012 
1013         /* TODO: scatter the packet over available receive ring descriptors space */
1014 
1015         if (size+4 > rx_space)
1016         {
1017             DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1018                 descriptor, rx_space, size);
1019 
1020             s->IntrStatus |= RxOverflow;
1021             ++s->RxMissed;
1022 
1023             /* update tally counter */
1024             ++s->tally_counters.RxERR;
1025             ++s->tally_counters.MissPkt;
1026 
1027             rtl8139_update_irq(s);
1028             return size_;
1029         }
1030 
1031         target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1032 
1033         /* receive/copy to target memory */
1034         cpu_physical_memory_write( rx_addr, buf, size );
1035 
1036         if (s->CpCmd & CPlusRxChkSum)
1037         {
1038             /* do some packet checksumming */
1039         }
1040 
1041         /* write checksum */
1042 #if defined (RTL8139_CALCULATE_RXCRC)
1043         val = cpu_to_le32(crc32(0, buf, size));
1044 #else
1045         val = 0;
1046 #endif
1047         cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1048 
1049 /* first segment of received packet flag */
1050 #define CP_RX_STATUS_FS (1<<29)
1051 /* last segment of received packet flag */
1052 #define CP_RX_STATUS_LS (1<<28)
1053 /* multicast packet flag */
1054 #define CP_RX_STATUS_MAR (1<<26)
1055 /* physical-matching packet flag */
1056 #define CP_RX_STATUS_PAM (1<<25)
1057 /* broadcast packet flag */
1058 #define CP_RX_STATUS_BAR (1<<24)
1059 /* runt packet flag */
1060 #define CP_RX_STATUS_RUNT (1<<19)
1061 /* crc error flag */
1062 #define CP_RX_STATUS_CRC (1<<18)
1063 /* IP checksum error flag */
1064 #define CP_RX_STATUS_IPF (1<<15)
1065 /* UDP checksum error flag */
1066 #define CP_RX_STATUS_UDPF (1<<14)
1067 /* TCP checksum error flag */
1068 #define CP_RX_STATUS_TCPF (1<<13)
1069 
1070         /* transfer ownership to target */
1071         rxdw0 &= ~CP_RX_OWN;
1072 
1073         /* set first segment bit */
1074         rxdw0 |= CP_RX_STATUS_FS;
1075 
1076         /* set last segment bit */
1077         rxdw0 |= CP_RX_STATUS_LS;
1078 
1079         /* set received packet type flags */
1080         if (packet_header & RxBroadcast)
1081             rxdw0 |= CP_RX_STATUS_BAR;
1082         if (packet_header & RxMulticast)
1083             rxdw0 |= CP_RX_STATUS_MAR;
1084         if (packet_header & RxPhysical)
1085             rxdw0 |= CP_RX_STATUS_PAM;
1086 
1087         /* set received size */
1088         rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1089         rxdw0 |= (size+4);
1090 
1091         /* reset VLAN tag flag */
1092         rxdw1 &= ~CP_RX_TAVA;
1093 
1094         /* update ring data */
1095         val = cpu_to_le32(rxdw0);
1096         cpu_physical_memory_write(cplus_rx_ring_desc,    (uint8_t *)&val, 4);
1097         val = cpu_to_le32(rxdw1);
1098         cpu_physical_memory_write(cplus_rx_ring_desc+4,  (uint8_t *)&val, 4);
1099 
1100         /* update tally counter */
1101         ++s->tally_counters.RxOk;
1102 
1103         /* seek to next Rx descriptor */
1104         if (rxdw0 & CP_RX_EOR)
1105         {
1106             s->currCPlusRxDesc = 0;
1107         }
1108         else
1109         {
1110             ++s->currCPlusRxDesc;
1111         }
1112 
1113         DPRINTF("done C+ Rx mode ----------------\n");
1114 
1115     }
1116     else
1117     {
1118         DPRINTF("in ring Rx mode ================\n");
1119 
1120         /* begin ring receiver mode */
1121         int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1122 
1123         /* if receiver buffer is empty then avail == 0 */
1124 
1125         if (avail != 0 && size + 8 >= avail)
1126         {
1127             DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1128                 "read 0x%04x === available 0x%04x need 0x%04x\n",
1129                 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
1130 
1131             s->IntrStatus |= RxOverflow;
1132             ++s->RxMissed;
1133             rtl8139_update_irq(s);
1134             return size_;
1135         }
1136 
1137         packet_header |= RxStatusOK;
1138 
1139         packet_header |= (((size+4) << 16) & 0xffff0000);
1140 
1141         /* write header */
1142         uint32_t val = cpu_to_le32(packet_header);
1143 
1144         rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1145 
1146         rtl8139_write_buffer(s, buf, size);
1147 
1148         /* write checksum */
1149 #if defined (RTL8139_CALCULATE_RXCRC)
1150         val = cpu_to_le32(crc32(0, buf, size));
1151 #else
1152         val = 0;
1153 #endif
1154 
1155         rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1156 
1157         /* correct buffer write pointer */
1158         s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1159 
1160         /* now we can signal we have received something */
1161 
1162         DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1163             s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
1164     }
1165 
1166     s->IntrStatus |= RxOK;
1167 
1168     if (do_interrupt)
1169     {
1170         rtl8139_update_irq(s);
1171     }
1172 
1173     return size_;
1174 }
1175 
rtl8139_receive(VLANClientState * nc,const uint8_t * buf,size_t size)1176 static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
1177 {
1178     return rtl8139_do_receive(nc, buf, size, 1);
1179 }
1180 
rtl8139_reset_rxring(RTL8139State * s,uint32_t bufferSize)1181 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1182 {
1183     s->RxBufferSize = bufferSize;
1184     s->RxBufPtr  = 0;
1185     s->RxBufAddr = 0;
1186 }
1187 
rtl8139_reset(DeviceState * d)1188 static void rtl8139_reset(DeviceState *d)
1189 {
1190     RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
1191     int i;
1192 
1193     /* restore MAC address */
1194     memcpy(s->phys, s->conf.macaddr.a, 6);
1195 
1196     /* reset interrupt mask */
1197     s->IntrStatus = 0;
1198     s->IntrMask = 0;
1199 
1200     rtl8139_update_irq(s);
1201 
1202     /* prepare eeprom */
1203     s->eeprom.contents[0] = 0x8129;
1204 #if 1
1205     // PCI vendor and device ID should be mirrored here
1206     s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
1207     s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
1208 #endif
1209 
1210     s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
1211     s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
1212     s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
1213 
1214     /* mark all status registers as owned by host */
1215     for (i = 0; i < 4; ++i)
1216     {
1217         s->TxStatus[i] = TxHostOwns;
1218     }
1219 
1220     s->currTxDesc = 0;
1221     s->currCPlusRxDesc = 0;
1222     s->currCPlusTxDesc = 0;
1223 
1224     s->RxRingAddrLO = 0;
1225     s->RxRingAddrHI = 0;
1226 
1227     s->RxBuf = 0;
1228 
1229     rtl8139_reset_rxring(s, 8192);
1230 
1231     /* ACK the reset */
1232     s->TxConfig = 0;
1233 
1234 #if 0
1235 //    s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139  HasHltClk
1236     s->clock_enabled = 0;
1237 #else
1238     s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1239     s->clock_enabled = 1;
1240 #endif
1241 
1242     s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1243 
1244     /* set initial state data */
1245     s->Config0 = 0x0; /* No boot ROM */
1246     s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1247     s->Config3 = 0x1; /* fast back-to-back compatible */
1248     s->Config5 = 0x0;
1249 
1250     s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1251 
1252     s->CpCmd   = 0x0; /* reset C+ mode */
1253     s->cplus_enabled = 0;
1254 
1255 
1256 //    s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1257 //    s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1258     s->BasicModeCtrl = 0x1000; // autonegotiation
1259 
1260     s->BasicModeStatus  = 0x7809;
1261     //s->BasicModeStatus |= 0x0040; /* UTP medium */
1262     s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1263     s->BasicModeStatus |= 0x0004; /* link is up */
1264 
1265     s->NWayAdvert    = 0x05e1; /* all modes, full duplex */
1266     s->NWayLPAR      = 0x05e1; /* all modes, full duplex */
1267     s->NWayExpansion = 0x0001; /* autonegotiation supported */
1268 
1269     /* also reset timer and disable timer interrupt */
1270     s->TCTR = 0;
1271     s->TimerInt = 0;
1272     s->TCTR_base = 0;
1273 
1274     /* reset tally counters */
1275     RTL8139TallyCounters_clear(&s->tally_counters);
1276 }
1277 
RTL8139TallyCounters_clear(RTL8139TallyCounters * counters)1278 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1279 {
1280     counters->TxOk = 0;
1281     counters->RxOk = 0;
1282     counters->TxERR = 0;
1283     counters->RxERR = 0;
1284     counters->MissPkt = 0;
1285     counters->FAE = 0;
1286     counters->Tx1Col = 0;
1287     counters->TxMCol = 0;
1288     counters->RxOkPhy = 0;
1289     counters->RxOkBrd = 0;
1290     counters->RxOkMul = 0;
1291     counters->TxAbt = 0;
1292     counters->TxUndrn = 0;
1293 }
1294 
RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr,RTL8139TallyCounters * tally_counters)1295 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1296 {
1297     uint16_t val16;
1298     uint32_t val32;
1299     uint64_t val64;
1300 
1301     val64 = cpu_to_le64(tally_counters->TxOk);
1302     cpu_physical_memory_write(tc_addr + 0,    (uint8_t *)&val64, 8);
1303 
1304     val64 = cpu_to_le64(tally_counters->RxOk);
1305     cpu_physical_memory_write(tc_addr + 8,    (uint8_t *)&val64, 8);
1306 
1307     val64 = cpu_to_le64(tally_counters->TxERR);
1308     cpu_physical_memory_write(tc_addr + 16,    (uint8_t *)&val64, 8);
1309 
1310     val32 = cpu_to_le32(tally_counters->RxERR);
1311     cpu_physical_memory_write(tc_addr + 24,    (uint8_t *)&val32, 4);
1312 
1313     val16 = cpu_to_le16(tally_counters->MissPkt);
1314     cpu_physical_memory_write(tc_addr + 28,    (uint8_t *)&val16, 2);
1315 
1316     val16 = cpu_to_le16(tally_counters->FAE);
1317     cpu_physical_memory_write(tc_addr + 30,    (uint8_t *)&val16, 2);
1318 
1319     val32 = cpu_to_le32(tally_counters->Tx1Col);
1320     cpu_physical_memory_write(tc_addr + 32,    (uint8_t *)&val32, 4);
1321 
1322     val32 = cpu_to_le32(tally_counters->TxMCol);
1323     cpu_physical_memory_write(tc_addr + 36,    (uint8_t *)&val32, 4);
1324 
1325     val64 = cpu_to_le64(tally_counters->RxOkPhy);
1326     cpu_physical_memory_write(tc_addr + 40,    (uint8_t *)&val64, 8);
1327 
1328     val64 = cpu_to_le64(tally_counters->RxOkBrd);
1329     cpu_physical_memory_write(tc_addr + 48,    (uint8_t *)&val64, 8);
1330 
1331     val32 = cpu_to_le32(tally_counters->RxOkMul);
1332     cpu_physical_memory_write(tc_addr + 56,    (uint8_t *)&val32, 4);
1333 
1334     val16 = cpu_to_le16(tally_counters->TxAbt);
1335     cpu_physical_memory_write(tc_addr + 60,    (uint8_t *)&val16, 2);
1336 
1337     val16 = cpu_to_le16(tally_counters->TxUndrn);
1338     cpu_physical_memory_write(tc_addr + 62,    (uint8_t *)&val16, 2);
1339 }
1340 
1341 /* Loads values of tally counters from VM state file */
1342 
1343 static const VMStateDescription vmstate_tally_counters = {
1344     .name = "tally_counters",
1345     .version_id = 1,
1346     .minimum_version_id = 1,
1347     .minimum_version_id_old = 1,
1348     .fields      = (VMStateField []) {
1349         VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1350         VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1351         VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1352         VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1353         VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1354         VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1355         VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1356         VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1357         VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1358         VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1359         VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1360         VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1361         VMSTATE_END_OF_LIST()
1362     }
1363 };
1364 
rtl8139_ChipCmd_write(RTL8139State * s,uint32_t val)1365 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1366 {
1367     val &= 0xff;
1368 
1369     DPRINTF("ChipCmd write val=0x%08x\n", val);
1370 
1371     if (val & CmdReset)
1372     {
1373         DPRINTF("ChipCmd reset\n");
1374         rtl8139_reset(&s->dev.qdev);
1375     }
1376     if (val & CmdRxEnb)
1377     {
1378         DPRINTF("ChipCmd enable receiver\n");
1379 
1380         s->currCPlusRxDesc = 0;
1381     }
1382     if (val & CmdTxEnb)
1383     {
1384         DPRINTF("ChipCmd enable transmitter\n");
1385 
1386         s->currCPlusTxDesc = 0;
1387     }
1388 
1389     /* mask unwritable bits */
1390     val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1391 
1392     /* Deassert reset pin before next read */
1393     val &= ~CmdReset;
1394 
1395     s->bChipCmdState = val;
1396 }
1397 
rtl8139_RxBufferEmpty(RTL8139State * s)1398 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1399 {
1400     int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1401 
1402     if (unread != 0)
1403     {
1404         DPRINTF("receiver buffer data available 0x%04x\n", unread);
1405         return 0;
1406     }
1407 
1408     DPRINTF("receiver buffer is empty\n");
1409 
1410     return 1;
1411 }
1412 
rtl8139_ChipCmd_read(RTL8139State * s)1413 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1414 {
1415     uint32_t ret = s->bChipCmdState;
1416 
1417     if (rtl8139_RxBufferEmpty(s))
1418         ret |= RxBufEmpty;
1419 
1420     DPRINTF("ChipCmd read val=0x%04x\n", ret);
1421 
1422     return ret;
1423 }
1424 
rtl8139_CpCmd_write(RTL8139State * s,uint32_t val)1425 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1426 {
1427     val &= 0xffff;
1428 
1429     DPRINTF("C+ command register write(w) val=0x%04x\n", val);
1430 
1431     s->cplus_enabled = 1;
1432 
1433     /* mask unwritable bits */
1434     val = SET_MASKED(val, 0xff84, s->CpCmd);
1435 
1436     s->CpCmd = val;
1437 }
1438 
rtl8139_CpCmd_read(RTL8139State * s)1439 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1440 {
1441     uint32_t ret = s->CpCmd;
1442 
1443     DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
1444 
1445     return ret;
1446 }
1447 
rtl8139_IntrMitigate_write(RTL8139State * s,uint32_t val)1448 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1449 {
1450     DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
1451 }
1452 
rtl8139_IntrMitigate_read(RTL8139State * s)1453 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1454 {
1455     uint32_t ret = 0;
1456 
1457     DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
1458 
1459     return ret;
1460 }
1461 
rtl8139_config_writeable(RTL8139State * s)1462 static int rtl8139_config_writeable(RTL8139State *s)
1463 {
1464     if (s->Cfg9346 & Cfg9346_Unlock)
1465     {
1466         return 1;
1467     }
1468 
1469     DPRINTF("Configuration registers are write-protected\n");
1470 
1471     return 0;
1472 }
1473 
rtl8139_BasicModeCtrl_write(RTL8139State * s,uint32_t val)1474 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1475 {
1476     val &= 0xffff;
1477 
1478     DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
1479 
1480     /* mask unwriteable bits */
1481     uint32_t mask = 0xccff;
1482 
1483     if (1 || !rtl8139_config_writeable(s))
1484     {
1485         /* Speed setting and autonegotiation enable bits are read-only */
1486         mask |= 0x3000;
1487         /* Duplex mode setting is read-only */
1488         mask |= 0x0100;
1489     }
1490 
1491     val = SET_MASKED(val, mask, s->BasicModeCtrl);
1492 
1493     s->BasicModeCtrl = val;
1494 }
1495 
rtl8139_BasicModeCtrl_read(RTL8139State * s)1496 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1497 {
1498     uint32_t ret = s->BasicModeCtrl;
1499 
1500     DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
1501 
1502     return ret;
1503 }
1504 
rtl8139_BasicModeStatus_write(RTL8139State * s,uint32_t val)1505 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1506 {
1507     val &= 0xffff;
1508 
1509     DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
1510 
1511     /* mask unwritable bits */
1512     val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1513 
1514     s->BasicModeStatus = val;
1515 }
1516 
rtl8139_BasicModeStatus_read(RTL8139State * s)1517 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1518 {
1519     uint32_t ret = s->BasicModeStatus;
1520 
1521     DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
1522 
1523     return ret;
1524 }
1525 
rtl8139_Cfg9346_write(RTL8139State * s,uint32_t val)1526 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1527 {
1528     val &= 0xff;
1529 
1530     DPRINTF("Cfg9346 write val=0x%02x\n", val);
1531 
1532     /* mask unwritable bits */
1533     val = SET_MASKED(val, 0x31, s->Cfg9346);
1534 
1535     uint32_t opmode = val & 0xc0;
1536     uint32_t eeprom_val = val & 0xf;
1537 
1538     if (opmode == 0x80) {
1539         /* eeprom access */
1540         int eecs = (eeprom_val & 0x08)?1:0;
1541         int eesk = (eeprom_val & 0x04)?1:0;
1542         int eedi = (eeprom_val & 0x02)?1:0;
1543         prom9346_set_wire(s, eecs, eesk, eedi);
1544     } else if (opmode == 0x40) {
1545         /* Reset.  */
1546         val = 0;
1547         rtl8139_reset(&s->dev.qdev);
1548     }
1549 
1550     s->Cfg9346 = val;
1551 }
1552 
rtl8139_Cfg9346_read(RTL8139State * s)1553 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1554 {
1555     uint32_t ret = s->Cfg9346;
1556 
1557     uint32_t opmode = ret & 0xc0;
1558 
1559     if (opmode == 0x80)
1560     {
1561         /* eeprom access */
1562         int eedo = prom9346_get_wire(s);
1563         if (eedo)
1564         {
1565             ret |=  0x01;
1566         }
1567         else
1568         {
1569             ret &= ~0x01;
1570         }
1571     }
1572 
1573     DPRINTF("Cfg9346 read val=0x%02x\n", ret);
1574 
1575     return ret;
1576 }
1577 
rtl8139_Config0_write(RTL8139State * s,uint32_t val)1578 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1579 {
1580     val &= 0xff;
1581 
1582     DPRINTF("Config0 write val=0x%02x\n", val);
1583 
1584     if (!rtl8139_config_writeable(s))
1585         return;
1586 
1587     /* mask unwritable bits */
1588     val = SET_MASKED(val, 0xf8, s->Config0);
1589 
1590     s->Config0 = val;
1591 }
1592 
rtl8139_Config0_read(RTL8139State * s)1593 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1594 {
1595     uint32_t ret = s->Config0;
1596 
1597     DPRINTF("Config0 read val=0x%02x\n", ret);
1598 
1599     return ret;
1600 }
1601 
rtl8139_Config1_write(RTL8139State * s,uint32_t val)1602 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1603 {
1604     val &= 0xff;
1605 
1606     DPRINTF("Config1 write val=0x%02x\n", val);
1607 
1608     if (!rtl8139_config_writeable(s))
1609         return;
1610 
1611     /* mask unwritable bits */
1612     val = SET_MASKED(val, 0xC, s->Config1);
1613 
1614     s->Config1 = val;
1615 }
1616 
rtl8139_Config1_read(RTL8139State * s)1617 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1618 {
1619     uint32_t ret = s->Config1;
1620 
1621     DPRINTF("Config1 read val=0x%02x\n", ret);
1622 
1623     return ret;
1624 }
1625 
rtl8139_Config3_write(RTL8139State * s,uint32_t val)1626 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1627 {
1628     val &= 0xff;
1629 
1630     DPRINTF("Config3 write val=0x%02x\n", val);
1631 
1632     if (!rtl8139_config_writeable(s))
1633         return;
1634 
1635     /* mask unwritable bits */
1636     val = SET_MASKED(val, 0x8F, s->Config3);
1637 
1638     s->Config3 = val;
1639 }
1640 
rtl8139_Config3_read(RTL8139State * s)1641 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1642 {
1643     uint32_t ret = s->Config3;
1644 
1645     DPRINTF("Config3 read val=0x%02x\n", ret);
1646 
1647     return ret;
1648 }
1649 
rtl8139_Config4_write(RTL8139State * s,uint32_t val)1650 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1651 {
1652     val &= 0xff;
1653 
1654     DPRINTF("Config4 write val=0x%02x\n", val);
1655 
1656     if (!rtl8139_config_writeable(s))
1657         return;
1658 
1659     /* mask unwritable bits */
1660     val = SET_MASKED(val, 0x0a, s->Config4);
1661 
1662     s->Config4 = val;
1663 }
1664 
rtl8139_Config4_read(RTL8139State * s)1665 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1666 {
1667     uint32_t ret = s->Config4;
1668 
1669     DPRINTF("Config4 read val=0x%02x\n", ret);
1670 
1671     return ret;
1672 }
1673 
rtl8139_Config5_write(RTL8139State * s,uint32_t val)1674 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1675 {
1676     val &= 0xff;
1677 
1678     DPRINTF("Config5 write val=0x%02x\n", val);
1679 
1680     /* mask unwritable bits */
1681     val = SET_MASKED(val, 0x80, s->Config5);
1682 
1683     s->Config5 = val;
1684 }
1685 
rtl8139_Config5_read(RTL8139State * s)1686 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1687 {
1688     uint32_t ret = s->Config5;
1689 
1690     DPRINTF("Config5 read val=0x%02x\n", ret);
1691 
1692     return ret;
1693 }
1694 
rtl8139_TxConfig_write(RTL8139State * s,uint32_t val)1695 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1696 {
1697     if (!rtl8139_transmitter_enabled(s))
1698     {
1699         DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
1700         return;
1701     }
1702 
1703     DPRINTF("TxConfig write val=0x%08x\n", val);
1704 
1705     val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1706 
1707     s->TxConfig = val;
1708 }
1709 
rtl8139_TxConfig_writeb(RTL8139State * s,uint32_t val)1710 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1711 {
1712     DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
1713 
1714     uint32_t tc = s->TxConfig;
1715     tc &= 0xFFFFFF00;
1716     tc |= (val & 0x000000FF);
1717     rtl8139_TxConfig_write(s, tc);
1718 }
1719 
rtl8139_TxConfig_read(RTL8139State * s)1720 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1721 {
1722     uint32_t ret = s->TxConfig;
1723 
1724     DPRINTF("TxConfig read val=0x%04x\n", ret);
1725 
1726     return ret;
1727 }
1728 
rtl8139_RxConfig_write(RTL8139State * s,uint32_t val)1729 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1730 {
1731     DPRINTF("RxConfig write val=0x%08x\n", val);
1732 
1733     /* mask unwritable bits */
1734     val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1735 
1736     s->RxConfig = val;
1737 
1738     /* reset buffer size and read/write pointers */
1739     rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1740 
1741     DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
1742 }
1743 
rtl8139_RxConfig_read(RTL8139State * s)1744 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1745 {
1746     uint32_t ret = s->RxConfig;
1747 
1748     DPRINTF("RxConfig read val=0x%08x\n", ret);
1749 
1750     return ret;
1751 }
1752 
rtl8139_transfer_frame(RTL8139State * s,const uint8_t * buf,int size,int do_interrupt)1753 static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1754 {
1755     if (!size)
1756     {
1757         DPRINTF("+++ empty ethernet frame\n");
1758         return;
1759     }
1760 
1761     if (TxLoopBack == (s->TxConfig & TxLoopBack))
1762     {
1763         DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1764         rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
1765     }
1766     else
1767     {
1768         qemu_send_packet(&s->nic->nc, buf, size);
1769     }
1770 }
1771 
rtl8139_transmit_one(RTL8139State * s,int descriptor)1772 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1773 {
1774     if (!rtl8139_transmitter_enabled(s))
1775     {
1776         DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1777             "disabled\n", descriptor);
1778         return 0;
1779     }
1780 
1781     if (s->TxStatus[descriptor] & TxHostOwns)
1782     {
1783         DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1784             "(%08x)\n", descriptor, s->TxStatus[descriptor]);
1785         return 0;
1786     }
1787 
1788     DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
1789 
1790     int txsize = s->TxStatus[descriptor] & 0x1fff;
1791     uint8_t txbuffer[0x2000];
1792 
1793     DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1794         txsize, s->TxAddr[descriptor]);
1795 
1796     cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
1797 
1798     /* Mark descriptor as transferred */
1799     s->TxStatus[descriptor] |= TxHostOwns;
1800     s->TxStatus[descriptor] |= TxStatOK;
1801 
1802     rtl8139_transfer_frame(s, txbuffer, txsize, 0);
1803 
1804     DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1805         descriptor);
1806 
1807     /* update interrupt */
1808     s->IntrStatus |= TxOK;
1809     rtl8139_update_irq(s);
1810 
1811     return 1;
1812 }
1813 
1814 /* structures and macros for task offloading */
1815 typedef struct ip_header
1816 {
1817     uint8_t  ip_ver_len;    /* version and header length */
1818     uint8_t  ip_tos;        /* type of service */
1819     uint16_t ip_len;        /* total length */
1820     uint16_t ip_id;         /* identification */
1821     uint16_t ip_off;        /* fragment offset field */
1822     uint8_t  ip_ttl;        /* time to live */
1823     uint8_t  ip_p;          /* protocol */
1824     uint16_t ip_sum;        /* checksum */
1825     uint32_t ip_src,ip_dst; /* source and dest address */
1826 } ip_header;
1827 
1828 #define IP_HEADER_VERSION_4 4
1829 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1830 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1831 
1832 typedef struct tcp_header
1833 {
1834     uint16_t th_sport;		/* source port */
1835     uint16_t th_dport;		/* destination port */
1836     uint32_t th_seq;			/* sequence number */
1837     uint32_t th_ack;			/* acknowledgement number */
1838     uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1839     uint16_t th_win;			/* window */
1840     uint16_t th_sum;			/* checksum */
1841     uint16_t th_urp;			/* urgent pointer */
1842 } tcp_header;
1843 
1844 typedef struct udp_header
1845 {
1846     uint16_t uh_sport; /* source port */
1847     uint16_t uh_dport; /* destination port */
1848     uint16_t uh_ulen;  /* udp length */
1849     uint16_t uh_sum;   /* udp checksum */
1850 } udp_header;
1851 
1852 typedef struct ip_pseudo_header
1853 {
1854     uint32_t ip_src;
1855     uint32_t ip_dst;
1856     uint8_t  zeros;
1857     uint8_t  ip_proto;
1858     uint16_t ip_payload;
1859 } ip_pseudo_header;
1860 
1861 #define IP_PROTO_TCP 6
1862 #define IP_PROTO_UDP 17
1863 
1864 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1865 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1866 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1867 
1868 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1869 
1870 #define TCP_FLAG_FIN  0x01
1871 #define TCP_FLAG_PUSH 0x08
1872 
1873 /* produces ones' complement sum of data */
ones_complement_sum(uint8_t * data,size_t len)1874 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1875 {
1876     uint32_t result = 0;
1877 
1878     for (; len > 1; data+=2, len-=2)
1879     {
1880         result += *(uint16_t*)data;
1881     }
1882 
1883     /* add the remainder byte */
1884     if (len)
1885     {
1886         uint8_t odd[2] = {*data, 0};
1887         result += *(uint16_t*)odd;
1888     }
1889 
1890     while (result>>16)
1891         result = (result & 0xffff) + (result >> 16);
1892 
1893     return result;
1894 }
1895 
ip_checksum(void * data,size_t len)1896 static uint16_t ip_checksum(void *data, size_t len)
1897 {
1898     return ~ones_complement_sum((uint8_t*)data, len);
1899 }
1900 
rtl8139_cplus_transmit_one(RTL8139State * s)1901 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1902 {
1903     if (!rtl8139_transmitter_enabled(s))
1904     {
1905         DPRINTF("+++ C+ mode: transmitter disabled\n");
1906         return 0;
1907     }
1908 
1909     if (!rtl8139_cp_transmitter_enabled(s))
1910     {
1911         DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
1912         return 0 ;
1913     }
1914 
1915     int descriptor = s->currCPlusTxDesc;
1916 
1917     target_phys_addr_t cplus_tx_ring_desc =
1918         rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1919 
1920     /* Normal priority ring */
1921     cplus_tx_ring_desc += 16 * descriptor;
1922 
1923     DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1924         "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
1925         s->TxAddr[0], cplus_tx_ring_desc);
1926 
1927     uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1928 
1929     cpu_physical_memory_read(cplus_tx_ring_desc,    (uint8_t *)&val, 4);
1930     txdw0 = le32_to_cpu(val);
1931     /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
1932     cpu_physical_memory_read(cplus_tx_ring_desc+4,  (uint8_t *)&val, 4);
1933     txdw1 = le32_to_cpu(val);
1934     cpu_physical_memory_read(cplus_tx_ring_desc+8,  (uint8_t *)&val, 4);
1935     txbufLO = le32_to_cpu(val);
1936     cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1937     txbufHI = le32_to_cpu(val);
1938 
1939     DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1940         txdw0, txdw1, txbufLO, txbufHI);
1941 
1942     /* TODO: the following discard cast should clean clang analyzer output */
1943     (void)txdw1;
1944 
1945 /* w0 ownership flag */
1946 #define CP_TX_OWN (1<<31)
1947 /* w0 end of ring flag */
1948 #define CP_TX_EOR (1<<30)
1949 /* first segment of received packet flag */
1950 #define CP_TX_FS (1<<29)
1951 /* last segment of received packet flag */
1952 #define CP_TX_LS (1<<28)
1953 /* large send packet flag */
1954 #define CP_TX_LGSEN (1<<27)
1955 /* large send MSS mask, bits 16...25 */
1956 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1957 
1958 /* IP checksum offload flag */
1959 #define CP_TX_IPCS (1<<18)
1960 /* UDP checksum offload flag */
1961 #define CP_TX_UDPCS (1<<17)
1962 /* TCP checksum offload flag */
1963 #define CP_TX_TCPCS (1<<16)
1964 
1965 /* w0 bits 0...15 : buffer size */
1966 #define CP_TX_BUFFER_SIZE (1<<16)
1967 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1968 /* w1 tag available flag */
1969 #define CP_RX_TAGC (1<<17)
1970 /* w1 bits 0...15 : VLAN tag */
1971 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1972 /* w2 low  32bit of Rx buffer ptr */
1973 /* w3 high 32bit of Rx buffer ptr */
1974 
1975 /* set after transmission */
1976 /* FIFO underrun flag */
1977 #define CP_TX_STATUS_UNF (1<<25)
1978 /* transmit error summary flag, valid if set any of three below */
1979 #define CP_TX_STATUS_TES (1<<23)
1980 /* out-of-window collision flag */
1981 #define CP_TX_STATUS_OWC (1<<22)
1982 /* link failure flag */
1983 #define CP_TX_STATUS_LNKF (1<<21)
1984 /* excessive collisions flag */
1985 #define CP_TX_STATUS_EXC (1<<20)
1986 
1987     if (!(txdw0 & CP_TX_OWN))
1988     {
1989         DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
1990         return 0 ;
1991     }
1992 
1993     DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
1994 
1995     if (txdw0 & CP_TX_FS)
1996     {
1997         DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
1998             "descriptor\n", descriptor);
1999 
2000         /* reset internal buffer offset */
2001         s->cplus_txbuffer_offset = 0;
2002     }
2003 
2004     int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
2005     target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
2006 
2007     /* make sure we have enough space to assemble the packet */
2008     if (!s->cplus_txbuffer)
2009     {
2010         s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2011         s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
2012         s->cplus_txbuffer_offset = 0;
2013 
2014         DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2015             s->cplus_txbuffer_len);
2016     }
2017 
2018     while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2019     {
2020         s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2021         s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
2022         DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2023                 "length to %d\n", txsize);
2024     }
2025 
2026     if (!s->cplus_txbuffer)
2027     {
2028         /* out of memory */
2029 
2030         DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2031             s->cplus_txbuffer_len);
2032 
2033         /* update tally counter */
2034         ++s->tally_counters.TxERR;
2035         ++s->tally_counters.TxAbt;
2036 
2037         return 0;
2038     }
2039 
2040     /* append more data to the packet */
2041 
2042     DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
2043             DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2044             s->cplus_txbuffer_offset);
2045 
2046     cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2047     s->cplus_txbuffer_offset += txsize;
2048 
2049     /* seek to next Rx descriptor */
2050     if (txdw0 & CP_TX_EOR)
2051     {
2052         s->currCPlusTxDesc = 0;
2053     }
2054     else
2055     {
2056         ++s->currCPlusTxDesc;
2057         if (s->currCPlusTxDesc >= 64)
2058             s->currCPlusTxDesc = 0;
2059     }
2060 
2061     /* transfer ownership to target */
2062     txdw0 &= ~CP_RX_OWN;
2063 
2064     /* reset error indicator bits */
2065     txdw0 &= ~CP_TX_STATUS_UNF;
2066     txdw0 &= ~CP_TX_STATUS_TES;
2067     txdw0 &= ~CP_TX_STATUS_OWC;
2068     txdw0 &= ~CP_TX_STATUS_LNKF;
2069     txdw0 &= ~CP_TX_STATUS_EXC;
2070 
2071     /* update ring data */
2072     val = cpu_to_le32(txdw0);
2073     cpu_physical_memory_write(cplus_tx_ring_desc,    (uint8_t *)&val, 4);
2074     /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
2075 //    val = cpu_to_le32(txdw1);
2076 //    cpu_physical_memory_write(cplus_tx_ring_desc+4,  &val, 4);
2077 
2078     /* Now decide if descriptor being processed is holding the last segment of packet */
2079     if (txdw0 & CP_TX_LS)
2080     {
2081         DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2082             descriptor);
2083 
2084         /* can transfer fully assembled packet */
2085 
2086         uint8_t *saved_buffer  = s->cplus_txbuffer;
2087         int      saved_size    = s->cplus_txbuffer_offset;
2088         int      saved_buffer_len = s->cplus_txbuffer_len;
2089 
2090         /* reset the card space to protect from recursive call */
2091         s->cplus_txbuffer = NULL;
2092         s->cplus_txbuffer_offset = 0;
2093         s->cplus_txbuffer_len = 0;
2094 
2095         if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2096         {
2097             DPRINTF("+++ C+ mode offloaded task checksum\n");
2098 
2099             #define ETH_P_IP	0x0800		/* Internet Protocol packet	*/
2100             #define ETH_HLEN    14
2101             #define ETH_MTU     1500
2102 
2103             /* Large enough for Ethernet and IP headers? */
2104             if (saved_size < ETH_HLEN + sizeof(ip_header)) {
2105                 goto skip_offload;
2106             }
2107 
2108             /* ip packet header */
2109             ip_header *ip = NULL;
2110             int hlen = 0;
2111             uint8_t  ip_protocol = 0;
2112             uint16_t ip_data_len = 0;
2113 
2114             uint8_t *eth_payload_data = NULL;
2115             size_t   eth_payload_len  = 0;
2116 
2117             int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2118             if (proto != ETH_P_IP)
2119             {
2120                 goto skip_offload;
2121             }
2122 
2123             DPRINTF("+++ C+ mode has IP packet\n");
2124 
2125             /* not aligned */
2126             eth_payload_data = saved_buffer + ETH_HLEN;
2127             eth_payload_len  = saved_size   - ETH_HLEN;
2128 
2129             ip = (ip_header*)eth_payload_data;
2130 
2131             if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2132                 DPRINTF("+++ C+ mode packet has bad IP version %d "
2133                     "expected %d\n", IP_HEADER_VERSION(ip),
2134                     IP_HEADER_VERSION_4);
2135                 goto skip_offload;
2136             }
2137 
2138             hlen = IP_HEADER_LENGTH(ip);
2139             if (hlen < sizeof(ip_header) || hlen > eth_payload_len) {
2140                 goto skip_offload;
2141             }
2142 
2143             ip_protocol = ip->ip_p;
2144 
2145             ip_data_len = be16_to_cpu(ip->ip_len);
2146             if (ip_data_len < hlen || ip_data_len > eth_payload_len) {
2147                 goto skip_offload;
2148             }
2149             ip_data_len -= hlen;
2150 
2151             if (txdw0 & CP_TX_IPCS)
2152             {
2153                 DPRINTF("+++ C+ mode need IP checksum\n");
2154 
2155                 ip->ip_sum = 0;
2156                 ip->ip_sum = ip_checksum(ip, hlen);
2157                 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2158                     hlen, ip->ip_sum);
2159             }
2160 
2161             if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2162             {
2163                 /* Large enough for the TCP header? */
2164                 if (ip_data_len < sizeof(tcp_header)) {
2165                     goto skip_offload;
2166                 }
2167 
2168 #if defined UG_RTL8139
2169                 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2170                 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2171                     "frame data %d specified MSS=%d\n", ETH_MTU,
2172                     ip_data_len, saved_size - ETH_HLEN, large_send_mss);
2173 #endif
2174 
2175 
2176                 int tcp_send_offset = 0;
2177                 int send_count = 0;
2178 
2179                 /* maximum IP header length is 60 bytes */
2180                 uint8_t saved_ip_header[60];
2181 
2182                 /* save IP header template; data area is used in tcp checksum calculation */
2183                 memcpy(saved_ip_header, eth_payload_data, hlen);
2184 
2185                 /* a placeholder for checksum calculation routine in tcp case */
2186                 uint8_t *data_to_checksum     = eth_payload_data + hlen - 12;
2187                 //                    size_t   data_to_checksum_len = eth_payload_len  - hlen + 12;
2188 
2189                 /* pointer to TCP header */
2190                 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2191 
2192                 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2193 
2194                 /* Invalid TCP data offset? */
2195                 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) {
2196                     goto skip_offload;
2197                 }
2198 
2199                 /* ETH_MTU = ip header len + tcp header len + payload */
2200                 int tcp_data_len = ip_data_len - tcp_hlen;
2201                 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2202 
2203                 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2204                     "data len %d TCP chunk size %d\n", ip_data_len,
2205                     tcp_hlen, tcp_data_len, tcp_chunk_size);
2206 
2207                 /* note the cycle below overwrites IP header data,
2208                    but restores it from saved_ip_header before sending packet */
2209 
2210                 int is_last_frame = 0;
2211 
2212                 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2213                 {
2214                     uint16_t chunk_size = tcp_chunk_size;
2215 
2216                     /* check if this is the last frame */
2217                     if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2218                     {
2219                         is_last_frame = 1;
2220                         chunk_size = tcp_data_len - tcp_send_offset;
2221                     }
2222 
2223                     DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2224                         be32_to_cpu(p_tcp_hdr->th_seq));
2225 
2226                     /* add 4 TCP pseudoheader fields */
2227                     /* copy IP source and destination fields */
2228                     memcpy(data_to_checksum, saved_ip_header + 12, 8);
2229 
2230                     DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2231                         "packet with %d bytes data\n", tcp_hlen +
2232                         chunk_size);
2233 
2234                     if (tcp_send_offset)
2235                     {
2236                         memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2237                     }
2238 
2239                     /* keep PUSH and FIN flags only for the last frame */
2240                     if (!is_last_frame)
2241                     {
2242                         TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2243                     }
2244 
2245                     /* recalculate TCP checksum */
2246                     ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2247                     p_tcpip_hdr->zeros      = 0;
2248                     p_tcpip_hdr->ip_proto   = IP_PROTO_TCP;
2249                     p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2250 
2251                     p_tcp_hdr->th_sum = 0;
2252 
2253                     int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2254                     DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2255                         tcp_checksum);
2256 
2257                     p_tcp_hdr->th_sum = tcp_checksum;
2258 
2259                     /* restore IP header */
2260                     memcpy(eth_payload_data, saved_ip_header, hlen);
2261 
2262                     /* set IP data length and recalculate IP checksum */
2263                     ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2264 
2265                     /* increment IP id for subsequent frames */
2266                     ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2267 
2268                     ip->ip_sum = 0;
2269                     ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2270                     DPRINTF("+++ C+ mode TSO IP header len=%d "
2271                         "checksum=%04x\n", hlen, ip->ip_sum);
2272 
2273                     int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2274                     DPRINTF("+++ C+ mode TSO transferring packet size "
2275                         "%d\n", tso_send_size);
2276                     rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2277 
2278                     /* add transferred count to TCP sequence number */
2279                     p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2280                     ++send_count;
2281                 }
2282 
2283                 /* Stop sending this frame */
2284                 saved_size = 0;
2285             }
2286             else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2287             {
2288                 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2289 
2290                 /* maximum IP header length is 60 bytes */
2291                 uint8_t saved_ip_header[60];
2292                 memcpy(saved_ip_header, eth_payload_data, hlen);
2293 
2294                 uint8_t *data_to_checksum     = eth_payload_data + hlen - 12;
2295                 //                    size_t   data_to_checksum_len = eth_payload_len  - hlen + 12;
2296 
2297                 /* add 4 TCP pseudoheader fields */
2298                 /* copy IP source and destination fields */
2299                 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2300 
2301                 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2302                 {
2303                     DPRINTF("+++ C+ mode calculating TCP checksum for "
2304                         "packet with %d bytes data\n", ip_data_len);
2305 
2306                     ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2307                     p_tcpip_hdr->zeros      = 0;
2308                     p_tcpip_hdr->ip_proto   = IP_PROTO_TCP;
2309                     p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2310 
2311                     tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2312 
2313                     p_tcp_hdr->th_sum = 0;
2314 
2315                     int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2316                     DPRINTF("+++ C+ mode TCP checksum %04x\n",
2317                         tcp_checksum);
2318 
2319                     p_tcp_hdr->th_sum = tcp_checksum;
2320                 }
2321                 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2322                 {
2323                     DPRINTF("+++ C+ mode calculating UDP checksum for "
2324                         "packet with %d bytes data\n", ip_data_len);
2325 
2326                     ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2327                     p_udpip_hdr->zeros      = 0;
2328                     p_udpip_hdr->ip_proto   = IP_PROTO_UDP;
2329                     p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2330 
2331                     udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2332 
2333                     p_udp_hdr->uh_sum = 0;
2334 
2335                     int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2336                     DPRINTF("+++ C+ mode UDP checksum %04x\n",
2337                         udp_checksum);
2338 
2339                     p_udp_hdr->uh_sum = udp_checksum;
2340                 }
2341 
2342                 /* restore IP header */
2343                 memcpy(eth_payload_data, saved_ip_header, hlen);
2344             }
2345         }
2346 
2347 skip_offload:
2348         /* update tally counter */
2349         ++s->tally_counters.TxOk;
2350 
2351         DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
2352 
2353         rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
2354 
2355         /* restore card space if there was no recursion and reset offset */
2356         if (!s->cplus_txbuffer)
2357         {
2358             s->cplus_txbuffer        = saved_buffer;
2359             s->cplus_txbuffer_len    = saved_buffer_len;
2360             s->cplus_txbuffer_offset = 0;
2361         }
2362         else
2363         {
2364             qemu_free(saved_buffer);
2365         }
2366     }
2367     else
2368     {
2369         DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
2370     }
2371 
2372     return 1;
2373 }
2374 
rtl8139_cplus_transmit(RTL8139State * s)2375 static void rtl8139_cplus_transmit(RTL8139State *s)
2376 {
2377     int txcount = 0;
2378 
2379     while (rtl8139_cplus_transmit_one(s))
2380     {
2381         ++txcount;
2382     }
2383 
2384     /* Mark transfer completed */
2385     if (!txcount)
2386     {
2387         DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2388             s->currCPlusTxDesc);
2389     }
2390     else
2391     {
2392         /* update interrupt status */
2393         s->IntrStatus |= TxOK;
2394         rtl8139_update_irq(s);
2395     }
2396 }
2397 
rtl8139_transmit(RTL8139State * s)2398 static void rtl8139_transmit(RTL8139State *s)
2399 {
2400     int descriptor = s->currTxDesc, txcount = 0;
2401 
2402     /*while*/
2403     if (rtl8139_transmit_one(s, descriptor))
2404     {
2405         ++s->currTxDesc;
2406         s->currTxDesc %= 4;
2407         ++txcount;
2408     }
2409 
2410     /* Mark transfer completed */
2411     if (!txcount)
2412     {
2413         DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2414             s->currTxDesc);
2415     }
2416 }
2417 
rtl8139_TxStatus_write(RTL8139State * s,uint32_t txRegOffset,uint32_t val)2418 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2419 {
2420 
2421     int descriptor = txRegOffset/4;
2422 
2423     /* handle C+ transmit mode register configuration */
2424 
2425     if (s->cplus_enabled)
2426     {
2427         DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2428             "descriptor=%d\n", txRegOffset, val, descriptor);
2429 
2430         /* handle Dump Tally Counters command */
2431         s->TxStatus[descriptor] = val;
2432 
2433         if (descriptor == 0 && (val & 0x8))
2434         {
2435             target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2436 
2437             /* dump tally counters to specified memory location */
2438             RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2439 
2440             /* mark dump completed */
2441             s->TxStatus[0] &= ~0x8;
2442         }
2443 
2444         return;
2445     }
2446 
2447     DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2448         txRegOffset, val, descriptor);
2449 
2450     /* mask only reserved bits */
2451     val &= ~0xff00c000; /* these bits are reset on write */
2452     val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2453 
2454     s->TxStatus[descriptor] = val;
2455 
2456     /* attempt to start transmission */
2457     rtl8139_transmit(s);
2458 }
2459 
rtl8139_TxStatus_read(RTL8139State * s,uint32_t txRegOffset)2460 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2461 {
2462     uint32_t ret = s->TxStatus[txRegOffset/4];
2463 
2464     DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
2465 
2466     return ret;
2467 }
2468 
rtl8139_TSAD_read(RTL8139State * s)2469 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2470 {
2471     uint16_t ret = 0;
2472 
2473     /* Simulate TSAD, it is read only anyway */
2474 
2475     ret = ((s->TxStatus[3] & TxStatOK  )?TSAD_TOK3:0)
2476          |((s->TxStatus[2] & TxStatOK  )?TSAD_TOK2:0)
2477          |((s->TxStatus[1] & TxStatOK  )?TSAD_TOK1:0)
2478          |((s->TxStatus[0] & TxStatOK  )?TSAD_TOK0:0)
2479 
2480          |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2481          |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2482          |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2483          |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2484 
2485          |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2486          |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2487          |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2488          |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2489 
2490          |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2491          |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2492          |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2493          |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2494 
2495 
2496     DPRINTF("TSAD read val=0x%04x\n", ret);
2497 
2498     return ret;
2499 }
2500 
rtl8139_CSCR_read(RTL8139State * s)2501 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2502 {
2503     uint16_t ret = s->CSCR;
2504 
2505     DPRINTF("CSCR read val=0x%04x\n", ret);
2506 
2507     return ret;
2508 }
2509 
rtl8139_TxAddr_write(RTL8139State * s,uint32_t txAddrOffset,uint32_t val)2510 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2511 {
2512     DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
2513 
2514     s->TxAddr[txAddrOffset/4] = val;
2515 }
2516 
rtl8139_TxAddr_read(RTL8139State * s,uint32_t txAddrOffset)2517 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2518 {
2519     uint32_t ret = s->TxAddr[txAddrOffset/4];
2520 
2521     DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
2522 
2523     return ret;
2524 }
2525 
rtl8139_RxBufPtr_write(RTL8139State * s,uint32_t val)2526 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2527 {
2528     DPRINTF("RxBufPtr write val=0x%04x\n", val);
2529 
2530     /* this value is off by 16 */
2531     s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2532 
2533     DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2534         s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
2535 }
2536 
rtl8139_RxBufPtr_read(RTL8139State * s)2537 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2538 {
2539     /* this value is off by 16 */
2540     uint32_t ret = s->RxBufPtr - 0x10;
2541 
2542     DPRINTF("RxBufPtr read val=0x%04x\n", ret);
2543 
2544     return ret;
2545 }
2546 
rtl8139_RxBufAddr_read(RTL8139State * s)2547 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2548 {
2549     /* this value is NOT off by 16 */
2550     uint32_t ret = s->RxBufAddr;
2551 
2552     DPRINTF("RxBufAddr read val=0x%04x\n", ret);
2553 
2554     return ret;
2555 }
2556 
rtl8139_RxBuf_write(RTL8139State * s,uint32_t val)2557 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2558 {
2559     DPRINTF("RxBuf write val=0x%08x\n", val);
2560 
2561     s->RxBuf = val;
2562 
2563     /* may need to reset rxring here */
2564 }
2565 
rtl8139_RxBuf_read(RTL8139State * s)2566 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2567 {
2568     uint32_t ret = s->RxBuf;
2569 
2570     DPRINTF("RxBuf read val=0x%08x\n", ret);
2571 
2572     return ret;
2573 }
2574 
rtl8139_IntrMask_write(RTL8139State * s,uint32_t val)2575 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2576 {
2577     DPRINTF("IntrMask write(w) val=0x%04x\n", val);
2578 
2579     /* mask unwritable bits */
2580     val = SET_MASKED(val, 0x1e00, s->IntrMask);
2581 
2582     s->IntrMask = val;
2583 
2584     rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
2585     rtl8139_update_irq(s);
2586 
2587 }
2588 
rtl8139_IntrMask_read(RTL8139State * s)2589 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2590 {
2591     uint32_t ret = s->IntrMask;
2592 
2593     DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
2594 
2595     return ret;
2596 }
2597 
rtl8139_IntrStatus_write(RTL8139State * s,uint32_t val)2598 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2599 {
2600     DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
2601 
2602 #if 0
2603 
2604     /* writing to ISR has no effect */
2605 
2606     return;
2607 
2608 #else
2609     uint16_t newStatus = s->IntrStatus & ~val;
2610 
2611     /* mask unwritable bits */
2612     newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2613 
2614     /* writing 1 to interrupt status register bit clears it */
2615     s->IntrStatus = 0;
2616     rtl8139_update_irq(s);
2617 
2618     s->IntrStatus = newStatus;
2619     /*
2620      * Computing if we miss an interrupt here is not that correct but
2621      * considered that we should have had already an interrupt
2622      * and probably emulated is slower is better to assume this resetting was
2623      * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2624      */
2625     rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
2626     rtl8139_update_irq(s);
2627 
2628 #endif
2629 }
2630 
rtl8139_IntrStatus_read(RTL8139State * s)2631 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2632 {
2633     rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
2634 
2635     uint32_t ret = s->IntrStatus;
2636 
2637     DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
2638 
2639 #if 0
2640 
2641     /* reading ISR clears all interrupts */
2642     s->IntrStatus = 0;
2643 
2644     rtl8139_update_irq(s);
2645 
2646 #endif
2647 
2648     return ret;
2649 }
2650 
rtl8139_MultiIntr_write(RTL8139State * s,uint32_t val)2651 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2652 {
2653     DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
2654 
2655     /* mask unwriteable bits */
2656     val = SET_MASKED(val, 0xf000, s->MultiIntr);
2657 
2658     s->MultiIntr = val;
2659 }
2660 
rtl8139_MultiIntr_read(RTL8139State * s)2661 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2662 {
2663     uint32_t ret = s->MultiIntr;
2664 
2665     DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
2666 
2667     return ret;
2668 }
2669 
rtl8139_io_writeb(void * opaque,uint8_t addr,uint32_t val)2670 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2671 {
2672     RTL8139State *s = opaque;
2673 
2674     addr &= 0xff;
2675 
2676     switch (addr)
2677     {
2678         case MAC0 ... MAC0+5:
2679             s->phys[addr - MAC0] = val;
2680             break;
2681         case MAC0+6 ... MAC0+7:
2682             /* reserved */
2683             break;
2684         case MAR0 ... MAR0+7:
2685             s->mult[addr - MAR0] = val;
2686             break;
2687         case ChipCmd:
2688             rtl8139_ChipCmd_write(s, val);
2689             break;
2690         case Cfg9346:
2691             rtl8139_Cfg9346_write(s, val);
2692             break;
2693         case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2694             rtl8139_TxConfig_writeb(s, val);
2695             break;
2696         case Config0:
2697             rtl8139_Config0_write(s, val);
2698             break;
2699         case Config1:
2700             rtl8139_Config1_write(s, val);
2701             break;
2702         case Config3:
2703             rtl8139_Config3_write(s, val);
2704             break;
2705         case Config4:
2706             rtl8139_Config4_write(s, val);
2707             break;
2708         case Config5:
2709             rtl8139_Config5_write(s, val);
2710             break;
2711         case MediaStatus:
2712             /* ignore */
2713             DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2714                 val);
2715             break;
2716 
2717         case HltClk:
2718             DPRINTF("HltClk write val=0x%08x\n", val);
2719             if (val == 'R')
2720             {
2721                 s->clock_enabled = 1;
2722             }
2723             else if (val == 'H')
2724             {
2725                 s->clock_enabled = 0;
2726             }
2727             break;
2728 
2729         case TxThresh:
2730             DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
2731             s->TxThresh = val;
2732             break;
2733 
2734         case TxPoll:
2735             DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
2736             if (val & (1 << 7))
2737             {
2738                 DPRINTF("C+ TxPoll high priority transmission (not "
2739                     "implemented)\n");
2740                 //rtl8139_cplus_transmit(s);
2741             }
2742             if (val & (1 << 6))
2743             {
2744                 DPRINTF("C+ TxPoll normal priority transmission\n");
2745                 rtl8139_cplus_transmit(s);
2746             }
2747 
2748             break;
2749 
2750         default:
2751             DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2752                 val);
2753             break;
2754     }
2755 }
2756 
rtl8139_io_writew(void * opaque,uint8_t addr,uint32_t val)2757 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2758 {
2759     RTL8139State *s = opaque;
2760 
2761     addr &= 0xfe;
2762 
2763     switch (addr)
2764     {
2765         case IntrMask:
2766             rtl8139_IntrMask_write(s, val);
2767             break;
2768 
2769         case IntrStatus:
2770             rtl8139_IntrStatus_write(s, val);
2771             break;
2772 
2773         case MultiIntr:
2774             rtl8139_MultiIntr_write(s, val);
2775             break;
2776 
2777         case RxBufPtr:
2778             rtl8139_RxBufPtr_write(s, val);
2779             break;
2780 
2781         case BasicModeCtrl:
2782             rtl8139_BasicModeCtrl_write(s, val);
2783             break;
2784         case BasicModeStatus:
2785             rtl8139_BasicModeStatus_write(s, val);
2786             break;
2787         case NWayAdvert:
2788             DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
2789             s->NWayAdvert = val;
2790             break;
2791         case NWayLPAR:
2792             DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
2793             break;
2794         case NWayExpansion:
2795             DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
2796             s->NWayExpansion = val;
2797             break;
2798 
2799         case CpCmd:
2800             rtl8139_CpCmd_write(s, val);
2801             break;
2802 
2803         case IntrMitigate:
2804             rtl8139_IntrMitigate_write(s, val);
2805             break;
2806 
2807         default:
2808             DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2809                 addr, val);
2810 
2811             rtl8139_io_writeb(opaque, addr, val & 0xff);
2812             rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2813             break;
2814     }
2815 }
2816 
rtl8139_set_next_tctr_time(RTL8139State * s,int64_t current_time)2817 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2818 {
2819     int64_t pci_time, next_time;
2820     uint32_t low_pci;
2821 
2822     DPRINTF("entered rtl8139_set_next_tctr_time\n");
2823 
2824     if (s->TimerExpire && current_time >= s->TimerExpire) {
2825         s->IntrStatus |= PCSTimeout;
2826         rtl8139_update_irq(s);
2827     }
2828 
2829     /* Set QEMU timer only if needed that is
2830      * - TimerInt <> 0 (we have a timer)
2831      * - mask = 1 (we want an interrupt timer)
2832      * - irq = 0  (irq is not already active)
2833      * If any of above change we need to compute timer again
2834      * Also we must check if timer is passed without QEMU timer
2835      */
2836     s->TimerExpire = 0;
2837     if (!s->TimerInt) {
2838         return;
2839     }
2840 
2841     pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2842                                 get_ticks_per_sec());
2843     low_pci = pci_time & 0xffffffff;
2844     pci_time = pci_time - low_pci + s->TimerInt;
2845     if (low_pci >= s->TimerInt) {
2846         pci_time += 0x100000000LL;
2847     }
2848     next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2849                                                 PCI_FREQUENCY);
2850     s->TimerExpire = next_time;
2851 
2852     if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2853         qemu_mod_timer(s->timer, next_time);
2854     }
2855 }
2856 
rtl8139_io_writel(void * opaque,uint8_t addr,uint32_t val)2857 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2858 {
2859     RTL8139State *s = opaque;
2860 
2861     addr &= 0xfc;
2862 
2863     switch (addr)
2864     {
2865         case RxMissed:
2866             DPRINTF("RxMissed clearing on write\n");
2867             s->RxMissed = 0;
2868             break;
2869 
2870         case TxConfig:
2871             rtl8139_TxConfig_write(s, val);
2872             break;
2873 
2874         case RxConfig:
2875             rtl8139_RxConfig_write(s, val);
2876             break;
2877 
2878         case TxStatus0 ... TxStatus0+4*4-1:
2879             rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2880             break;
2881 
2882         case TxAddr0 ... TxAddr0+4*4-1:
2883             rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2884             break;
2885 
2886         case RxBuf:
2887             rtl8139_RxBuf_write(s, val);
2888             break;
2889 
2890         case RxRingAddrLO:
2891             DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
2892             s->RxRingAddrLO = val;
2893             break;
2894 
2895         case RxRingAddrHI:
2896             DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
2897             s->RxRingAddrHI = val;
2898             break;
2899 
2900         case Timer:
2901             DPRINTF("TCTR Timer reset on write\n");
2902             s->TCTR_base = qemu_get_clock(vm_clock);
2903             rtl8139_set_next_tctr_time(s, s->TCTR_base);
2904             break;
2905 
2906         case FlashReg:
2907             DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
2908             if (s->TimerInt != val) {
2909                 s->TimerInt = val;
2910                 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
2911             }
2912             break;
2913 
2914         default:
2915             DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2916                 addr, val);
2917             rtl8139_io_writeb(opaque, addr, val & 0xff);
2918             rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2919             rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2920             rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2921             break;
2922     }
2923 }
2924 
rtl8139_io_readb(void * opaque,uint8_t addr)2925 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2926 {
2927     RTL8139State *s = opaque;
2928     int ret;
2929 
2930     addr &= 0xff;
2931 
2932     switch (addr)
2933     {
2934         case MAC0 ... MAC0+5:
2935             ret = s->phys[addr - MAC0];
2936             break;
2937         case MAC0+6 ... MAC0+7:
2938             ret = 0;
2939             break;
2940         case MAR0 ... MAR0+7:
2941             ret = s->mult[addr - MAR0];
2942             break;
2943         case ChipCmd:
2944             ret = rtl8139_ChipCmd_read(s);
2945             break;
2946         case Cfg9346:
2947             ret = rtl8139_Cfg9346_read(s);
2948             break;
2949         case Config0:
2950             ret = rtl8139_Config0_read(s);
2951             break;
2952         case Config1:
2953             ret = rtl8139_Config1_read(s);
2954             break;
2955         case Config3:
2956             ret = rtl8139_Config3_read(s);
2957             break;
2958         case Config4:
2959             ret = rtl8139_Config4_read(s);
2960             break;
2961         case Config5:
2962             ret = rtl8139_Config5_read(s);
2963             break;
2964 
2965         case MediaStatus:
2966             ret = 0xd0;
2967             DPRINTF("MediaStatus read 0x%x\n", ret);
2968             break;
2969 
2970         case HltClk:
2971             ret = s->clock_enabled;
2972             DPRINTF("HltClk read 0x%x\n", ret);
2973             break;
2974 
2975         case PCIRevisionID:
2976             ret = RTL8139_PCI_REVID;
2977             DPRINTF("PCI Revision ID read 0x%x\n", ret);
2978             break;
2979 
2980         case TxThresh:
2981             ret = s->TxThresh;
2982             DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
2983             break;
2984 
2985         case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2986             ret = s->TxConfig >> 24;
2987             DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
2988             break;
2989 
2990         default:
2991             DPRINTF("not implemented read(b) addr=0x%x\n", addr);
2992             ret = 0;
2993             break;
2994     }
2995 
2996     return ret;
2997 }
2998 
rtl8139_io_readw(void * opaque,uint8_t addr)2999 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3000 {
3001     RTL8139State *s = opaque;
3002     uint32_t ret;
3003 
3004     addr &= 0xfe; /* mask lower bit */
3005 
3006     switch (addr)
3007     {
3008         case IntrMask:
3009             ret = rtl8139_IntrMask_read(s);
3010             break;
3011 
3012         case IntrStatus:
3013             ret = rtl8139_IntrStatus_read(s);
3014             break;
3015 
3016         case MultiIntr:
3017             ret = rtl8139_MultiIntr_read(s);
3018             break;
3019 
3020         case RxBufPtr:
3021             ret = rtl8139_RxBufPtr_read(s);
3022             break;
3023 
3024         case RxBufAddr:
3025             ret = rtl8139_RxBufAddr_read(s);
3026             break;
3027 
3028         case BasicModeCtrl:
3029             ret = rtl8139_BasicModeCtrl_read(s);
3030             break;
3031         case BasicModeStatus:
3032             ret = rtl8139_BasicModeStatus_read(s);
3033             break;
3034         case NWayAdvert:
3035             ret = s->NWayAdvert;
3036             DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
3037             break;
3038         case NWayLPAR:
3039             ret = s->NWayLPAR;
3040             DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
3041             break;
3042         case NWayExpansion:
3043             ret = s->NWayExpansion;
3044             DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
3045             break;
3046 
3047         case CpCmd:
3048             ret = rtl8139_CpCmd_read(s);
3049             break;
3050 
3051         case IntrMitigate:
3052             ret = rtl8139_IntrMitigate_read(s);
3053             break;
3054 
3055         case TxSummary:
3056             ret = rtl8139_TSAD_read(s);
3057             break;
3058 
3059         case CSCR:
3060             ret = rtl8139_CSCR_read(s);
3061             break;
3062 
3063         default:
3064             DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
3065 
3066             ret  = rtl8139_io_readb(opaque, addr);
3067             ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3068 
3069             DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
3070             break;
3071     }
3072 
3073     return ret;
3074 }
3075 
rtl8139_io_readl(void * opaque,uint8_t addr)3076 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3077 {
3078     RTL8139State *s = opaque;
3079     uint32_t ret;
3080 
3081     addr &= 0xfc; /* also mask low 2 bits */
3082 
3083     switch (addr)
3084     {
3085         case RxMissed:
3086             ret = s->RxMissed;
3087 
3088             DPRINTF("RxMissed read val=0x%08x\n", ret);
3089             break;
3090 
3091         case TxConfig:
3092             ret = rtl8139_TxConfig_read(s);
3093             break;
3094 
3095         case RxConfig:
3096             ret = rtl8139_RxConfig_read(s);
3097             break;
3098 
3099         case TxStatus0 ... TxStatus0+4*4-1:
3100             ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3101             break;
3102 
3103         case TxAddr0 ... TxAddr0+4*4-1:
3104             ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3105             break;
3106 
3107         case RxBuf:
3108             ret = rtl8139_RxBuf_read(s);
3109             break;
3110 
3111         case RxRingAddrLO:
3112             ret = s->RxRingAddrLO;
3113             DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
3114             break;
3115 
3116         case RxRingAddrHI:
3117             ret = s->RxRingAddrHI;
3118             DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
3119             break;
3120 
3121         case Timer:
3122             ret = muldiv64(qemu_get_clock(vm_clock) - s->TCTR_base,
3123                            PCI_FREQUENCY, get_ticks_per_sec());
3124             DPRINTF("TCTR Timer read val=0x%08x\n", ret);
3125             break;
3126 
3127         case FlashReg:
3128             ret = s->TimerInt;
3129             DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
3130             break;
3131 
3132         default:
3133             DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
3134 
3135             ret  = rtl8139_io_readb(opaque, addr);
3136             ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3137             ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3138             ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3139 
3140             DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
3141             break;
3142     }
3143 
3144     return ret;
3145 }
3146 
3147 /* */
3148 
rtl8139_ioport_writeb(void * opaque,uint32_t addr,uint32_t val)3149 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3150 {
3151     rtl8139_io_writeb(opaque, addr & 0xFF, val);
3152 }
3153 
rtl8139_ioport_writew(void * opaque,uint32_t addr,uint32_t val)3154 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3155 {
3156     rtl8139_io_writew(opaque, addr & 0xFF, val);
3157 }
3158 
rtl8139_ioport_writel(void * opaque,uint32_t addr,uint32_t val)3159 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3160 {
3161     rtl8139_io_writel(opaque, addr & 0xFF, val);
3162 }
3163 
rtl8139_ioport_readb(void * opaque,uint32_t addr)3164 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3165 {
3166     return rtl8139_io_readb(opaque, addr & 0xFF);
3167 }
3168 
rtl8139_ioport_readw(void * opaque,uint32_t addr)3169 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3170 {
3171     return rtl8139_io_readw(opaque, addr & 0xFF);
3172 }
3173 
rtl8139_ioport_readl(void * opaque,uint32_t addr)3174 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3175 {
3176     return rtl8139_io_readl(opaque, addr & 0xFF);
3177 }
3178 
3179 /* */
3180 
rtl8139_mmio_writeb(void * opaque,target_phys_addr_t addr,uint32_t val)3181 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3182 {
3183     rtl8139_io_writeb(opaque, addr & 0xFF, val);
3184 }
3185 
rtl8139_mmio_writew(void * opaque,target_phys_addr_t addr,uint32_t val)3186 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3187 {
3188     rtl8139_io_writew(opaque, addr & 0xFF, val);
3189 }
3190 
rtl8139_mmio_writel(void * opaque,target_phys_addr_t addr,uint32_t val)3191 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3192 {
3193     rtl8139_io_writel(opaque, addr & 0xFF, val);
3194 }
3195 
rtl8139_mmio_readb(void * opaque,target_phys_addr_t addr)3196 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3197 {
3198     return rtl8139_io_readb(opaque, addr & 0xFF);
3199 }
3200 
rtl8139_mmio_readw(void * opaque,target_phys_addr_t addr)3201 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3202 {
3203     uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3204     return val;
3205 }
3206 
rtl8139_mmio_readl(void * opaque,target_phys_addr_t addr)3207 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3208 {
3209     uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3210     return val;
3211 }
3212 
rtl8139_post_load(void * opaque,int version_id)3213 static int rtl8139_post_load(void *opaque, int version_id)
3214 {
3215     RTL8139State* s = opaque;
3216     rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
3217     if (version_id < 4) {
3218         s->cplus_enabled = s->CpCmd != 0;
3219     }
3220 
3221     return 0;
3222 }
3223 
rtl8139_hotplug_ready_needed(void * opaque)3224 static bool rtl8139_hotplug_ready_needed(void *opaque)
3225 {
3226     return qdev_machine_modified();
3227 }
3228 
3229 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3230     .name = "rtl8139/hotplug_ready",
3231     .version_id = 1,
3232     .minimum_version_id = 1,
3233     .minimum_version_id_old = 1,
3234     .fields      = (VMStateField []) {
3235         VMSTATE_END_OF_LIST()
3236     }
3237 };
3238 
rtl8139_pre_save(void * opaque)3239 static void rtl8139_pre_save(void *opaque)
3240 {
3241     RTL8139State* s = opaque;
3242     int64_t current_time = qemu_get_clock(vm_clock);
3243 
3244     /* set IntrStatus correctly */
3245     rtl8139_set_next_tctr_time(s, current_time);
3246     s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3247                        get_ticks_per_sec());
3248     s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr;
3249 }
3250 
3251 static const VMStateDescription vmstate_rtl8139 = {
3252     .name = "rtl8139",
3253     .version_id = 4,
3254     .minimum_version_id = 3,
3255     .minimum_version_id_old = 3,
3256     .post_load = rtl8139_post_load,
3257     .pre_save  = rtl8139_pre_save,
3258     .fields      = (VMStateField []) {
3259         VMSTATE_PCI_DEVICE(dev, RTL8139State),
3260         VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3261         VMSTATE_BUFFER(mult, RTL8139State),
3262         VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3263         VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3264 
3265         VMSTATE_UINT32(RxBuf, RTL8139State),
3266         VMSTATE_UINT32(RxBufferSize, RTL8139State),
3267         VMSTATE_UINT32(RxBufPtr, RTL8139State),
3268         VMSTATE_UINT32(RxBufAddr, RTL8139State),
3269 
3270         VMSTATE_UINT16(IntrStatus, RTL8139State),
3271         VMSTATE_UINT16(IntrMask, RTL8139State),
3272 
3273         VMSTATE_UINT32(TxConfig, RTL8139State),
3274         VMSTATE_UINT32(RxConfig, RTL8139State),
3275         VMSTATE_UINT32(RxMissed, RTL8139State),
3276         VMSTATE_UINT16(CSCR, RTL8139State),
3277 
3278         VMSTATE_UINT8(Cfg9346, RTL8139State),
3279         VMSTATE_UINT8(Config0, RTL8139State),
3280         VMSTATE_UINT8(Config1, RTL8139State),
3281         VMSTATE_UINT8(Config3, RTL8139State),
3282         VMSTATE_UINT8(Config4, RTL8139State),
3283         VMSTATE_UINT8(Config5, RTL8139State),
3284 
3285         VMSTATE_UINT8(clock_enabled, RTL8139State),
3286         VMSTATE_UINT8(bChipCmdState, RTL8139State),
3287 
3288         VMSTATE_UINT16(MultiIntr, RTL8139State),
3289 
3290         VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3291         VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3292         VMSTATE_UINT16(NWayAdvert, RTL8139State),
3293         VMSTATE_UINT16(NWayLPAR, RTL8139State),
3294         VMSTATE_UINT16(NWayExpansion, RTL8139State),
3295 
3296         VMSTATE_UINT16(CpCmd, RTL8139State),
3297         VMSTATE_UINT8(TxThresh, RTL8139State),
3298 
3299         VMSTATE_UNUSED(4),
3300         VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3301         VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3302 
3303         VMSTATE_UINT32(currTxDesc, RTL8139State),
3304         VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3305         VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3306         VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3307         VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3308 
3309         VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3310         VMSTATE_INT32(eeprom.mode, RTL8139State),
3311         VMSTATE_UINT32(eeprom.tick, RTL8139State),
3312         VMSTATE_UINT8(eeprom.address, RTL8139State),
3313         VMSTATE_UINT16(eeprom.input, RTL8139State),
3314         VMSTATE_UINT16(eeprom.output, RTL8139State),
3315 
3316         VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3317         VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3318         VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3319         VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3320 
3321         VMSTATE_UINT32(TCTR, RTL8139State),
3322         VMSTATE_UINT32(TimerInt, RTL8139State),
3323         VMSTATE_INT64(TCTR_base, RTL8139State),
3324 
3325         VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3326                        vmstate_tally_counters, RTL8139TallyCounters),
3327 
3328         VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3329         VMSTATE_END_OF_LIST()
3330     },
3331     .subsections = (VMStateSubsection []) {
3332         {
3333             .vmsd = &vmstate_rtl8139_hotplug_ready,
3334             .needed = rtl8139_hotplug_ready_needed,
3335         }, {
3336             /* empty */
3337         }
3338     }
3339 };
3340 
3341 /***********************************************************/
3342 /* PCI RTL8139 definitions */
3343 
rtl8139_mmio_map(PCIDevice * pci_dev,int region_num,pcibus_t addr,pcibus_t size,int type)3344 static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
3345                        pcibus_t addr, pcibus_t size, int type)
3346 {
3347     RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
3348 
3349     cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3350 }
3351 
rtl8139_ioport_map(PCIDevice * pci_dev,int region_num,pcibus_t addr,pcibus_t size,int type)3352 static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3353                        pcibus_t addr, pcibus_t size, int type)
3354 {
3355     RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
3356 
3357     register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3358     register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb,  s);
3359 
3360     register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3361     register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw,  s);
3362 
3363     register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3364     register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl,  s);
3365 }
3366 
3367 static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
3368     rtl8139_mmio_readb,
3369     rtl8139_mmio_readw,
3370     rtl8139_mmio_readl,
3371 };
3372 
3373 static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
3374     rtl8139_mmio_writeb,
3375     rtl8139_mmio_writew,
3376     rtl8139_mmio_writel,
3377 };
3378 
rtl8139_timer(void * opaque)3379 static void rtl8139_timer(void *opaque)
3380 {
3381     RTL8139State *s = opaque;
3382 
3383     if (!s->clock_enabled)
3384     {
3385         DPRINTF(">>> timer: clock is not running\n");
3386         return;
3387     }
3388 
3389     s->IntrStatus |= PCSTimeout;
3390     rtl8139_update_irq(s);
3391     rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
3392 }
3393 
rtl8139_cleanup(VLANClientState * nc)3394 static void rtl8139_cleanup(VLANClientState *nc)
3395 {
3396     RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
3397 
3398     s->nic = NULL;
3399 }
3400 
pci_rtl8139_uninit(PCIDevice * dev)3401 static int pci_rtl8139_uninit(PCIDevice *dev)
3402 {
3403     RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3404 
3405     cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
3406     if (s->cplus_txbuffer) {
3407         qemu_free(s->cplus_txbuffer);
3408         s->cplus_txbuffer = NULL;
3409     }
3410     qemu_del_timer(s->timer);
3411     qemu_free_timer(s->timer);
3412     qemu_del_vlan_client(&s->nic->nc);
3413     return 0;
3414 }
3415 
3416 static NetClientInfo net_rtl8139_info = {
3417     .type = NET_CLIENT_TYPE_NIC,
3418     .size = sizeof(NICState),
3419     .can_receive = rtl8139_can_receive,
3420     .receive = rtl8139_receive,
3421     .cleanup = rtl8139_cleanup,
3422 };
3423 
pci_rtl8139_init(PCIDevice * dev)3424 static int pci_rtl8139_init(PCIDevice *dev)
3425 {
3426     RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
3427     uint8_t *pci_conf;
3428 
3429     pci_conf = s->dev.config;
3430     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3431     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
3432     pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3433     pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
3434     pci_conf[PCI_INTERRUPT_PIN] = 1;    /* interrupt pin 0 */
3435     /* TODO: start of capability list, but no capability
3436      * list bit in status register, and offset 0xdc seems unused. */
3437     pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3438 
3439     /* I/O handler for memory-mapped I/O */
3440     s->