xref: /illumos-kvm-cmd/hw/pxa2xx.c (revision 68396ea9)
1 /*
2  * Intel XScale PXA255/270 processor support.
3  *
4  * Copyright (c) 2006 Openedhand Ltd.
5  * Written by Andrzej Zaborowski <balrog@zabor.org>
6  *
7  * This code is licenced under the GPL.
8  */
9 
10 #include "sysbus.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "ssi.h"
16 #include "qemu-timer.h"
17 #include "qemu-char.h"
18 #include "blockdev.h"
19 
20 static struct {
21     target_phys_addr_t io_base;
22     int irqn;
23 } pxa255_serial[] = {
24     { 0x40100000, PXA2XX_PIC_FFUART },
25     { 0x40200000, PXA2XX_PIC_BTUART },
26     { 0x40700000, PXA2XX_PIC_STUART },
27     { 0x41600000, PXA25X_PIC_HWUART },
28     { 0, 0 }
29 }, pxa270_serial[] = {
30     { 0x40100000, PXA2XX_PIC_FFUART },
31     { 0x40200000, PXA2XX_PIC_BTUART },
32     { 0x40700000, PXA2XX_PIC_STUART },
33     { 0, 0 }
34 };
35 
36 typedef struct PXASSPDef {
37     target_phys_addr_t io_base;
38     int irqn;
39 } PXASSPDef;
40 
41 #if 0
42 static PXASSPDef pxa250_ssp[] = {
43     { 0x41000000, PXA2XX_PIC_SSP },
44     { 0, 0 }
45 };
46 #endif
47 
48 static PXASSPDef pxa255_ssp[] = {
49     { 0x41000000, PXA2XX_PIC_SSP },
50     { 0x41400000, PXA25X_PIC_NSSP },
51     { 0, 0 }
52 };
53 
54 #if 0
55 static PXASSPDef pxa26x_ssp[] = {
56     { 0x41000000, PXA2XX_PIC_SSP },
57     { 0x41400000, PXA25X_PIC_NSSP },
58     { 0x41500000, PXA26X_PIC_ASSP },
59     { 0, 0 }
60 };
61 #endif
62 
63 static PXASSPDef pxa27x_ssp[] = {
64     { 0x41000000, PXA2XX_PIC_SSP },
65     { 0x41700000, PXA27X_PIC_SSP2 },
66     { 0x41900000, PXA2XX_PIC_SSP3 },
67     { 0, 0 }
68 };
69 
70 #define PMCR	0x00	/* Power Manager Control register */
71 #define PSSR	0x04	/* Power Manager Sleep Status register */
72 #define PSPR	0x08	/* Power Manager Scratch-Pad register */
73 #define PWER	0x0c	/* Power Manager Wake-Up Enable register */
74 #define PRER	0x10	/* Power Manager Rising-Edge Detect Enable register */
75 #define PFER	0x14	/* Power Manager Falling-Edge Detect Enable register */
76 #define PEDR	0x18	/* Power Manager Edge-Detect Status register */
77 #define PCFR	0x1c	/* Power Manager General Configuration register */
78 #define PGSR0	0x20	/* Power Manager GPIO Sleep-State register 0 */
79 #define PGSR1	0x24	/* Power Manager GPIO Sleep-State register 1 */
80 #define PGSR2	0x28	/* Power Manager GPIO Sleep-State register 2 */
81 #define PGSR3	0x2c	/* Power Manager GPIO Sleep-State register 3 */
82 #define RCSR	0x30	/* Reset Controller Status register */
83 #define PSLR	0x34	/* Power Manager Sleep Configuration register */
84 #define PTSR	0x38	/* Power Manager Standby Configuration register */
85 #define PVCR	0x40	/* Power Manager Voltage Change Control register */
86 #define PUCR	0x4c	/* Power Manager USIM Card Control/Status register */
87 #define PKWR	0x50	/* Power Manager Keyboard Wake-Up Enable register */
88 #define PKSR	0x54	/* Power Manager Keyboard Level-Detect Status */
89 #define PCMD0	0x80	/* Power Manager I2C Command register File 0 */
90 #define PCMD31	0xfc	/* Power Manager I2C Command register File 31 */
91 
pxa2xx_pm_read(void * opaque,target_phys_addr_t addr)92 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
93 {
94     PXA2xxState *s = (PXA2xxState *) opaque;
95 
96     switch (addr) {
97     case PMCR ... PCMD31:
98         if (addr & 3)
99             goto fail;
100 
101         return s->pm_regs[addr >> 2];
102     default:
103     fail:
104         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
105         break;
106     }
107     return 0;
108 }
109 
pxa2xx_pm_write(void * opaque,target_phys_addr_t addr,uint32_t value)110 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
111                 uint32_t value)
112 {
113     PXA2xxState *s = (PXA2xxState *) opaque;
114 
115     switch (addr) {
116     case PMCR:
117         s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
118         s->pm_regs[addr >> 2] |= value & 0x15;
119         break;
120 
121     case PSSR:	/* Read-clean registers */
122     case RCSR:
123     case PKSR:
124         s->pm_regs[addr >> 2] &= ~value;
125         break;
126 
127     default:	/* Read-write registers */
128         if (!(addr & 3)) {
129             s->pm_regs[addr >> 2] = value;
130             break;
131         }
132 
133         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
134         break;
135     }
136 }
137 
138 static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = {
139     pxa2xx_pm_read,
140     pxa2xx_pm_read,
141     pxa2xx_pm_read,
142 };
143 
144 static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = {
145     pxa2xx_pm_write,
146     pxa2xx_pm_write,
147     pxa2xx_pm_write,
148 };
149 
pxa2xx_pm_save(QEMUFile * f,void * opaque)150 static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
151 {
152     PXA2xxState *s = (PXA2xxState *) opaque;
153     int i;
154 
155     for (i = 0; i < 0x40; i ++)
156         qemu_put_be32s(f, &s->pm_regs[i]);
157 }
158 
pxa2xx_pm_load(QEMUFile * f,void * opaque,int version_id)159 static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
160 {
161     PXA2xxState *s = (PXA2xxState *) opaque;
162     int i;
163 
164     for (i = 0; i < 0x40; i ++)
165         qemu_get_be32s(f, &s->pm_regs[i]);
166 
167     return 0;
168 }
169 
170 #define CCCR	0x00	/* Core Clock Configuration register */
171 #define CKEN	0x04	/* Clock Enable register */
172 #define OSCC	0x08	/* Oscillator Configuration register */
173 #define CCSR	0x0c	/* Core Clock Status register */
174 
pxa2xx_cm_read(void * opaque,target_phys_addr_t addr)175 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
176 {
177     PXA2xxState *s = (PXA2xxState *) opaque;
178 
179     switch (addr) {
180     case CCCR:
181     case CKEN:
182     case OSCC:
183         return s->cm_regs[addr >> 2];
184 
185     case CCSR:
186         return s->cm_regs[CCCR >> 2] | (3 << 28);
187 
188     default:
189         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
190         break;
191     }
192     return 0;
193 }
194 
pxa2xx_cm_write(void * opaque,target_phys_addr_t addr,uint32_t value)195 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
196                 uint32_t value)
197 {
198     PXA2xxState *s = (PXA2xxState *) opaque;
199 
200     switch (addr) {
201     case CCCR:
202     case CKEN:
203         s->cm_regs[addr >> 2] = value;
204         break;
205 
206     case OSCC:
207         s->cm_regs[addr >> 2] &= ~0x6c;
208         s->cm_regs[addr >> 2] |= value & 0x6e;
209         if ((value >> 1) & 1)			/* OON */
210             s->cm_regs[addr >> 2] |= 1 << 0;	/* Oscillator is now stable */
211         break;
212 
213     default:
214         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
215         break;
216     }
217 }
218 
219 static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = {
220     pxa2xx_cm_read,
221     pxa2xx_cm_read,
222     pxa2xx_cm_read,
223 };
224 
225 static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = {
226     pxa2xx_cm_write,
227     pxa2xx_cm_write,
228     pxa2xx_cm_write,
229 };
230 
pxa2xx_cm_save(QEMUFile * f,void * opaque)231 static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
232 {
233     PXA2xxState *s = (PXA2xxState *) opaque;
234     int i;
235 
236     for (i = 0; i < 4; i ++)
237         qemu_put_be32s(f, &s->cm_regs[i]);
238     qemu_put_be32s(f, &s->clkcfg);
239     qemu_put_be32s(f, &s->pmnc);
240 }
241 
pxa2xx_cm_load(QEMUFile * f,void * opaque,int version_id)242 static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
243 {
244     PXA2xxState *s = (PXA2xxState *) opaque;
245     int i;
246 
247     for (i = 0; i < 4; i ++)
248         qemu_get_be32s(f, &s->cm_regs[i]);
249     qemu_get_be32s(f, &s->clkcfg);
250     qemu_get_be32s(f, &s->pmnc);
251 
252     return 0;
253 }
254 
pxa2xx_clkpwr_read(void * opaque,int op2,int reg,int crm)255 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
256 {
257     PXA2xxState *s = (PXA2xxState *) opaque;
258 
259     switch (reg) {
260     case 6:	/* Clock Configuration register */
261         return s->clkcfg;
262 
263     case 7:	/* Power Mode register */
264         return 0;
265 
266     default:
267         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
268         break;
269     }
270     return 0;
271 }
272 
pxa2xx_clkpwr_write(void * opaque,int op2,int reg,int crm,uint32_t value)273 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
274                 uint32_t value)
275 {
276     PXA2xxState *s = (PXA2xxState *) opaque;
277     static const char *pwrmode[8] = {
278         "Normal", "Idle", "Deep-idle", "Standby",
279         "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
280     };
281 
282     switch (reg) {
283     case 6:	/* Clock Configuration register */
284         s->clkcfg = value & 0xf;
285         if (value & 2)
286             printf("%s: CPU frequency change attempt\n", __FUNCTION__);
287         break;
288 
289     case 7:	/* Power Mode register */
290         if (value & 8)
291             printf("%s: CPU voltage change attempt\n", __FUNCTION__);
292         switch (value & 7) {
293         case 0:
294             /* Do nothing */
295             break;
296 
297         case 1:
298             /* Idle */
299             if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) {	/* CPDIS */
300                 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
301                 break;
302             }
303             /* Fall through.  */
304 
305         case 2:
306             /* Deep-Idle */
307             cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
308             s->pm_regs[RCSR >> 2] |= 0x8;	/* Set GPR */
309             goto message;
310 
311         case 3:
312             s->env->uncached_cpsr =
313                     ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
314             s->env->cp15.c1_sys = 0;
315             s->env->cp15.c1_coproc = 0;
316             s->env->cp15.c2_base0 = 0;
317             s->env->cp15.c3 = 0;
318             s->pm_regs[PSSR >> 2] |= 0x8;	/* Set STS */
319             s->pm_regs[RCSR >> 2] |= 0x8;	/* Set GPR */
320 
321             /*
322              * The scratch-pad register is almost universally used
323              * for storing the return address on suspend.  For the
324              * lack of a resuming bootloader, perform a jump
325              * directly to that address.
326              */
327             memset(s->env->regs, 0, 4 * 15);
328             s->env->regs[15] = s->pm_regs[PSPR >> 2];
329 
330 #if 0
331             buffer = 0xe59ff000;	/* ldr     pc, [pc, #0] */
332             cpu_physical_memory_write(0, &buffer, 4);
333             buffer = s->pm_regs[PSPR >> 2];
334             cpu_physical_memory_write(8, &buffer, 4);
335 #endif
336 
337             /* Suspend */
338             cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
339 
340             goto message;
341 
342         default:
343         message:
344             printf("%s: machine entered %s mode\n", __FUNCTION__,
345                             pwrmode[value & 7]);
346         }
347         break;
348 
349     default:
350         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
351         break;
352     }
353 }
354 
355 /* Performace Monitoring Registers */
356 #define CPPMNC		0	/* Performance Monitor Control register */
357 #define CPCCNT		1	/* Clock Counter register */
358 #define CPINTEN		4	/* Interrupt Enable register */
359 #define CPFLAG		5	/* Overflow Flag register */
360 #define CPEVTSEL	8	/* Event Selection register */
361 
362 #define CPPMN0		0	/* Performance Count register 0 */
363 #define CPPMN1		1	/* Performance Count register 1 */
364 #define CPPMN2		2	/* Performance Count register 2 */
365 #define CPPMN3		3	/* Performance Count register 3 */
366 
pxa2xx_perf_read(void * opaque,int op2,int reg,int crm)367 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
368 {
369     PXA2xxState *s = (PXA2xxState *) opaque;
370 
371     switch (reg) {
372     case CPPMNC:
373         return s->pmnc;
374     case CPCCNT:
375         if (s->pmnc & 1)
376             return qemu_get_clock(vm_clock);
377         else
378             return 0;
379     case CPINTEN:
380     case CPFLAG:
381     case CPEVTSEL:
382         return 0;
383 
384     default:
385         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
386         break;
387     }
388     return 0;
389 }
390 
pxa2xx_perf_write(void * opaque,int op2,int reg,int crm,uint32_t value)391 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
392                 uint32_t value)
393 {
394     PXA2xxState *s = (PXA2xxState *) opaque;
395 
396     switch (reg) {
397     case CPPMNC:
398         s->pmnc = value;
399         break;
400 
401     case CPCCNT:
402     case CPINTEN:
403     case CPFLAG:
404     case CPEVTSEL:
405         break;
406 
407     default:
408         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
409         break;
410     }
411 }
412 
pxa2xx_cp14_read(void * opaque,int op2,int reg,int crm)413 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
414 {
415     switch (crm) {
416     case 0:
417         return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
418     case 1:
419         return pxa2xx_perf_read(opaque, op2, reg, crm);
420     case 2:
421         switch (reg) {
422         case CPPMN0:
423         case CPPMN1:
424         case CPPMN2:
425         case CPPMN3:
426             return 0;
427         }
428         /* Fall through */
429     default:
430         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
431         break;
432     }
433     return 0;
434 }
435 
pxa2xx_cp14_write(void * opaque,int op2,int reg,int crm,uint32_t value)436 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
437                 uint32_t value)
438 {
439     switch (crm) {
440     case 0:
441         pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
442         break;
443     case 1:
444         pxa2xx_perf_write(opaque, op2, reg, crm, value);
445         break;
446     case 2:
447         switch (reg) {
448         case CPPMN0:
449         case CPPMN1:
450         case CPPMN2:
451         case CPPMN3:
452             return;
453         }
454         /* Fall through */
455     default:
456         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
457         break;
458     }
459 }
460 
461 #define MDCNFG		0x00	/* SDRAM Configuration register */
462 #define MDREFR		0x04	/* SDRAM Refresh Control register */
463 #define MSC0		0x08	/* Static Memory Control register 0 */
464 #define MSC1		0x0c	/* Static Memory Control register 1 */
465 #define MSC2		0x10	/* Static Memory Control register 2 */
466 #define MECR		0x14	/* Expansion Memory Bus Config register */
467 #define SXCNFG		0x1c	/* Synchronous Static Memory Config register */
468 #define MCMEM0		0x28	/* PC Card Memory Socket 0 Timing register */
469 #define MCMEM1		0x2c	/* PC Card Memory Socket 1 Timing register */
470 #define MCATT0		0x30	/* PC Card Attribute Socket 0 register */
471 #define MCATT1		0x34	/* PC Card Attribute Socket 1 register */
472 #define MCIO0		0x38	/* PC Card I/O Socket 0 Timing register */
473 #define MCIO1		0x3c	/* PC Card I/O Socket 1 Timing register */
474 #define MDMRS		0x40	/* SDRAM Mode Register Set Config register */
475 #define BOOT_DEF	0x44	/* Boot-time Default Configuration register */
476 #define ARB_CNTL	0x48	/* Arbiter Control register */
477 #define BSCNTR0		0x4c	/* Memory Buffer Strength Control register 0 */
478 #define BSCNTR1		0x50	/* Memory Buffer Strength Control register 1 */
479 #define LCDBSCNTR	0x54	/* LCD Buffer Strength Control register */
480 #define MDMRSLP		0x58	/* Low Power SDRAM Mode Set Config register */
481 #define BSCNTR2		0x5c	/* Memory Buffer Strength Control register 2 */
482 #define BSCNTR3		0x60	/* Memory Buffer Strength Control register 3 */
483 #define SA1110		0x64	/* SA-1110 Memory Compatibility register */
484 
pxa2xx_mm_read(void * opaque,target_phys_addr_t addr)485 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
486 {
487     PXA2xxState *s = (PXA2xxState *) opaque;
488 
489     switch (addr) {
490     case MDCNFG ... SA1110:
491         if ((addr & 3) == 0)
492             return s->mm_regs[addr >> 2];
493 
494     default:
495         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
496         break;
497     }
498     return 0;
499 }
500 
pxa2xx_mm_write(void * opaque,target_phys_addr_t addr,uint32_t value)501 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
502                 uint32_t value)
503 {
504     PXA2xxState *s = (PXA2xxState *) opaque;
505 
506     switch (addr) {
507     case MDCNFG ... SA1110:
508         if ((addr & 3) == 0) {
509             s->mm_regs[addr >> 2] = value;
510             break;
511         }
512 
513     default:
514         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
515         break;
516     }
517 }
518 
519 static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = {
520     pxa2xx_mm_read,
521     pxa2xx_mm_read,
522     pxa2xx_mm_read,
523 };
524 
525 static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = {
526     pxa2xx_mm_write,
527     pxa2xx_mm_write,
528     pxa2xx_mm_write,
529 };
530 
pxa2xx_mm_save(QEMUFile * f,void * opaque)531 static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
532 {
533     PXA2xxState *s = (PXA2xxState *) opaque;
534     int i;
535 
536     for (i = 0; i < 0x1a; i ++)
537         qemu_put_be32s(f, &s->mm_regs[i]);
538 }
539 
pxa2xx_mm_load(QEMUFile * f,void * opaque,int version_id)540 static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
541 {
542     PXA2xxState *s = (PXA2xxState *) opaque;
543     int i;
544 
545     for (i = 0; i < 0x1a; i ++)
546         qemu_get_be32s(f, &s->mm_regs[i]);
547 
548     return 0;
549 }
550 
551 /* Synchronous Serial Ports */
552 typedef struct {
553     SysBusDevice busdev;
554     qemu_irq irq;
555     int enable;
556     SSIBus *bus;
557 
558     uint32_t sscr[2];
559     uint32_t sspsp;
560     uint32_t ssto;
561     uint32_t ssitr;
562     uint32_t sssr;
563     uint8_t sstsa;
564     uint8_t ssrsa;
565     uint8_t ssacd;
566 
567     uint32_t rx_fifo[16];
568     int rx_level;
569     int rx_start;
570 } PXA2xxSSPState;
571 
572 #define SSCR0	0x00	/* SSP Control register 0 */
573 #define SSCR1	0x04	/* SSP Control register 1 */
574 #define SSSR	0x08	/* SSP Status register */
575 #define SSITR	0x0c	/* SSP Interrupt Test register */
576 #define SSDR	0x10	/* SSP Data register */
577 #define SSTO	0x28	/* SSP Time-Out register */
578 #define SSPSP	0x2c	/* SSP Programmable Serial Protocol register */
579 #define SSTSA	0x30	/* SSP TX Time Slot Active register */
580 #define SSRSA	0x34	/* SSP RX Time Slot Active register */
581 #define SSTSS	0x38	/* SSP Time Slot Status register */
582 #define SSACD	0x3c	/* SSP Audio Clock Divider register */
583 
584 /* Bitfields for above registers */
585 #define SSCR0_SPI(x)	(((x) & 0x30) == 0x00)
586 #define SSCR0_SSP(x)	(((x) & 0x30) == 0x10)
587 #define SSCR0_UWIRE(x)	(((x) & 0x30) == 0x20)
588 #define SSCR0_PSP(x)	(((x) & 0x30) == 0x30)
589 #define SSCR0_SSE	(1 << 7)
590 #define SSCR0_RIM	(1 << 22)
591 #define SSCR0_TIM	(1 << 23)
592 #define SSCR0_MOD	(1 << 31)
593 #define SSCR0_DSS(x)	(((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
594 #define SSCR1_RIE	(1 << 0)
595 #define SSCR1_TIE	(1 << 1)
596 #define SSCR1_LBM	(1 << 2)
597 #define SSCR1_MWDS	(1 << 5)
598 #define SSCR1_TFT(x)	((((x) >> 6) & 0xf) + 1)
599 #define SSCR1_RFT(x)	((((x) >> 10) & 0xf) + 1)
600 #define SSCR1_EFWR	(1 << 14)
601 #define SSCR1_PINTE	(1 << 18)
602 #define SSCR1_TINTE	(1 << 19)
603 #define SSCR1_RSRE	(1 << 20)
604 #define SSCR1_TSRE	(1 << 21)
605 #define SSCR1_EBCEI	(1 << 29)
606 #define SSITR_INT	(7 << 5)
607 #define SSSR_TNF	(1 << 2)
608 #define SSSR_RNE	(1 << 3)
609 #define SSSR_TFS	(1 << 5)
610 #define SSSR_RFS	(1 << 6)
611 #define SSSR_ROR	(1 << 7)
612 #define SSSR_PINT	(1 << 18)
613 #define SSSR_TINT	(1 << 19)
614 #define SSSR_EOC	(1 << 20)
615 #define SSSR_TUR	(1 << 21)
616 #define SSSR_BCE	(1 << 23)
617 #define SSSR_RW		0x00bc0080
618 
pxa2xx_ssp_int_update(PXA2xxSSPState * s)619 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
620 {
621     int level = 0;
622 
623     level |= s->ssitr & SSITR_INT;
624     level |= (s->sssr & SSSR_BCE)  &&  (s->sscr[1] & SSCR1_EBCEI);
625     level |= (s->sssr & SSSR_TUR)  && !(s->sscr[0] & SSCR0_TIM);
626     level |= (s->sssr & SSSR_EOC)  &&  (s->sssr & (SSSR_TINT | SSSR_PINT));
627     level |= (s->sssr & SSSR_TINT) &&  (s->sscr[1] & SSCR1_TINTE);
628     level |= (s->sssr & SSSR_PINT) &&  (s->sscr[1] & SSCR1_PINTE);
629     level |= (s->sssr & SSSR_ROR)  && !(s->sscr[0] & SSCR0_RIM);
630     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
631     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
632     qemu_set_irq(s->irq, !!level);
633 }
634 
pxa2xx_ssp_fifo_update(PXA2xxSSPState * s)635 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
636 {
637     s->sssr &= ~(0xf << 12);	/* Clear RFL */
638     s->sssr &= ~(0xf << 8);	/* Clear TFL */
639     s->sssr &= ~SSSR_TFS;
640     s->sssr &= ~SSSR_TNF;
641     if (s->enable) {
642         s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
643         if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
644             s->sssr |= SSSR_RFS;
645         else
646             s->sssr &= ~SSSR_RFS;
647         if (s->rx_level)
648             s->sssr |= SSSR_RNE;
649         else
650             s->sssr &= ~SSSR_RNE;
651         /* TX FIFO is never filled, so it is always in underrun
652            condition if SSP is enabled */
653         s->sssr |= SSSR_TFS;
654         s->sssr |= SSSR_TNF;
655     }
656 
657     pxa2xx_ssp_int_update(s);
658 }
659 
pxa2xx_ssp_read(void * opaque,target_phys_addr_t addr)660 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
661 {
662     PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
663     uint32_t retval;
664 
665     switch (addr) {
666     case SSCR0:
667         return s->sscr[0];
668     case SSCR1:
669         return s->sscr[1];
670     case SSPSP:
671         return s->sspsp;
672     case SSTO:
673         return s->ssto;
674     case SSITR:
675         return s->ssitr;
676     case SSSR:
677         return s->sssr | s->ssitr;
678     case SSDR:
679         if (!s->enable)
680             return 0xffffffff;
681         if (s->rx_level < 1) {
682             printf("%s: SSP Rx Underrun\n", __FUNCTION__);
683             return 0xffffffff;
684         }
685         s->rx_level --;
686         retval = s->rx_fifo[s->rx_start ++];
687         s->rx_start &= 0xf;
688         pxa2xx_ssp_fifo_update(s);
689         return retval;
690     case SSTSA:
691         return s->sstsa;
692     case SSRSA:
693         return s->ssrsa;
694     case SSTSS:
695         return 0;
696     case SSACD:
697         return s->ssacd;
698     default:
699         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
700         break;
701     }
702     return 0;
703 }
704 
pxa2xx_ssp_write(void * opaque,target_phys_addr_t addr,uint32_t value)705 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
706                 uint32_t value)
707 {
708     PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
709 
710     switch (addr) {
711     case SSCR0:
712         s->sscr[0] = value & 0xc7ffffff;
713         s->enable = value & SSCR0_SSE;
714         if (value & SSCR0_MOD)
715             printf("%s: Attempt to use network mode\n", __FUNCTION__);
716         if (s->enable && SSCR0_DSS(value) < 4)
717             printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
718                             SSCR0_DSS(value));
719         if (!(value & SSCR0_SSE)) {
720             s->sssr = 0;
721             s->ssitr = 0;
722             s->rx_level = 0;
723         }
724         pxa2xx_ssp_fifo_update(s);
725         break;
726 
727     case SSCR1:
728         s->sscr[1] = value;
729         if (value & (SSCR1_LBM | SSCR1_EFWR))
730             printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
731         pxa2xx_ssp_fifo_update(s);
732         break;
733 
734     case SSPSP:
735         s->sspsp = value;
736         break;
737 
738     case SSTO:
739         s->ssto = value;
740         break;
741 
742     case SSITR:
743         s->ssitr = value & SSITR_INT;
744         pxa2xx_ssp_int_update(s);
745         break;
746 
747     case SSSR:
748         s->sssr &= ~(value & SSSR_RW);
749         pxa2xx_ssp_int_update(s);
750         break;
751 
752     case SSDR:
753         if (SSCR0_UWIRE(s->sscr[0])) {
754             if (s->sscr[1] & SSCR1_MWDS)
755                 value &= 0xffff;
756             else
757                 value &= 0xff;
758         } else
759             /* Note how 32bits overflow does no harm here */
760             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
761 
762         /* Data goes from here to the Tx FIFO and is shifted out from
763          * there directly to the slave, no need to buffer it.
764          */
765         if (s->enable) {
766             uint32_t readval;
767             readval = ssi_transfer(s->bus, value);
768             if (s->rx_level < 0x10) {
769                 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
770             } else {
771                 s->sssr |= SSSR_ROR;
772             }
773         }
774         pxa2xx_ssp_fifo_update(s);
775         break;
776 
777     case SSTSA:
778         s->sstsa = value;
779         break;
780 
781     case SSRSA:
782         s->ssrsa = value;
783         break;
784 
785     case SSACD:
786         s->ssacd = value;
787         break;
788 
789     default:
790         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
791         break;
792     }
793 }
794 
795 static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = {
796     pxa2xx_ssp_read,
797     pxa2xx_ssp_read,
798     pxa2xx_ssp_read,
799 };
800 
801 static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = {
802     pxa2xx_ssp_write,
803     pxa2xx_ssp_write,
804     pxa2xx_ssp_write,
805 };
806 
pxa2xx_ssp_save(QEMUFile * f,void * opaque)807 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
808 {
809     PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
810     int i;
811 
812     qemu_put_be32(f, s->enable);
813 
814     qemu_put_be32s(f, &s->sscr[0]);
815     qemu_put_be32s(f, &s->sscr[1]);
816     qemu_put_be32s(f, &s->sspsp);
817     qemu_put_be32s(f, &s->ssto);
818     qemu_put_be32s(f, &s->ssitr);
819     qemu_put_be32s(f, &s->sssr);
820     qemu_put_8s(f, &s->sstsa);
821     qemu_put_8s(f, &s->ssrsa);
822     qemu_put_8s(f, &s->ssacd);
823 
824     qemu_put_byte(f, s->rx_level);
825     for (i = 0; i < s->rx_level; i ++)
826         qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
827 }
828 
pxa2xx_ssp_load(QEMUFile * f,void * opaque,int version_id)829 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
830 {
831     PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
832     int i;
833 
834     s->enable = qemu_get_be32(f);
835 
836     qemu_get_be32s(f, &s->sscr[0]);
837     qemu_get_be32s(f, &s->sscr[1]);
838     qemu_get_be32s(f, &s->sspsp);
839     qemu_get_be32s(f, &s->ssto);
840     qemu_get_be32s(f, &s->ssitr);
841     qemu_get_be32s(f, &s->sssr);
842     qemu_get_8s(f, &s->sstsa);
843     qemu_get_8s(f, &s->ssrsa);
844     qemu_get_8s(f, &s->ssacd);
845 
846     s->rx_level = qemu_get_byte(f);
847     s->rx_start = 0;
848     for (i = 0; i < s->rx_level; i ++)
849         s->rx_fifo[i] = qemu_get_byte(f);
850 
851     return 0;
852 }
853 
pxa2xx_ssp_init(SysBusDevice * dev)854 static int pxa2xx_ssp_init(SysBusDevice *dev)
855 {
856     int iomemtype;
857     PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
858 
859     sysbus_init_irq(dev, &s->irq);
860 
861     iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
862                                        pxa2xx_ssp_writefn, s,
863                                        DEVICE_NATIVE_ENDIAN);
864     sysbus_init_mmio(dev, 0x1000, iomemtype);
865     register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
866                     pxa2xx_ssp_save, pxa2xx_ssp_load, s);
867 
868     s->bus = ssi_create_bus(&dev->qdev, "ssi");
869     return 0;
870 }
871 
872 /* Real-Time Clock */
873 #define RCNR		0x00	/* RTC Counter register */
874 #define RTAR		0x04	/* RTC Alarm register */
875 #define RTSR		0x08	/* RTC Status register */
876 #define RTTR		0x0c	/* RTC Timer Trim register */
877 #define RDCR		0x10	/* RTC Day Counter register */
878 #define RYCR		0x14	/* RTC Year Counter register */
879 #define RDAR1		0x18	/* RTC Wristwatch Day Alarm register 1 */
880 #define RYAR1		0x1c	/* RTC Wristwatch Year Alarm register 1 */
881 #define RDAR2		0x20	/* RTC Wristwatch Day Alarm register 2 */
882 #define RYAR2		0x24	/* RTC Wristwatch Year Alarm register 2 */
883 #define SWCR		0x28	/* RTC Stopwatch Counter register */
884 #define SWAR1		0x2c	/* RTC Stopwatch Alarm register 1 */
885 #define SWAR2		0x30	/* RTC Stopwatch Alarm register 2 */
886 #define RTCPICR		0x34	/* RTC Periodic Interrupt Counter register */
887 #define PIAR		0x38	/* RTC Periodic Interrupt Alarm register */
888 
pxa2xx_rtc_int_update(PXA2xxState * s)889 static inline void pxa2xx_rtc_int_update(PXA2xxState *s)
890 {
891     qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
892 }
893 
pxa2xx_rtc_hzupdate(PXA2xxState * s)894 static void pxa2xx_rtc_hzupdate(PXA2xxState *s)
895 {
896     int64_t rt = qemu_get_clock(rt_clock);
897     s->last_rcnr += ((rt - s->last_hz) << 15) /
898             (1000 * ((s->rttr & 0xffff) + 1));
899     s->last_rdcr += ((rt - s->last_hz) << 15) /
900             (1000 * ((s->rttr & 0xffff) + 1));
901     s->last_hz = rt;
902 }
903 
pxa2xx_rtc_swupdate(PXA2xxState * s)904 static void pxa2xx_rtc_swupdate(PXA2xxState *s)
905 {
906     int64_t rt = qemu_get_clock(rt_clock);
907     if (s->rtsr & (1 << 12))
908         s->last_swcr += (rt - s->last_sw) / 10;
909     s->last_sw = rt;
910 }
911 
pxa2xx_rtc_piupdate(PXA2xxState * s)912 static void pxa2xx_rtc_piupdate(PXA2xxState *s)
913 {
914     int64_t rt = qemu_get_clock(rt_clock);
915     if (s->rtsr & (1 << 15))
916         s->last_swcr += rt - s->last_pi;
917     s->last_pi = rt;
918 }
919 
pxa2xx_rtc_alarm_update(PXA2xxState * s,uint32_t rtsr)920 static inline void pxa2xx_rtc_alarm_update(PXA2xxState *s,
921                 uint32_t rtsr)
922 {
923     if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
924         qemu_mod_timer(s->rtc_hz, s->last_hz +
925                 (((s->rtar - s->last_rcnr) * 1000 *
926                   ((s->rttr & 0xffff) + 1)) >> 15));
927     else
928         qemu_del_timer(s->rtc_hz);
929 
930     if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
931         qemu_mod_timer(s->rtc_rdal1, s->last_hz +
932                 (((s->rdar1 - s->last_rdcr) * 1000 *
933                   ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
934     else
935         qemu_del_timer(s->rtc_rdal1);
936 
937     if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
938         qemu_mod_timer(s->rtc_rdal2, s->last_hz +
939                 (((s->rdar2 - s->last_rdcr) * 1000 *
940                   ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
941     else
942         qemu_del_timer(s->rtc_rdal2);
943 
944     if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
945         qemu_mod_timer(s->rtc_swal1, s->last_sw +
946                         (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
947     else
948         qemu_del_timer(s->rtc_swal1);
949 
950     if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
951         qemu_mod_timer(s->rtc_swal2, s->last_sw +
952                         (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
953     else
954         qemu_del_timer(s->rtc_swal2);
955 
956     if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
957         qemu_mod_timer(s->rtc_pi, s->last_pi +
958                         (s->piar & 0xffff) - s->last_rtcpicr);
959     else
960         qemu_del_timer(s->rtc_pi);
961 }
962 
pxa2xx_rtc_hz_tick(void * opaque)963 static inline void pxa2xx_rtc_hz_tick(void *opaque)
964 {
965     PXA2xxState *s = (PXA2xxState *) opaque;
966     s->rtsr |= (1 << 0);
967     pxa2xx_rtc_alarm_update(s, s->rtsr);
968     pxa2xx_rtc_int_update(s);
969 }
970 
pxa2xx_rtc_rdal1_tick(void * opaque)971 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
972 {
973     PXA2xxState *s = (PXA2xxState *) opaque;
974     s->rtsr |= (1 << 4);
975     pxa2xx_rtc_alarm_update(s, s->rtsr);
976     pxa2xx_rtc_int_update(s);
977 }
978 
pxa2xx_rtc_rdal2_tick(void * opaque)979 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
980 {
981     PXA2xxState *s = (PXA2xxState *) opaque;
982     s->rtsr |= (1 << 6);
983     pxa2xx_rtc_alarm_update(s, s->rtsr);
984     pxa2xx_rtc_int_update(s);
985 }
986 
pxa2xx_rtc_swal1_tick(void * opaque)987 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
988 {
989     PXA2xxState *s = (PXA2xxState *) opaque;
990     s->rtsr |= (1 << 8);
991     pxa2xx_rtc_alarm_update(s, s->rtsr);
992     pxa2xx_rtc_int_update(s);
993 }
994 
pxa2xx_rtc_swal2_tick(void * opaque)995 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
996 {
997     PXA2xxState *s = (PXA2xxState *) opaque;
998     s->rtsr |= (1 << 10);
999     pxa2xx_rtc_alarm_update(s, s->rtsr);
1000     pxa2xx_rtc_int_update(s);
1001 }
1002 
pxa2xx_rtc_pi_tick(void * opaque)1003 static inline void pxa2xx_rtc_pi_tick(void *opaque)
1004 {
1005     PXA2xxState *s = (PXA2xxState *) opaque;
1006     s->rtsr |= (1 << 13);
1007     pxa2xx_rtc_piupdate(s);
1008     s->last_rtcpicr = 0;
1009     pxa2xx_rtc_alarm_update(s, s->rtsr);
1010     pxa2xx_rtc_int_update(s);
1011 }
1012 
pxa2xx_rtc_read(void * opaque,target_phys_addr_t addr)1013 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1014 {
1015     PXA2xxState *s = (PXA2xxState *) opaque;
1016 
1017     switch (addr) {
1018     case RTTR:
1019         return s->rttr;
1020     case RTSR:
1021         return s->rtsr;
1022     case RTAR:
1023         return s->rtar;
1024     case RDAR1:
1025         return s->rdar1;
1026     case RDAR2:
1027         return s->rdar2;
1028     case RYAR1:
1029         return s->ryar1;
1030     case RYAR2:
1031         return s->ryar2;
1032     case SWAR1:
1033         return s->swar1;
1034     case SWAR2:
1035         return s->swar2;
1036     case PIAR:
1037         return s->piar;
1038     case RCNR:
1039         return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1040                 (1000 * ((s->rttr & 0xffff) + 1));
1041     case RDCR:
1042         return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1043                 (1000 * ((s->rttr & 0xffff) + 1));
1044     case RYCR:
1045         return s->last_rycr;
1046     case SWCR:
1047         if (s->rtsr & (1 << 12))
1048             return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
1049         else
1050             return s->last_swcr;
1051     default:
1052         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1053         break;
1054     }
1055     return 0;
1056 }
1057 
pxa2xx_rtc_write(void * opaque,target_phys_addr_t addr,uint32_t value)1058 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1059                 uint32_t value)
1060 {
1061     PXA2xxState *s = (PXA2xxState *) opaque;
1062 
1063     switch (addr) {
1064     case RTTR:
1065         if (!(s->rttr & (1 << 31))) {
1066             pxa2xx_rtc_hzupdate(s);
1067             s->rttr = value;
1068             pxa2xx_rtc_alarm_update(s, s->rtsr);
1069         }
1070         break;
1071 
1072     case RTSR:
1073         if ((s->rtsr ^ value) & (1 << 15))
1074             pxa2xx_rtc_piupdate(s);
1075 
1076         if ((s->rtsr ^ value) & (1 << 12))
1077             pxa2xx_rtc_swupdate(s);
1078 
1079         if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1080             pxa2xx_rtc_alarm_update(s, value);
1081 
1082         s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1083         pxa2xx_rtc_int_update(s);
1084         break;
1085 
1086     case RTAR:
1087         s->rtar = value;
1088         pxa2xx_rtc_alarm_update(s, s->rtsr);
1089         break;
1090 
1091     case RDAR1:
1092         s->rdar1 = value;
1093         pxa2xx_rtc_alarm_update(s, s->rtsr);
1094         break;
1095 
1096     case RDAR2:
1097         s->rdar2 = value;
1098         pxa2xx_rtc_alarm_update(s, s->rtsr);
1099         break;
1100 
1101     case RYAR1:
1102         s->ryar1 = value;
1103         pxa2xx_rtc_alarm_update(s, s->rtsr);
1104         break;
1105 
1106     case RYAR2:
1107         s->ryar2 = value;
1108         pxa2xx_rtc_alarm_update(s, s->rtsr);
1109         break;
1110 
1111     case SWAR1:
1112         pxa2xx_rtc_swupdate(s);
1113         s->swar1 = value;
1114         s->last_swcr = 0;
1115         pxa2xx_rtc_alarm_update(s, s->rtsr);
1116         break;
1117 
1118     case SWAR2:
1119         s->swar2 = value;
1120         pxa2xx_rtc_alarm_update(s, s->rtsr);
1121         break;
1122 
1123     case PIAR:
1124         s->piar = value;
1125         pxa2xx_rtc_alarm_update(s, s->rtsr);
1126         break;
1127 
1128     case RCNR:
1129         pxa2xx_rtc_hzupdate(s);
1130         s->last_rcnr = value;
1131         pxa2xx_rtc_alarm_update(s, s->rtsr);
1132         break;
1133 
1134     case RDCR:
1135         pxa2xx_rtc_hzupdate(s);
1136         s->last_rdcr = value;
1137         pxa2xx_rtc_alarm_update(s, s->rtsr);
1138         break;
1139 
1140     case RYCR:
1141         s->last_rycr = value;
1142         break;
1143 
1144     case SWCR:
1145         pxa2xx_rtc_swupdate(s);
1146         s->last_swcr = value;
1147         pxa2xx_rtc_alarm_update(s, s->rtsr);
1148         break;
1149 
1150     case RTCPICR:
1151         pxa2xx_rtc_piupdate(s);
1152         s->last_rtcpicr = value & 0xffff;
1153         pxa2xx_rtc_alarm_update(s, s->rtsr);
1154         break;
1155 
1156     default:
1157         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1158     }
1159 }
1160 
1161 static CPUReadMemoryFunc * const pxa2xx_rtc_readfn[] = {
1162     pxa2xx_rtc_read,
1163     pxa2xx_rtc_read,
1164     pxa2xx_rtc_read,
1165 };
1166 
1167 static CPUWriteMemoryFunc * const pxa2xx_rtc_writefn[] = {
1168     pxa2xx_rtc_write,
1169     pxa2xx_rtc_write,
1170     pxa2xx_rtc_write,
1171 };
1172 
pxa2xx_rtc_init(PXA2xxState * s)1173 static void pxa2xx_rtc_init(PXA2xxState *s)
1174 {
1175     struct tm tm;
1176     int wom;
1177 
1178     s->rttr = 0x7fff;
1179     s->rtsr = 0;
1180 
1181     qemu_get_timedate(&tm, 0);
1182     wom = ((tm.tm_mday - 1) / 7) + 1;
1183 
1184     s->last_rcnr = (uint32_t) mktimegm(&tm);
1185     s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1186             (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1187     s->last_rycr = ((tm.tm_year + 1900) << 9) |
1188             ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1189     s->last_swcr = (tm.tm_hour << 19) |
1190             (tm.tm_min << 13) | (tm.tm_sec << 7);
1191     s->last_rtcpicr = 0;
1192     s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1193 
1194     s->rtc_hz    = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick,    s);
1195     s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1196     s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1197     s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1198     s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1199     s->rtc_pi    = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick,    s);
1200 }
1201 
pxa2xx_rtc_save(QEMUFile * f,void * opaque)1202 static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1203 {
1204     PXA2xxState *s = (PXA2xxState *) opaque;
1205 
1206     pxa2xx_rtc_hzupdate(s);
1207     pxa2xx_rtc_piupdate(s);
1208     pxa2xx_rtc_swupdate(s);
1209 
1210     qemu_put_be32s(f, &s->rttr);
1211     qemu_put_be32s(f, &s->rtsr);
1212     qemu_put_be32s(f, &s->rtar);
1213     qemu_put_be32s(f, &s->rdar1);
1214     qemu_put_be32s(f, &s->rdar2);
1215     qemu_put_be32s(f, &s->ryar1);
1216     qemu_put_be32s(f, &s->ryar2);
1217     qemu_put_be32s(f, &s->swar1);
1218     qemu_put_be32s(f, &s->swar2);
1219     qemu_put_be32s(f, &s->piar);
1220     qemu_put_be32s(f, &s->last_rcnr);
1221     qemu_put_be32s(f, &s->last_rdcr);
1222     qemu_put_be32s(f, &s->last_rycr);
1223     qemu_put_be32s(f, &s->last_swcr);
1224     qemu_put_be32s(f, &s->last_rtcpicr);
1225     qemu_put_sbe64s(f, &s->last_hz);
1226     qemu_put_sbe64s(f, &s->last_sw);
1227     qemu_put_sbe64s(f, &s->last_pi);
1228 }
1229 
pxa2xx_rtc_load(QEMUFile * f,void * opaque,int version_id)1230 static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1231 {
1232     PXA2xxState *s = (PXA2xxState *) opaque;
1233 
1234     qemu_get_be32s(f, &s->rttr);
1235     qemu_get_be32s(f, &s->rtsr);
1236     qemu_get_be32s(f, &s->rtar);
1237     qemu_get_be32s(f, &s->rdar1);
1238     qemu_get_be32s(f, &s->rdar2);
1239     qemu_get_be32s(f, &s->ryar1);
1240     qemu_get_be32s(f, &s->ryar2);
1241     qemu_get_be32s(f, &s->swar1);
1242     qemu_get_be32s(f, &s->swar2);
1243     qemu_get_be32s(f, &s->piar);
1244     qemu_get_be32s(f, &s->last_rcnr);
1245     qemu_get_be32s(f, &s->last_rdcr);
1246     qemu_get_be32s(f, &s->last_rycr);
1247     qemu_get_be32s(f, &s->last_swcr);
1248     qemu_get_be32s(f, &s->last_rtcpicr);
1249     qemu_get_sbe64s(f, &s->last_hz);
1250     qemu_get_sbe64s(f, &s->last_sw);
1251     qemu_get_sbe64s(f, &s->last_pi);
1252 
1253     pxa2xx_rtc_alarm_update(s, s->rtsr);
1254 
1255     return 0;
1256 }
1257 
1258 /* I2C Interface */
1259 typedef struct {
1260     i2c_slave i2c;
1261     PXA2xxI2CState *host;
1262 } PXA2xxI2CSlaveState;
1263 
1264 struct PXA2xxI2CState {
1265     PXA2xxI2CSlaveState *slave;
1266     i2c_bus *bus;
1267     qemu_irq irq;
1268     target_phys_addr_t offset;
1269 
1270     uint16_t control;
1271     uint16_t status;
1272     uint8_t ibmr;
1273     uint8_t data;
1274 };
1275 
1276 #define IBMR	0x80	/* I2C Bus Monitor register */
1277 #define IDBR	0x88	/* I2C Data Buffer register */
1278 #define ICR	0x90	/* I2C Control register */
1279 #define ISR	0x98	/* I2C Status register */
1280 #define ISAR	0xa0	/* I2C Slave Address register */
1281 
pxa2xx_i2c_update(PXA2xxI2CState * s)1282 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1283 {
1284     uint16_t level = 0;
1285     level |= s->status & s->control & (1 << 10);		/* BED */
1286     level |= (s->status & (1 << 7)) && (s->control & (1 << 9));	/* IRF */
1287     level |= (s->status & (1 << 6)) && (s->control & (1 << 8));	/* ITE */
1288     level |= s->status & (1 << 9);				/* SAD */
1289     qemu_set_irq(s->irq, !!level);
1290 }
1291 
1292 /* These are only stubs now.  */
pxa2xx_i2c_event(i2c_slave * i2c,enum i2c_event event)1293 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1294 {
1295     PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1296     PXA2xxI2CState *s = slave->host;
1297 
1298     switch (event) {
1299     case I2C_START_SEND:
1300         s->status |= (1 << 9);				/* set SAD */
1301         s->status &= ~(1 << 0);				/* clear RWM */
1302         break;
1303     case I2C_START_RECV:
1304         s->status |= (1 << 9);				/* set SAD */
1305         s->status |= 1 << 0;				/* set RWM */
1306         break;
1307     case I2C_FINISH:
1308         s->status |= (1 << 4);				/* set SSD */
1309         break;
1310     case I2C_NACK:
1311         s->status |= 1 << 1;				/* set ACKNAK */
1312         break;
1313     }
1314     pxa2xx_i2c_update(s);
1315 }
1316 
pxa2xx_i2c_rx(i2c_slave * i2c)1317 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1318 {
1319     PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1320     PXA2xxI2CState *s = slave->host;
1321     if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1322         return 0;
1323 
1324     if (s->status & (1 << 0)) {			/* RWM */
1325         s->status |= 1 << 6;			/* set ITE */
1326     }
1327     pxa2xx_i2c_update(s);
1328 
1329     return s->data;
1330 }
1331 
pxa2xx_i2c_tx(i2c_slave * i2c,uint8_t data)1332 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1333 {
1334     PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1335     PXA2xxI2CState *s = slave->host;
1336     if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1337         return 1;
1338 
1339     if (!(s->status & (1 << 0))) {		/* RWM */
1340         s->status |= 1 << 7;			/* set IRF */
1341         s->data = data;
1342     }
1343     pxa2xx_i2c_update(s);
1344 
1345     return 1;
1346 }
1347 
pxa2xx_i2c_read(void * opaque,target_phys_addr_t addr)1348 static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1349 {
1350     PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1351 
1352     addr -= s->offset;
1353     switch (addr) {
1354     case ICR:
1355         return s->control;
1356     case ISR:
1357         return s->status | (i2c_bus_busy(s->bus) << 2);
1358     case ISAR:
1359         return s->slave->i2c.address;
1360     case IDBR:
1361         return s->data;
1362     case IBMR:
1363         if (s->status & (1 << 2))
1364             s->ibmr ^= 3;	/* Fake SCL and SDA pin changes */
1365         else
1366             s->ibmr = 0;
1367         return s->ibmr;
1368     default:
1369         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1370         break;
1371     }
1372     return 0;
1373 }
1374 
pxa2xx_i2c_write(void * opaque,target_phys_addr_t addr,uint32_t value)1375 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1376                 uint32_t value)
1377 {
1378     PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1379     int ack;
1380 
1381     addr -= s->offset;
1382     switch (addr) {
1383     case ICR:
1384         s->control = value & 0xfff7;
1385         if ((value & (1 << 3)) && (value & (1 << 6))) {	/* TB and IUE */
1386             /* TODO: slave mode */
1387             if (value & (1 << 0)) {			/* START condition */
1388                 if (s->data & 1)
1389                     s->status |= 1 << 0;		/* set RWM */
1390                 else
1391                     s->status &= ~(1 << 0);		/* clear RWM */
1392                 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1393             } else {
1394                 if (s->status & (1 << 0)) {		/* RWM */
1395                     s->data = i2c_recv(s->bus);
1396                     if (value & (1 << 2))		/* ACKNAK */
1397                         i2c_nack(s->bus);
1398                     ack = 1;
1399                 } else
1400                     ack = !i2c_send(s->bus, s->data);
1401             }
1402 
1403             if (value & (1 << 1))			/* STOP condition */
1404                 i2c_end_transfer(s->bus);
1405 
1406             if (ack) {
1407                 if (value & (1 << 0))			/* START condition */
1408                     s->status |= 1 << 6;		/* set ITE */
1409                 else
1410                     if (s->status & (1 << 0))		/* RWM */
1411                         s->status |= 1 << 7;		/* set IRF */
1412                     else
1413                         s->status |= 1 << 6;		/* set ITE */
1414                 s->status &= ~(1 << 1);			/* clear ACKNAK */
1415             } else {
1416                 s->status |= 1 << 6;			/* set ITE */
1417                 s->status |= 1 << 10;			/* set BED */
1418                 s->status |= 1 << 1;			/* set ACKNAK */
1419             }
1420         }
1421         if (!(value & (1 << 3)) && (value & (1 << 6)))	/* !TB and IUE */
1422             if (value & (1 << 4))			/* MA */
1423                 i2c_end_transfer(s->bus);
1424         pxa2xx_i2c_update(s);
1425         break;
1426 
1427     case ISR:
1428         s->status &= ~(value & 0x07f0);
1429         pxa2xx_i2c_update(s);
1430         break;
1431 
1432     case ISAR:
1433         i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1434         break;
1435 
1436     case IDBR:
1437         s->data = value & 0xff;
1438         break;
1439 
1440     default:
1441         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1442     }
1443 }
1444 
1445 static CPUReadMemoryFunc * const pxa2xx_i2c_readfn[] = {
1446     pxa2xx_i2c_read,
1447     pxa2xx_i2c_read,
1448     pxa2xx_i2c_read,
1449 };
1450 
1451 static CPUWriteMemoryFunc * const pxa2xx_i2c_writefn[] = {
1452     pxa2xx_i2c_write,
1453     pxa2xx_i2c_write,
1454     pxa2xx_i2c_write,
1455 };
1456 
1457 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1458     .name = "pxa2xx_i2c_slave",
1459     .version_id = 1,
1460     .minimum_version_id = 1,
1461     .minimum_version_id_old = 1,
1462     .fields      = (VMStateField []) {
1463         VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1464         VMSTATE_END_OF_LIST()
1465     }
1466 };
1467 
1468 static const VMStateDescription vmstate_pxa2xx_i2c = {
1469     .name = "pxa2xx_i2c",
1470     .version_id = 1,
1471     .minimum_version_id = 1,
1472     .minimum_version_id_old = 1,
1473     .fields      = (VMStateField []) {
1474         VMSTATE_UINT16(control, PXA2xxI2CState),
1475         VMSTATE_UINT16(status, PXA2xxI2CState),
1476         VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1477         VMSTATE_UINT8(data, PXA2xxI2CState),
1478         VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1479                                vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *),
1480         VMSTATE_END_OF_LIST()
1481     }
1482 };
1483 
pxa2xx_i2c_slave_init(i2c_slave * i2c)1484 static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
1485 {
1486     /* Nothing to do.  */
1487     return 0;
1488 }
1489 
1490 static I2CSlaveInfo pxa2xx_i2c_slave_info = {
1491     .qdev.name = "pxa2xx-i2c-slave",
1492     .qdev.size = sizeof(PXA2xxI2CSlaveState),
1493     .init = pxa2xx_i2c_slave_init,
1494     .event = pxa2xx_i2c_event,
1495     .recv = pxa2xx_i2c_rx,
1496     .send = pxa2xx_i2c_tx
1497 };
1498 
pxa2xx_i2c_init(target_phys_addr_t base,qemu_irq irq,uint32_t region_size)1499 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1500                 qemu_irq irq, uint32_t region_size)
1501 {
1502     int iomemtype;
1503     DeviceState *dev;
1504     PXA2xxI2CState *s = qemu_mallocz(sizeof(PXA2xxI2CState));
1505 
1506     /* FIXME: Should the slave device really be on a separate bus?  */
1507     dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1508     s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1509     s->slave->host = s;
1510 
1511     s->irq = irq;
1512     s->bus = i2c_init_bus(NULL, "i2c");
1513     s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK);
1514 
1515     iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
1516                     pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
1517     cpu_register_physical_memory(base & ~region_size,
1518                     region_size + 1, iomemtype);
1519 
1520     vmstate_register(NULL, base, &vmstate_pxa2xx_i2c, s);
1521 
1522     return s;
1523 }
1524 
pxa2xx_i2c_bus(PXA2xxI2CState * s)1525 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1526 {
1527     return s->bus;
1528 }
1529 
1530 /* PXA Inter-IC Sound Controller */
pxa2xx_i2s_reset(PXA2xxI2SState * i2s)1531 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1532 {
1533     i2s->rx_len = 0;
1534     i2s->tx_len = 0;
1535     i2s->fifo_len = 0;
1536     i2s->clk = 0x1a;
1537     i2s->control[0] = 0x00;
1538     i2s->control[1] = 0x00;
1539     i2s->status = 0x00;
1540     i2s->mask = 0x00;
1541 }
1542 
1543 #define SACR_TFTH(val)	((val >> 8) & 0xf)
1544 #define SACR_RFTH(val)	((val >> 12) & 0xf)
1545 #define SACR_DREC(val)	(val & (1 << 3))
1546 #define SACR_DPRL(val)	(val & (1 << 4))
1547 
pxa2xx_i2s_update(PXA2xxI2SState * i2s)1548 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1549 {
1550     int rfs, tfs;
1551     rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1552             !SACR_DREC(i2s->control[1]);
1553     tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1554             i2s->enable && !SACR_DPRL(i2s->control[1]);
1555 
1556     pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1557     pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1558 
1559     i2s->status &= 0xe0;
1560     if (i2s->fifo_len < 16 || !i2s->enable)
1561         i2s->status |= 1 << 0;			/* TNF */
1562     if (i2s->rx_len)
1563         i2s->status |= 1 << 1;			/* RNE */
1564     if (i2s->enable)
1565         i2s->status |= 1 << 2;			/* BSY */
1566     if (tfs)
1567         i2s->status |= 1 << 3;			/* TFS */
1568     if (rfs)
1569         i2s->status |= 1 << 4;			/* RFS */
1570     if (!(i2s->tx_len && i2s->enable))
1571         i2s->status |= i2s->fifo_len << 8;	/* TFL */
1572     i2s->status |= MAX(i2s->rx_len, 0xf) << 12;	/* RFL */
1573 
1574     qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1575 }
1576 
1577 #define SACR0	0x00	/* Serial Audio Global Control register */
1578 #define SACR1	0x04	/* Serial Audio I2S/MSB-Justified Control register */
1579 #define SASR0	0x0c	/* Serial Audio Interface and FIFO Status register */
1580 #define SAIMR	0x14	/* Serial Audio Interrupt Mask register */
1581 #define SAICR	0x18	/* Serial Audio Interrupt Clear register */
1582 #define SADIV	0x60	/* Serial Audio Clock Divider register */
1583 #define SADR	0x80	/* Serial Audio Data register */
1584 
pxa2xx_i2s_read(void * opaque,target_phys_addr_t addr)1585 static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1586 {
1587     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1588 
1589     switch (addr) {
1590     case SACR0:
1591         return s->control[0];
1592     case SACR1:
1593         return s->control[1];
1594     case SASR0:
1595         return s->status;
1596     case SAIMR:
1597         return s->mask;
1598     case SAICR:
1599         return 0;
1600     case SADIV:
1601         return s->clk;
1602     case SADR:
1603         if (s->rx_len > 0) {
1604             s->rx_len --;
1605             pxa2xx_i2s_update(s);
1606             return s->codec_in(s->opaque);
1607         }
1608         return 0;
1609     default:
1610         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1611         break;
1612     }
1613     return 0;
1614 }
1615 
pxa2xx_i2s_write(void * opaque,target_phys_addr_t addr,uint32_t value)1616 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1617                 uint32_t value)
1618 {
1619     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1620     uint32_t *sample;
1621 
1622     switch (addr) {
1623     case SACR0:
1624         if (value & (1 << 3))				/* RST */
1625             pxa2xx_i2s_reset(s);
1626         s->control[0] = value & 0xff3d;
1627         if (!s->enable && (value & 1) && s->tx_len) {	/* ENB */
1628             for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1629                 s->codec_out(s->opaque, *sample);
1630             s->status &= ~(1 << 7);			/* I2SOFF */
1631         }
1632         if (value & (1 << 4))				/* EFWR */
1633             printf("%s: Attempt to use special function\n", __FUNCTION__);
1634         s->enable = ((value ^ 4) & 5) == 5;		/* ENB && !RST*/
1635         pxa2xx_i2s_update(s);
1636         break;
1637     case SACR1:
1638         s->control[1] = value & 0x0039;
1639         if (value & (1 << 5))				/* ENLBF */
1640             printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1641         if (value & (1 << 4))				/* DPRL */
1642             s->fifo_len = 0;
1643         pxa2xx_i2s_update(s);
1644         break;
1645     case SAIMR:
1646         s->mask = value & 0x0078;
1647         pxa2xx_i2s_update(s);
1648         break;
1649     case SAICR:
1650         s->status &= ~(value & (3 << 5));
1651         pxa2xx_i2s_update(s);
1652         break;
1653     case SADIV:
1654         s->clk = value & 0x007f;
1655         break;
1656     case SADR:
1657         if (s->tx_len && s->enable) {
1658             s->tx_len --;
1659             pxa2xx_i2s_update(s);
1660             s->codec_out(s->opaque, value);
1661         } else if (s->fifo_len < 16) {
1662             s->fifo[s->fifo_len ++] = value;
1663             pxa2xx_i2s_update(s);
1664         }
1665         break;
1666     default:
1667         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1668     }
1669 }
1670 
1671 static CPUReadMemoryFunc * const pxa2xx_i2s_readfn[] = {
1672     pxa2xx_i2s_read,
1673     pxa2xx_i2s_read,
1674     pxa2xx_i2s_read,
1675 };
1676 
1677 static CPUWriteMemoryFunc * const pxa2xx_i2s_writefn[] = {
1678     pxa2xx_i2s_write,
1679     pxa2xx_i2s_write,
1680     pxa2xx_i2s_write,
1681 };
1682 
pxa2xx_i2s_save(QEMUFile * f,void * opaque)1683 static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1684 {
1685     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1686 
1687     qemu_put_be32s(f, &s->control[0]);
1688     qemu_put_be32s(f, &s->control[1]);
1689     qemu_put_be32s(f, &s->status);
1690     qemu_put_be32s(f, &s->mask);
1691     qemu_put_be32s(f, &s->clk);
1692 
1693     qemu_put_be32(f, s->enable);
1694     qemu_put_be32(f, s->rx_len);
1695     qemu_put_be32(f, s->tx_len);
1696     qemu_put_be32(f, s->fifo_len);
1697 }
1698 
pxa2xx_i2s_load(QEMUFile * f,void * opaque,int version_id)1699 static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1700 {
1701     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1702 
1703     qemu_get_be32s(f, &s->control[0]);
1704     qemu_get_be32s(f, &s->control[1]);
1705     qemu_get_be32s(f, &s->status);
1706     qemu_get_be32s(f, &s->mask);
1707     qemu_get_be32s(f, &s->clk);
1708 
1709     s->enable = qemu_get_be32(f);
1710     s->rx_len = qemu_get_be32(f);
1711     s->tx_len = qemu_get_be32(f);
1712     s->fifo_len = qemu_get_be32(f);
1713 
1714     return 0;
1715 }
1716 
pxa2xx_i2s_data_req(void * opaque,int tx,int rx)1717 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1718 {
1719     PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1720     uint32_t *sample;
1721 
1722     /* Signal FIFO errors */
1723     if (s->enable && s->tx_len)
1724         s->status |= 1 << 5;		/* TUR */
1725     if (s->enable && s->rx_len)
1726         s->status |= 1 << 6;		/* ROR */
1727 
1728     /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1729      * handle the cases where it makes a difference.  */
1730     s->tx_len = tx - s->fifo_len;
1731     s->rx_len = rx;
1732     /* Note that is s->codec_out wasn't set, we wouldn't get called.  */
1733     if (s->enable)
1734         for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1735             s->codec_out(s->opaque, *sample);
1736     pxa2xx_i2s_update(s);
1737 }
1738 
pxa2xx_i2s_init(target_phys_addr_t base,qemu_irq irq,PXA2xxDMAState * dma)1739 static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
1740                 qemu_irq irq, PXA2xxDMAState *dma)
1741 {
1742     int iomemtype;
1743     PXA2xxI2SState *s = (PXA2xxI2SState *)
1744             qemu_mallocz(sizeof(PXA2xxI2SState));
1745 
1746     s->irq = irq;
1747     s->dma = dma;
1748     s->data_req = pxa2xx_i2s_data_req;
1749 
1750     pxa2xx_i2s_reset(s);
1751 
1752     iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
1753                     pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN);
1754     cpu_register_physical_memory(base, 0x100000, iomemtype);
1755 
1756     register_savevm(NULL, "pxa2xx_i2s", base, 0,
1757                     pxa2xx_i2s_save, pxa2xx_i2s_load, s);
1758 
1759     return s;
1760 }
1761 
1762 /* PXA Fast Infra-red Communications Port */
1763 struct PXA2xxFIrState {
1764     qemu_irq irq;
1765     PXA2xxDMAState *dma;
1766     int enable;
1767     CharDriverState *chr;
1768 
1769     uint8_t control[3];
1770     uint8_t status[2];
1771 
1772     int rx_len;
1773     int rx_start;
1774     uint8_t rx_fifo[64];
1775 };
1776 
pxa2xx_fir_reset(PXA2xxFIrState * s)1777 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1778 {
1779     s->control[0] = 0x00;
1780     s->control[1] = 0x00;
1781     s->control[2] = 0x00;
1782     s->status[0] = 0x00;
1783     s->status[1] = 0x00;
1784     s->enable = 0;
1785 }
1786 
pxa2xx_fir_update(PXA2xxFIrState * s)1787 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1788 {
1789     static const int tresh[4] = { 8, 16, 32, 0 };
1790     int intr = 0;
1791     if ((s->control[0] & (1 << 4)) &&			/* RXE */
1792                     s->rx_len >= tresh[s->control[2] & 3])	/* TRIG */
1793         s->status[0] |= 1 << 4;				/* RFS */
1794     else
1795         s->status[0] &= ~(1 << 4);			/* RFS */
1796     if (s->control[0] & (1 << 3))			/* TXE */
1797         s->status[0] |= 1 << 3;				/* TFS */
1798     else
1799         s->status[0] &= ~(1 << 3);			/* TFS */
1800     if (s->rx_len)
1801         s->status[1] |= 1 << 2;				/* RNE */
1802     else
1803         s->status[1] &= ~(1 << 2);			/* RNE */
1804     if (s->control[0] & (1 << 4))			/* RXE */
1805         s->status[1] |= 1 << 0;				/* RSY */
1806     else
1807         s->status[1] &= ~(1 << 0);			/* RSY */
1808 
1809     intr |= (s->control[0] & (1 << 5)) &&		/* RIE */
1810             (s->status[0] & (1 << 4));			/* RFS */
1811     intr |= (s->control[0] & (1 << 6)) &&		/* TIE */
1812             (s->status[0] & (1 << 3));			/* TFS */
1813     intr |= (s->control[2] & (1 << 4)) &&		/* TRAIL */
1814             (s->status[0] & (1 << 6));			/* EOC */
1815     intr |= (s->control[0] & (1 << 2)) &&		/* TUS */
1816             (s->status[0] & (1 << 1));			/* TUR */
1817     intr |= s->status[0] & 0x25;			/* FRE, RAB, EIF */
1818 
1819     pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1820     pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1821 
1822     qemu_set_irq(s->irq, intr && s->enable);
1823 }
1824 
1825 #define ICCR0	0x00	/* FICP Control register 0 */
1826 #define ICCR1	0x04	/* FICP Control register 1 */
1827 #define ICCR2	0x08	/* FICP Control register 2 */
1828 #define ICDR	0x0c	/* FICP Data register */
1829 #define ICSR0	0x14	/* FICP Status register 0 */
1830 #define ICSR1	0x18	/* FICP Status register 1 */
1831 #define ICFOR	0x1c	/* FICP FIFO Occupancy Status register */
1832 
pxa2xx_fir_read(void * opaque,target_phys_addr_t addr)1833 static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1834 {
1835     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1836     uint8_t ret;
1837 
1838     switch (addr) {
1839     case ICCR0:
1840         return s->control[0];
1841     case ICCR1:
1842         return s->control[1];
1843     case ICCR2:
1844         return s->control[2];
1845     case ICDR:
1846         s->status[0] &= ~0x01;
1847         s->status[1] &= ~0x72;
1848         if (s->rx_len) {
1849             s->rx_len --;
1850             ret = s->rx_fifo[s->rx_start ++];
1851             s->rx_start &= 63;
1852             pxa2xx_fir_update(s);
1853             return ret;
1854         }
1855         printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1856         break;
1857     case ICSR0:
1858         return s->status[0];
1859     case ICSR1:
1860         return s->status[1] | (1 << 3);			/* TNF */
1861     case ICFOR:
1862         return s->rx_len;
1863     default:
1864         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1865         break;
1866     }
1867     return 0;
1868 }
1869 
pxa2xx_fir_write(void * opaque,target_phys_addr_t addr,uint32_t value)1870 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1871                 uint32_t value)
1872 {
1873     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1874     uint8_t ch;
1875 
1876     switch (addr) {
1877     case ICCR0:
1878         s->control[0] = value;
1879         if (!(value & (1 << 4)))			/* RXE */
1880             s->rx_len = s->rx_start = 0;
1881         if (!(value & (1 << 3))) {                      /* TXE */
1882             /* Nop */
1883         }
1884         s->enable = value & 1;				/* ITR */
1885         if (!s->enable)
1886             s->status[0] = 0;
1887         pxa2xx_fir_update(s);
1888         break;
1889     case ICCR1:
1890         s->control[1] = value;
1891         break;
1892     case ICCR2:
1893         s->control[2] = value & 0x3f;
1894         pxa2xx_fir_update(s);
1895         break;
1896     case ICDR:
1897         if (s->control[2] & (1 << 2))			/* TXP */
1898             ch = value;
1899         else
1900             ch = ~value;
1901         if (s->chr && s->enable && (s->control[0] & (1 << 3)))	/* TXE */
1902             qemu_chr_write(s->chr, &ch, 1);
1903         break;
1904     case ICSR0:
1905         s->status[0] &= ~(value & 0x66);
1906         pxa2xx_fir_update(s);
1907         break;
1908     case ICFOR:
1909         break;
1910     default:
1911         printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1912     }
1913 }
1914 
1915 static CPUReadMemoryFunc * const pxa2xx_fir_readfn[] = {
1916     pxa2xx_fir_read,
1917     pxa2xx_fir_read,
1918     pxa2xx_fir_read,
1919 };
1920 
1921 static CPUWriteMemoryFunc * const pxa2xx_fir_writefn[] = {
1922     pxa2xx_fir_write,
1923     pxa2xx_fir_write,
1924     pxa2xx_fir_write,
1925 };
1926 
pxa2xx_fir_is_empty(void * opaque)1927 static int pxa2xx_fir_is_empty(void *opaque)
1928 {
1929     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1930     return (s->rx_len < 64);
1931 }
1932 
pxa2xx_fir_rx(void * opaque,const uint8_t * buf,int size)1933 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1934 {
1935     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1936     if (!(s->control[0] & (1 << 4)))			/* RXE */
1937         return;
1938 
1939     while (size --) {
1940         s->status[1] |= 1 << 4;				/* EOF */
1941         if (s->rx_len >= 64) {
1942             s->status[1] |= 1 << 6;			/* ROR */
1943             break;
1944         }
1945 
1946         if (s->control[2] & (1 << 3))			/* RXP */
1947             s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1948         else
1949             s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1950     }
1951 
1952     pxa2xx_fir_update(s);
1953 }
1954 
pxa2xx_fir_event(void * opaque,int event)1955 static void pxa2xx_fir_event(void *opaque, int event)
1956 {
1957 }
1958 
pxa2xx_fir_save(QEMUFile * f,void * opaque)1959 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1960 {
1961     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1962     int i;
1963 
1964     qemu_put_be32(f, s->enable);
1965 
1966     qemu_put_8s(f, &s->control[0]);
1967     qemu_put_8s(f, &s->control[1]);
1968     qemu_put_8s(f, &s->control[2]);
1969     qemu_put_8s(f, &s->status[0]);
1970     qemu_put_8s(f, &s->status[1]);
1971 
1972     qemu_put_byte(f, s->rx_len);
1973     for (i = 0; i < s->rx_len; i ++)
1974         qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1975 }
1976 
pxa2xx_fir_load(QEMUFile * f,void * opaque,int version_id)1977 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1978 {
1979     PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1980     int i;
1981 
1982     s->enable = qemu_get_be32(f);
1983 
1984     qemu_get_8s(f, &s->control[0]);
1985     qemu_get_8s(f, &s->control[1]);
1986     qemu_get_8s(f, &s->control[2]);
1987     qemu_get_8s(f, &s->status[0]);
1988     qemu_get_8s(f, &s->status[1]);
1989 
1990     s->rx_len = qemu_get_byte(f);
1991     s->rx_start = 0;
1992     for (i = 0; i < s->rx_len; i ++)
1993         s->rx_fifo[i] = qemu_get_byte(f);
1994 
1995     return 0;
1996 }
1997 
pxa2xx_fir_init(target_phys_addr_t base,qemu_irq irq,PXA2xxDMAState * dma,CharDriverState * chr)1998 static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
1999                 qemu_irq irq, PXA2xxDMAState *dma,
2000                 CharDriverState *chr)
2001 {
2002     int iomemtype;
2003     PXA2xxFIrState *s = (PXA2xxFIrState *)
2004             qemu_mallocz(sizeof(PXA2xxFIrState));
2005 
2006     s->irq = irq;
2007     s->dma = dma;
2008     s->chr = chr;
2009 
2010     pxa2xx_fir_reset(s);
2011 
2012     iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
2013                     pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN);
2014     cpu_register_physical_memory(base, 0x1000, iomemtype);
2015 
2016     if (chr)
2017         qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2018                         pxa2xx_fir_rx, pxa2xx_fir_event, s);
2019 
2020     register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2021                     pxa2xx_fir_load, s);
2022 
2023     return s;
2024 }
2025 
pxa2xx_reset(void * opaque,int line,int level)2026 static void pxa2xx_reset(void *opaque, int line, int level)
2027 {
2028     PXA2xxState *s = (PXA2xxState *) opaque;
2029 
2030     if (level && (s->pm_regs[PCFR >> 2] & 0x10)) {	/* GPR_EN */
2031         cpu_reset(s->env);
2032         /* TODO: reset peripherals */
2033     }
2034 }
2035 
2036 /* Initialise a PXA270 integrated chip (ARM based core).  */
pxa270_init(unsigned int sdram_size,const char * revision)2037 PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
2038 {
2039     PXA2xxState *s;
2040     int iomemtype, i;
2041     DriveInfo *dinfo;
2042     s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2043 
2044     if (revision && strncmp(revision, "pxa27", 5)) {
2045         fprintf(stderr, "Machine requires a PXA27x processor.\n");
2046         exit(1);
2047     }
2048     if (!revision)
2049         revision = "pxa270";
2050 
2051     s->env = cpu_init(revision);
2052     if (!s->env) {
2053         fprintf(stderr, "Unable to find CPU definition\n");
2054         exit(1);
2055     }
2056     s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2057 
2058     /* SDRAM & Internal Memory Storage */
2059     cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2060                     sdram_size, qemu_ram_alloc(NULL, "pxa270.sdram",
2061                                                sdram_size) | IO_MEM_RAM);
2062     cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2063                     0x40000, qemu_ram_alloc(NULL, "pxa270.internal",
2064                                             0x40000) | IO_MEM_RAM);
2065 
2066     s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2067 
2068     s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2069 
2070     pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
2071                     s->pic[PXA27X_PIC_OST_4_11]);
2072 
2073     s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2074 
2075     dinfo = drive_get(IF_SD, 0, 0);
2076     if (!dinfo) {
2077         fprintf(stderr, "qemu: missing SecureDigital device\n");
2078         exit(1);
2079     }
2080     s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2081                               s->pic[PXA2XX_PIC_MMC], s->dma);
2082 
2083     for (i = 0; pxa270_serial[i].io_base; i ++)
2084         if (serial_hds[i])
2085 #ifdef TARGET_WORDS_BIGENDIAN
2086             serial_mm_init(pxa270_serial[i].io_base, 2,
2087                            s->pic[pxa270_serial[i].irqn], 14857000/16,
2088                            serial_hds[i], 1, 1);
2089 #else
2090             serial_mm_init(pxa270_serial[i].io_base, 2,
2091                            s->pic[pxa270_serial[i].irqn], 14857000/16,
2092                            serial_hds[i], 1, 0);
2093 #endif
2094         else
2095             break;
2096     if (serial_hds[i])
2097         s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2098                         s->dma, serial_hds[i]);
2099 
2100     s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
2101 
2102     s->cm_base = 0x41300000;
2103     s->cm_regs[CCCR >> 2] = 0x02000210;	/* 416.0 MHz */
2104     s->clkcfg = 0x00000009;		/* Turbo mode active */
2105     iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2106                     pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
2107     cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2108     register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2109 
2110     cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2111 
2112     s->mm_base = 0x48000000;
2113     s->mm_regs[MDMRS >> 2] = 0x00020002;
2114     s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2115     s->mm_regs[MECR >> 2] = 0x00000001;	/* Two PC Card sockets */
2116     iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2117                     pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
2118     cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2119     register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2120 
2121     s->pm_base = 0x40f00000;
2122     iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2123                     pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
2124     cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2125     register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2126 
2127     for (i = 0; pxa27x_ssp[i].io_base; i ++);
2128     s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2129     for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2130         DeviceState *dev;
2131         dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2132                                    s->pic[pxa27x_ssp[i].irqn]);
2133         s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2134     }
2135 
2136     if (usb_enabled) {
2137         sysbus_create_simple("sysbus-ohci", 0x4c000000,
2138                              s->pic[PXA2XX_PIC_USBH1]);
2139     }
2140 
2141     s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2142     s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2143 
2144     s->rtc_base = 0x40900000;
2145     iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
2146                     pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
2147     cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2148     pxa2xx_rtc_init(s);
2149     register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
2150                     pxa2xx_rtc_load, s);
2151 
2152     s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2153     s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2154 
2155     s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2156 
2157     s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
2158 
2159     /* GPIO1 resets the processor */
2160     /* The handler can be overridden by board-specific code */
2161     qdev_connect_gpio_out(s->gpio, 1, s->reset);
2162     return s;
2163 }
2164 
2165 /* Initialise a PXA255 integrated chip (ARM based core).  */
pxa255_init(unsigned int sdram_size)2166 PXA2xxState *pxa255_init(unsigned int sdram_size)
2167 {
2168     PXA2xxState *s;
2169     int iomemtype, i;
2170     DriveInfo *dinfo;
2171 
2172     s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2173 
2174     s->env = cpu_init("pxa255");
2175     if (!s->env) {
2176         fprintf(stderr, "Unable to find CPU definition\n");
2177         exit(1);
2178     }
2179     s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2180 
2181     /* SDRAM & Internal Memory Storage */
2182     cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2183                     qemu_ram_alloc(NULL, "pxa255.sdram",
2184                                    sdram_size) | IO_MEM_RAM);
2185     cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2186                     qemu_ram_alloc(NULL, "pxa255.internal",
2187                                    PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
2188 
2189     s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2190 
2191     s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2192 
2193     pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
2194 
2195     s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2196 
2197     dinfo = drive_get(IF_SD, 0, 0);
2198     if (!dinfo) {
2199         fprintf(stderr, "qemu: missing SecureDigital device\n");
2200         exit(1);
2201     }
2202     s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2203                               s->pic[PXA2XX_PIC_MMC], s->dma);
2204 
2205     for (i = 0; pxa255_serial[i].io_base; i ++)
2206         if (serial_hds[i]) {
2207 #ifdef TARGET_WORDS_BIGENDIAN
2208             serial_mm_init(pxa255_serial[i].io_base, 2,
2209                            s->pic[pxa255_serial[i].irqn], 14745600/16,
2210                            serial_hds[i], 1, 1);
2211 #else
2212             serial_mm_init(pxa255_serial[i].io_base, 2,
2213                            s->pic[pxa255_serial[i].irqn], 14745600/16,
2214                            serial_hds[i], 1, 0);
2215 #endif
2216         } else {
2217             break;
2218         }
2219     if (serial_hds[i])
2220         s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2221                         s->dma, serial_hds[i]);
2222 
2223     s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
2224 
2225     s->cm_base = 0x41300000;
2226     s->cm_regs[CCCR >> 2] = 0x02000210;	/* 416.0 MHz */
2227     s->clkcfg = 0x00000009;		/* Turbo mode active */
2228     iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2229                     pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
2230     cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2231     register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2232 
2233     cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2234 
2235     s->mm_base = 0x48000000;
2236     s->mm_regs[MDMRS >> 2] = 0x00020002;
2237     s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2238     s->mm_regs[MECR >> 2] = 0x00000001;	/* Two PC Card sockets */
2239     iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2240                     pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
2241     cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2242     register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2243 
2244     s->pm_base = 0x40f00000;
2245     iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2246                     pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
2247     cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2248     register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2249 
2250     for (i = 0; pxa255_ssp[i].io_base; i ++);
2251     s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2252     for (i = 0; pxa255_ssp[i].io_base; i ++) {
2253         DeviceState *dev;
2254         dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2255                                    s->pic[pxa255_ssp[i].irqn]);
2256         s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2257     }
2258 
2259     if (usb_enabled) {
2260         sysbus_create_simple("sysbus-ohci", 0x4c000000,
2261                              s->pic[PXA2XX_PIC_USBH1]);
2262     }
2263 
2264     s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2265     s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2266 
2267     s->rtc_base = 0x40900000;
2268     iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
2269                     pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
2270     cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2271     pxa2xx_rtc_init(s);
2272     register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
2273                     pxa2xx_rtc_load, s);
2274 
2275     s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2276     s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2277 
2278     s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2279 
2280     /* GPIO1 resets the processor */
2281     /* The handler can be overridden by board-specific code */
2282     qdev_connect_gpio_out(s->gpio, 1, s->reset);
2283     return s;
2284 }
2285 
pxa2xx_register_devices(void)2286 static void pxa2xx_register_devices(void)
2287 {
2288     i2c_register_slave(&pxa2xx_i2c_slave_info);
2289     sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init);
2290 }
2291 
2292 device_init(pxa2xx_register_devices)
2293