xref: /illumos-kvm-cmd/hw/pci.h (revision 68396ea9)
1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
3 
4 #include "qemu-common.h"
5 #include "qobject.h"
6 
7 #include "qdev.h"
8 
9 struct kvm_irq_routing_entry;
10 
11 /* PCI includes legacy ISA access.  */
12 #include "isa.h"
13 
14 #include "pcie.h"
15 
16 /* PCI bus */
17 
18 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
19 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
20 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
21 #define PCI_FUNC_MAX            8
22 
23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
24 #include "pci_ids.h"
25 
26 /* QEMU-specific Vendor and Device ID definitions */
27 
28 /* IBM (0x1014) */
29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
31 
32 /* Hitachi (0x1054) */
33 #define PCI_VENDOR_ID_HITACHI            0x1054
34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
35 
36 /* Apple (0x106b) */
37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
42 
43 /* Realtek (0x10ec) */
44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
45 
46 /* Xilinx (0x10ee) */
47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
48 
49 /* Marvell (0x11ab) */
50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
51 
52 /* QEMU/Bochs VGA (0x1234) */
53 #define PCI_VENDOR_ID_QEMU               0x1234
54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
55 
56 /* VMWare (0x15ad) */
57 #define PCI_VENDOR_ID_VMWARE             0x15ad
58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
63 
64 /* Intel (0x8086) */
65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
68 
69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
73 
74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
78 
79 #define FMT_PCIBUS                      PRIx64
80 
81 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
82                                 uint32_t address, uint32_t data, int len);
83 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
84                                    uint32_t address, int len);
85 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
86                                 pcibus_t addr, pcibus_t size, int type);
87 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
88 
89 typedef struct PCIIORegion {
90     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
91 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
92     pcibus_t size;
93     pcibus_t filtered_size;
94     uint8_t type;
95     PCIMapIORegionFunc *map_func;
96 } PCIIORegion;
97 
98 #define PCI_ROM_SLOT 6
99 #define PCI_NUM_REGIONS 7
100 
101 #include "pci_regs.h"
102 
103 /* PCI HEADER_TYPE */
104 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
105 
106 /* Size of the standard PCI config header */
107 #define PCI_CONFIG_HEADER_SIZE 0x40
108 /* Size of the standard PCI config space */
109 #define PCI_CONFIG_SPACE_SIZE 0x100
110 /* Size of the standart PCIe config space: 4KB */
111 #define PCIE_CONFIG_SPACE_SIZE  0x1000
112 
113 #define PCI_NUM_PINS 4 /* A-D */
114 
115 /* Bits in cap_present field. */
116 enum {
117     QEMU_PCI_CAP_MSI = 0x1,
118     QEMU_PCI_CAP_MSIX = 0x2,
119     QEMU_PCI_CAP_EXPRESS = 0x4,
120 
121     /* multifunction capable device */
122 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
123     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
124 
125     /* command register SERR bit enabled */
126 #define QEMU_PCI_CAP_SERR_BITNR 4
127     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
128 };
129 
130 typedef int (*msix_mask_notifier_func)(PCIDevice *, unsigned vector,
131 				       int masked);
132 
133 struct kvm_msix_message {
134     uint32_t gsi;
135     uint32_t addr_lo;
136     uint32_t addr_hi;
137     uint32_t data;
138 };
139 
140 struct PCIDevice {
141     DeviceState qdev;
142     /* PCI config space */
143     uint8_t *config;
144 
145     /* Used to enable config checks on load. Note that writeable bits are
146      * never checked even if set in cmask. */
147     uint8_t *cmask;
148 
149     /* Used to implement R/W bytes */
150     uint8_t *wmask;
151 
152     /* Used to implement RW1C(Write 1 to Clear) bytes */
153     uint8_t *w1cmask;
154 
155     /* Used to allocate config space and track capabilities. */
156     uint8_t *config_map;
157 
158     /* the following fields are read only */
159     PCIBus *bus;
160     uint32_t devfn;
161     char name[64];
162     PCIIORegion io_regions[PCI_NUM_REGIONS];
163 
164     /* do not access the following fields */
165     PCIConfigReadFunc *config_read;
166     PCIConfigWriteFunc *config_write;
167 
168     /* IRQ objects for the INTA-INTD pins.  */
169     qemu_irq *irq;
170 
171     /* Current IRQ levels.  Used internally by the generic PCI code.  */
172     uint8_t irq_state;
173 
174     /* Capability bits */
175     uint32_t cap_present;
176 
177     /* Offset of MSI-X capability in config space */
178     uint8_t msix_cap;
179 
180     /* MSI-X entries */
181     int msix_entries_nr;
182 
183     /* Space to store MSIX table */
184     uint8_t *msix_table_page;
185     /* MMIO index used to map MSIX table and pending bit entries. */
186     int msix_mmio_index;
187     /* Reference-count for entries actually in use by driver. */
188     unsigned *msix_entry_used;
189     /* Region including the MSI-X table */
190     uint32_t msix_bar_size;
191     /* Version id needed for VMState */
192     int32_t version_id;
193 
194     /* Offset of MSI capability in config space */
195     uint8_t msi_cap;
196 
197     /* PCI Express */
198     PCIExpressDevice exp;
199 
200     /* Location of option rom */
201     char *romfile;
202     ram_addr_t rom_offset;
203     uint32_t rom_bar;
204 
205     /* How much space does an MSIX table need. */
206     /* The spec requires giving the table structure
207      * a 4K aligned region all by itself. Align it to
208      * target pages so that drivers can do passthrough
209      * on the rest of the region. */
210     target_phys_addr_t msix_page_size;
211 
212     struct kvm_msix_message *msix_irq_entries;
213 
214     msix_mask_notifier_func msix_mask_notifier;
215 };
216 
217 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
218                                int instance_size, int devfn,
219                                PCIConfigReadFunc *config_read,
220                                PCIConfigWriteFunc *config_write);
221 
222 void pci_register_bar(PCIDevice *pci_dev, int region_num,
223                             pcibus_t size, uint8_t type,
224                             PCIMapIORegionFunc *map_func);
225 
226 void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr,
227                         pcibus_t size, int type);
228 
229 int pci_map_irq(PCIDevice *pci_dev, int pin);
230 
231 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
232                        uint8_t offset, uint8_t size);
233 
234 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
235 
236 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
237 
238 uint32_t pci_default_read_config(PCIDevice *d,
239                                  uint32_t address, int len);
240 void pci_default_write_config(PCIDevice *d,
241                               uint32_t address, uint32_t val, int len);
242 void pci_device_save(PCIDevice *s, QEMUFile *f);
243 int pci_device_load(PCIDevice *s, QEMUFile *f);
244 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
245 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
246 
247 typedef enum {
248     PCI_HOTPLUG_DISABLED,
249     PCI_HOTPLUG_ENABLED,
250     PCI_COLDPLUG_ENABLED,
251 } PCIHotplugState;
252 
253 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
254                               PCIHotplugState state);
255 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
256                          const char *name, int devfn_min);
257 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
258 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
259                   void *irq_opaque, int nirq);
260 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
261 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
262                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
263                          void *irq_opaque, int devfn_min, int nirq);
264 void pci_device_reset(PCIDevice *dev);
265 void pci_bus_reset(PCIBus *bus);
266 
267 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
268 
269 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
270                         const char *default_devaddr);
271 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
272                                const char *default_devaddr);
273 int pci_bus_num(PCIBus *s);
274 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
275 PCIBus *pci_find_root_bus(int domain);
276 int pci_find_domain(const PCIBus *bus);
277 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
278 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
279 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
280 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
281 
282 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
283                       unsigned int *slotp, unsigned int *funcp);
284 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
285                      unsigned *slotp);
286 
287 int pci_parse_host_devaddr(const char *addr, int *segp, int *busp,
288                            int *slotp, int *funcp);
289 
290 void do_pci_info_print(Monitor *mon, const QObject *data);
291 void do_pci_info(Monitor *mon, QObject **ret_data);
292 void pci_bridge_update_mappings(PCIBus *b);
293 
294 void pci_device_deassert_intx(PCIDevice *dev);
295 
296 static inline void
pci_set_byte(uint8_t * config,uint8_t val)297 pci_set_byte(uint8_t *config, uint8_t val)
298 {
299     *config = val;
300 }
301 
302 static inline uint8_t
pci_get_byte(const uint8_t * config)303 pci_get_byte(const uint8_t *config)
304 {
305     return *config;
306 }
307 
308 static inline void
pci_set_word(uint8_t * config,uint16_t val)309 pci_set_word(uint8_t *config, uint16_t val)
310 {
311     cpu_to_le16wu((uint16_t *)config, val);
312 }
313 
314 static inline uint16_t
pci_get_word(const uint8_t * config)315 pci_get_word(const uint8_t *config)
316 {
317     return le16_to_cpupu((const uint16_t *)config);
318 }
319 
320 static inline void
pci_set_long(uint8_t * config,uint32_t val)321 pci_set_long(uint8_t *config, uint32_t val)
322 {
323     cpu_to_le32wu((uint32_t *)config, val);
324 }
325 
326 static inline uint32_t
pci_get_long(const uint8_t * config)327 pci_get_long(const uint8_t *config)
328 {
329     return le32_to_cpupu((const uint32_t *)config);
330 }
331 
332 static inline void
pci_set_quad(uint8_t * config,uint64_t val)333 pci_set_quad(uint8_t *config, uint64_t val)
334 {
335     cpu_to_le64w((uint64_t *)config, val);
336 }
337 
338 static inline uint64_t
pci_get_quad(const uint8_t * config)339 pci_get_quad(const uint8_t *config)
340 {
341     return le64_to_cpup((const uint64_t *)config);
342 }
343 
344 static inline void
pci_config_set_vendor_id(uint8_t * pci_config,uint16_t val)345 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
346 {
347     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
348 }
349 
350 static inline void
pci_config_set_device_id(uint8_t * pci_config,uint16_t val)351 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
352 {
353     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
354 }
355 
356 static inline void
pci_config_set_revision(uint8_t * pci_config,uint8_t val)357 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
358 {
359     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
360 }
361 
362 static inline void
pci_config_set_class(uint8_t * pci_config,uint16_t val)363 pci_config_set_class(uint8_t *pci_config, uint16_t val)
364 {
365     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
366 }
367 
368 static inline void
pci_config_set_prog_interface(uint8_t * pci_config,uint8_t val)369 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
370 {
371     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
372 }
373 
374 static inline void
pci_config_set_interrupt_pin(uint8_t * pci_config,uint8_t val)375 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
376 {
377     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
378 }
379 
380 /*
381  * helper functions to do bit mask operation on configuration space.
382  * Just to set bit, use test-and-set and discard returned value.
383  * Just to clear bit, use test-and-clear and discard returned value.
384  * NOTE: They aren't atomic.
385  */
386 static inline uint8_t
pci_byte_test_and_clear_mask(uint8_t * config,uint8_t mask)387 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
388 {
389     uint8_t val = pci_get_byte(config);
390     pci_set_byte(config, val & ~mask);
391     return val & mask;
392 }
393 
394 static inline uint8_t
pci_byte_test_and_set_mask(uint8_t * config,uint8_t mask)395 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
396 {
397     uint8_t val = pci_get_byte(config);
398     pci_set_byte(config, val | mask);
399     return val & mask;
400 }
401 
402 static inline uint16_t
pci_word_test_and_clear_mask(uint8_t * config,uint16_t mask)403 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
404 {
405     uint16_t val = pci_get_word(config);
406     pci_set_word(config, val & ~mask);
407     return val & mask;
408 }
409 
410 static inline uint16_t
pci_word_test_and_set_mask(uint8_t * config,uint16_t mask)411 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
412 {
413     uint16_t val = pci_get_word(config);
414     pci_set_word(config, val | mask);
415     return val & mask;
416 }
417 
418 static inline uint32_t
pci_long_test_and_clear_mask(uint8_t * config,uint32_t mask)419 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
420 {
421     uint32_t val = pci_get_long(config);
422     pci_set_long(config, val & ~mask);
423     return val & mask;
424 }
425 
426 static inline uint32_t
pci_long_test_and_set_mask(uint8_t * config,uint32_t mask)427 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
428 {
429     uint32_t val = pci_get_long(config);
430     pci_set_long(config, val | mask);
431     return val & mask;
432 }
433 
434 static inline uint64_t
pci_quad_test_and_clear_mask(uint8_t * config,uint64_t mask)435 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
436 {
437     uint64_t val = pci_get_quad(config);
438     pci_set_quad(config, val & ~mask);
439     return val & mask;
440 }
441 
442 static inline uint64_t
pci_quad_test_and_set_mask(uint8_t * config,uint64_t mask)443 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
444 {
445     uint64_t val = pci_get_quad(config);
446     pci_set_quad(config, val | mask);
447     return val & mask;
448 }
449 
450 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
451 typedef struct {
452     DeviceInfo qdev;
453     pci_qdev_initfn init;
454     PCIUnregisterFunc *exit;
455     PCIConfigReadFunc *config_read;
456     PCIConfigWriteFunc *config_write;
457 
458     /*
459      * pci-to-pci bridge or normal device.
460      * This doesn't mean pci host switch.
461      * When card bus bridge is supported, this would be enhanced.
462      */
463     int is_bridge;
464 
465     /* pcie stuff */
466     int is_express;   /* is this device pci express? */
467 
468     /* device isn't hot-pluggable */
469     int no_hotplug;
470 
471     /* rom bar */
472     const char *romfile;
473 } PCIDeviceInfo;
474 
475 void pci_qdev_register(PCIDeviceInfo *info);
476 void pci_qdev_register_many(PCIDeviceInfo *info);
477 
478 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
479                                     const char *name);
480 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
481                                            bool multifunction,
482                                            const char *name);
483 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
484 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
485 
pci_is_express(const PCIDevice * d)486 static inline int pci_is_express(const PCIDevice *d)
487 {
488     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
489 }
490 
pci_config_size(const PCIDevice * d)491 static inline uint32_t pci_config_size(const PCIDevice *d)
492 {
493     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
494 }
495 
496 #endif
497