xref: /illumos-kvm-cmd/hw/ide/via.c (revision 68396ea9)
1 /*
2  * QEMU IDE Emulation: PCI VIA82C686B support.
3  *
4  * Copyright (c) 2003 Fabrice Bellard
5  * Copyright (c) 2006 Openedhand Ltd.
6  * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  */
26 #include <hw/hw.h>
27 #include <hw/pc.h>
28 #include <hw/pci.h>
29 #include <hw/isa.h>
30 #include "block.h"
31 #include "block_int.h"
32 #include "sysemu.h"
33 #include "dma.h"
34 
35 #include <hw/ide/pci.h>
36 
bmdma_readb(void * opaque,uint32_t addr)37 static uint32_t bmdma_readb(void *opaque, uint32_t addr)
38 {
39     BMDMAState *bm = opaque;
40     uint32_t val;
41 
42     switch (addr & 3) {
43     case 0:
44         val = bm->cmd;
45         break;
46     case 2:
47         val = bm->status;
48         break;
49     default:
50         val = 0xff;
51         break;
52     }
53 #ifdef DEBUG_IDE
54     printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
55 #endif
56     return val;
57 }
58 
bmdma_writeb(void * opaque,uint32_t addr,uint32_t val)59 static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
60 {
61     BMDMAState *bm = opaque;
62 #ifdef DEBUG_IDE
63     printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
64 #endif
65     switch (addr & 3) {
66     case 2:
67         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
68         break;
69     default:;
70     }
71 }
72 
bmdma_map(PCIDevice * pci_dev,int region_num,pcibus_t addr,pcibus_t size,int type)73 static void bmdma_map(PCIDevice *pci_dev, int region_num,
74                     pcibus_t addr, pcibus_t size, int type)
75 {
76     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
77     int i;
78 
79     for(i = 0;i < 2; i++) {
80         BMDMAState *bm = &d->bmdma[i];
81 
82         register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
83 
84         register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
85         register_ioport_read(addr, 4, 1, bmdma_readb, bm);
86 
87         iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4);
88         ioport_register(&bm->addr_ioport);
89         addr += 8;
90     }
91 }
92 
via_reset(void * opaque)93 static void via_reset(void *opaque)
94 {
95     PCIIDEState *d = opaque;
96     uint8_t *pci_conf = d->dev.config;
97     int i;
98 
99     for (i = 0; i < 2; i++) {
100         ide_bus_reset(&d->bus[i]);
101     }
102 
103     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
104     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
105                  PCI_STATUS_DEVSEL_MEDIUM);
106 
107     pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
108     pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
109     pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
110     pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
111     pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
112     pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
113 
114     /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
115     pci_set_long(pci_conf + 0x40, 0x0a090600);
116     /* IDE misc configuration 1/2/3 */
117     pci_set_long(pci_conf + 0x44, 0x00c00068);
118     /* IDE Timing control */
119     pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
120     /* IDE Address Setup Time */
121     pci_set_long(pci_conf + 0x4c, 0x000000ff);
122     /* UltraDMA Extended Timing Control*/
123     pci_set_long(pci_conf + 0x50, 0x07070707);
124     /* UltraDMA FIFO Control */
125     pci_set_long(pci_conf + 0x54, 0x00000004);
126     /* IDE primary sector size */
127     pci_set_long(pci_conf + 0x60, 0x00000200);
128     /* IDE secondary sector size */
129     pci_set_long(pci_conf + 0x68, 0x00000200);
130     /* PCI PM Block */
131     pci_set_long(pci_conf + 0xc0, 0x00020001);
132 }
133 
vt82c686b_init_ports(PCIIDEState * d)134 static void vt82c686b_init_ports(PCIIDEState *d) {
135     int i;
136     struct {
137         int iobase;
138         int iobase2;
139         int isairq;
140     } port_info[] = {
141         {0x1f0, 0x3f6, 14},
142         {0x170, 0x376, 15},
143     };
144 
145     for (i = 0; i < 2; i++) {
146         ide_bus_new(&d->bus[i], &d->dev.qdev, i);
147         ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
148         ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));
149 
150         bmdma_init(&d->bus[i], &d->bmdma[i]);
151         d->bmdma[i].bus = &d->bus[i];
152         qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
153                                          &d->bmdma[i].dma);
154     }
155 }
156 
157 /* via ide func */
vt82c686b_ide_initfn(PCIDevice * dev)158 static int vt82c686b_ide_initfn(PCIDevice *dev)
159 {
160     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);;
161     uint8_t *pci_conf = d->dev.config;
162 
163     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
164     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_IDE);
165     pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
166     pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
167     pci_config_set_revision(pci_conf,0x06); /* Revision 0.6 */
168     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
169 
170     qemu_register_reset(via_reset, d);
171     pci_register_bar(&d->dev, 4, 0x10,
172                            PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
173 
174     vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
175 
176     vt82c686b_init_ports(d);
177 
178     return 0;
179 }
180 
vt82c686b_ide_init(PCIBus * bus,DriveInfo ** hd_table,int devfn)181 void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
182 {
183     PCIDevice *dev;
184 
185     dev = pci_create_simple(bus, devfn, "via-ide");
186     pci_ide_create_devs(dev, hd_table);
187 }
188 
189 static PCIDeviceInfo via_ide_info = {
190     .qdev.name    = "via-ide",
191     .qdev.size    = sizeof(PCIIDEState),
192     .qdev.no_user = 1,
193     .init         = vt82c686b_ide_initfn,
194 };
195 
via_ide_register(void)196 static void via_ide_register(void)
197 {
198     pci_qdev_register(&via_ide_info);
199 }
200 device_init(via_ide_register);
201