xref: /illumos-kvm-cmd/hw/ide/piix.c (revision 68396ea9)
1 /*
2  * QEMU IDE Emulation: PCI PIIX3/4 support.
3  *
4  * Copyright (c) 2003 Fabrice Bellard
5  * Copyright (c) 2006 Openedhand Ltd.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 #include <hw/hw.h>
26 #include <hw/pc.h>
27 #include <hw/pci.h>
28 #include <hw/isa.h>
29 #include "block.h"
30 #include "block_int.h"
31 #include "sysemu.h"
32 #include "dma.h"
33 
34 #include <hw/ide/pci.h>
35 
bmdma_readb(void * opaque,uint32_t addr)36 static uint32_t bmdma_readb(void *opaque, uint32_t addr)
37 {
38     BMDMAState *bm = opaque;
39     uint32_t val;
40 
41     switch(addr & 3) {
42     case 0:
43         val = bm->cmd;
44         break;
45     case 2:
46         val = bm->status;
47         break;
48     default:
49         val = 0xff;
50         break;
51     }
52 #ifdef DEBUG_IDE
53     printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
54 #endif
55     return val;
56 }
57 
bmdma_writeb(void * opaque,uint32_t addr,uint32_t val)58 static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
59 {
60     BMDMAState *bm = opaque;
61 #ifdef DEBUG_IDE
62     printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
63 #endif
64     switch(addr & 3) {
65     case 2:
66         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
67         break;
68     }
69 }
70 
bmdma_map(PCIDevice * pci_dev,int region_num,pcibus_t addr,pcibus_t size,int type)71 static void bmdma_map(PCIDevice *pci_dev, int region_num,
72                     pcibus_t addr, pcibus_t size, int type)
73 {
74     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
75     int i;
76 
77     for(i = 0;i < 2; i++) {
78         BMDMAState *bm = &d->bmdma[i];
79 
80         register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
81 
82         register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
83         register_ioport_read(addr, 4, 1, bmdma_readb, bm);
84 
85         iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4);
86         ioport_register(&bm->addr_ioport);
87         addr += 8;
88     }
89 }
90 
piix3_reset(void * opaque)91 static void piix3_reset(void *opaque)
92 {
93     PCIIDEState *d = opaque;
94     uint8_t *pci_conf = d->dev.config;
95     int i;
96 
97     for (i = 0; i < 2; i++) {
98         ide_bus_reset(&d->bus[i]);
99     }
100 
101     /* TODO: this is the default. do not override. */
102     pci_conf[PCI_COMMAND] = 0x00;
103     /* TODO: this is the default. do not override. */
104     pci_conf[PCI_COMMAND + 1] = 0x00;
105     /* TODO: use pci_set_word */
106     pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
107     pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
108     pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
109 }
110 
pci_piix_init_ports(PCIIDEState * d)111 static void pci_piix_init_ports(PCIIDEState *d) {
112     int i;
113     struct {
114         int iobase;
115         int iobase2;
116         int isairq;
117     } port_info[] = {
118         {0x1f0, 0x3f6, 14},
119         {0x170, 0x376, 15},
120     };
121 
122     for (i = 0; i < 2; i++) {
123         ide_bus_new(&d->bus[i], &d->dev.qdev, i);
124         ide_init_ioport(&d->bus[i], port_info[i].iobase, port_info[i].iobase2);
125         ide_init2(&d->bus[i], isa_get_irq(port_info[i].isairq));
126 
127         bmdma_init(&d->bus[i], &d->bmdma[i]);
128         d->bmdma[i].bus = &d->bus[i];
129         qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
130                                          &d->bmdma[i].dma);
131     }
132 }
133 
pci_piix_ide_initfn(PCIIDEState * d)134 static int pci_piix_ide_initfn(PCIIDEState *d)
135 {
136     uint8_t *pci_conf = d->dev.config;
137 
138     pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
139     pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
140 
141     qemu_register_reset(piix3_reset, d);
142 
143     pci_register_bar(&d->dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
144 
145     vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
146 
147     pci_piix_init_ports(d);
148 
149     return 0;
150 }
151 
pci_piix3_ide_initfn(PCIDevice * dev)152 static int pci_piix3_ide_initfn(PCIDevice *dev)
153 {
154     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
155 
156     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
157     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1);
158     return pci_piix_ide_initfn(d);
159 }
160 
pci_piix4_ide_initfn(PCIDevice * dev)161 static int pci_piix4_ide_initfn(PCIDevice *dev)
162 {
163     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
164 
165     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
166     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB);
167     return pci_piix_ide_initfn(d);
168 }
169 
170 /* hd_table must contain 4 block drivers */
171 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
pci_piix3_ide_init(PCIBus * bus,DriveInfo ** hd_table,int devfn)172 PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
173 {
174     PCIDevice *dev;
175 
176     dev = pci_create_simple(bus, devfn, "piix3-ide");
177     pci_ide_create_devs(dev, hd_table);
178     return dev;
179 }
180 
181 /* hd_table must contain 4 block drivers */
182 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
pci_piix4_ide_init(PCIBus * bus,DriveInfo ** hd_table,int devfn)183 PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
184 {
185     PCIDevice *dev;
186 
187     dev = pci_create_simple(bus, devfn, "piix4-ide");
188     pci_ide_create_devs(dev, hd_table);
189     return dev;
190 }
191 
192 static PCIDeviceInfo piix_ide_info[] = {
193     {
194         .qdev.name    = "piix3-ide",
195         .qdev.size    = sizeof(PCIIDEState),
196         .qdev.no_user = 1,
197         .no_hotplug   = 1,
198         .init         = pci_piix3_ide_initfn,
199     },{
200         .qdev.name    = "piix4-ide",
201         .qdev.size    = sizeof(PCIIDEState),
202         .qdev.no_user = 1,
203         .no_hotplug   = 1,
204         .init         = pci_piix4_ide_initfn,
205     },{
206         /* end of list */
207     }
208 };
209 
piix_ide_register(void)210 static void piix_ide_register(void)
211 {
212     pci_qdev_register_many(piix_ide_info);
213 }
214 device_init(piix_ide_register);
215