xref: /illumos-kvm-cmd/hw/es1370.c (revision 68396ea9)
1 /*
2  * QEMU ES1370 emulation
3  *
4  * Copyright (c) 2005 Vassili Karpov (malc)
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 /* #define DEBUG_ES1370 */
26 /* #define VERBOSE_ES1370 */
27 #define SILENT_ES1370
28 
29 #include "hw.h"
30 #include "audiodev.h"
31 #include "audio/audio.h"
32 #include "pci.h"
33 
34 /* Missing stuff:
35    SCTRL_P[12](END|ST)INC
36    SCTRL_P1SCTRLD
37    SCTRL_P2DACSEN
38    CTRL_DAC_SYNC
39    MIDI
40    non looped mode
41    surely more
42 */
43 
44 /*
45   Following macros and samplerate array were copied verbatim from
46   Linux kernel 2.4.30: drivers/sound/es1370.c
47 
48   Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
49 */
50 
51 /* Start blatant GPL violation */
52 
53 #define ES1370_REG_CONTROL        0x00
54 #define ES1370_REG_STATUS         0x04
55 #define ES1370_REG_UART_DATA      0x08
56 #define ES1370_REG_UART_STATUS    0x09
57 #define ES1370_REG_UART_CONTROL   0x09
58 #define ES1370_REG_UART_TEST      0x0a
59 #define ES1370_REG_MEMPAGE        0x0c
60 #define ES1370_REG_CODEC          0x10
61 #define ES1370_REG_SERIAL_CONTROL 0x20
62 #define ES1370_REG_DAC1_SCOUNT    0x24
63 #define ES1370_REG_DAC2_SCOUNT    0x28
64 #define ES1370_REG_ADC_SCOUNT     0x2c
65 
66 #define ES1370_REG_DAC1_FRAMEADR    0xc30
67 #define ES1370_REG_DAC1_FRAMECNT    0xc34
68 #define ES1370_REG_DAC2_FRAMEADR    0xc38
69 #define ES1370_REG_DAC2_FRAMECNT    0xc3c
70 #define ES1370_REG_ADC_FRAMEADR     0xd30
71 #define ES1370_REG_ADC_FRAMECNT     0xd34
72 #define ES1370_REG_PHANTOM_FRAMEADR 0xd38
73 #define ES1370_REG_PHANTOM_FRAMECNT 0xd3c
74 
75 static const unsigned dac1_samplerate[] = { 5512, 11025, 22050, 44100 };
76 
77 #define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2)
78 #define DAC2_DIVTOSR(x) (1411200/((x)+2))
79 
80 #define CTRL_ADC_STOP   0x80000000  /* 1 = ADC stopped */
81 #define CTRL_XCTL1      0x40000000  /* electret mic bias */
82 #define CTRL_OPEN       0x20000000  /* no function, can be read and written */
83 #define CTRL_PCLKDIV    0x1fff0000  /* ADC/DAC2 clock divider */
84 #define CTRL_SH_PCLKDIV 16
85 #define CTRL_MSFMTSEL   0x00008000  /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
86 #define CTRL_M_SBB      0x00004000  /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
87 #define CTRL_WTSRSEL    0x00003000  /* DAC1 clock freq: 0=5512, 1=11025, 2=22050, 3=44100 */
88 #define CTRL_SH_WTSRSEL 12
89 #define CTRL_DAC_SYNC   0x00000800  /* 1 = DAC2 runs off DAC1 clock */
90 #define CTRL_CCB_INTRM  0x00000400  /* 1 = CCB "voice" ints enabled */
91 #define CTRL_M_CB       0x00000200  /* recording source: 0 = ADC, 1 = MPEG */
92 #define CTRL_XCTL0      0x00000100  /* 0 = Line in, 1 = Line out */
93 #define CTRL_BREQ       0x00000080  /* 1 = test mode (internal mem test) */
94 #define CTRL_DAC1_EN    0x00000040  /* enable DAC1 */
95 #define CTRL_DAC2_EN    0x00000020  /* enable DAC2 */
96 #define CTRL_ADC_EN     0x00000010  /* enable ADC */
97 #define CTRL_UART_EN    0x00000008  /* enable MIDI uart */
98 #define CTRL_JYSTK_EN   0x00000004  /* enable Joystick port (presumably at address 0x200) */
99 #define CTRL_CDC_EN     0x00000002  /* enable serial (CODEC) interface */
100 #define CTRL_SERR_DIS   0x00000001  /* 1 = disable PCI SERR signal */
101 
102 #define STAT_INTR       0x80000000  /* wired or of all interrupt bits */
103 #define STAT_CSTAT      0x00000400  /* 1 = codec busy or codec write in progress */
104 #define STAT_CBUSY      0x00000200  /* 1 = codec busy */
105 #define STAT_CWRIP      0x00000100  /* 1 = codec write in progress */
106 #define STAT_VC         0x00000060  /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
107 #define STAT_SH_VC      5
108 #define STAT_MCCB       0x00000010  /* CCB int pending */
109 #define STAT_UART       0x00000008  /* UART int pending */
110 #define STAT_DAC1       0x00000004  /* DAC1 int pending */
111 #define STAT_DAC2       0x00000002  /* DAC2 int pending */
112 #define STAT_ADC        0x00000001  /* ADC int pending */
113 
114 #define USTAT_RXINT     0x80        /* UART rx int pending */
115 #define USTAT_TXINT     0x04        /* UART tx int pending */
116 #define USTAT_TXRDY     0x02        /* UART tx ready */
117 #define USTAT_RXRDY     0x01        /* UART rx ready */
118 
119 #define UCTRL_RXINTEN   0x80        /* 1 = enable RX ints */
120 #define UCTRL_TXINTEN   0x60        /* TX int enable field mask */
121 #define UCTRL_ENA_TXINT 0x20        /* enable TX int */
122 #define UCTRL_CNTRL     0x03        /* control field */
123 #define UCTRL_CNTRL_SWR 0x03        /* software reset command */
124 
125 #define SCTRL_P2ENDINC    0x00380000  /*  */
126 #define SCTRL_SH_P2ENDINC 19
127 #define SCTRL_P2STINC     0x00070000  /*  */
128 #define SCTRL_SH_P2STINC  16
129 #define SCTRL_R1LOOPSEL   0x00008000  /* 0 = loop mode */
130 #define SCTRL_P2LOOPSEL   0x00004000  /* 0 = loop mode */
131 #define SCTRL_P1LOOPSEL   0x00002000  /* 0 = loop mode */
132 #define SCTRL_P2PAUSE     0x00001000  /* 1 = pause mode */
133 #define SCTRL_P1PAUSE     0x00000800  /* 1 = pause mode */
134 #define SCTRL_R1INTEN     0x00000400  /* enable interrupt */
135 #define SCTRL_P2INTEN     0x00000200  /* enable interrupt */
136 #define SCTRL_P1INTEN     0x00000100  /* enable interrupt */
137 #define SCTRL_P1SCTRLD    0x00000080  /* reload sample count register for DAC1 */
138 #define SCTRL_P2DACSEN    0x00000040  /* 1 = DAC2 play back last sample when disabled */
139 #define SCTRL_R1SEB       0x00000020  /* 1 = 16bit */
140 #define SCTRL_R1SMB       0x00000010  /* 1 = stereo */
141 #define SCTRL_R1FMT       0x00000030  /* format mask */
142 #define SCTRL_SH_R1FMT    4
143 #define SCTRL_P2SEB       0x00000008  /* 1 = 16bit */
144 #define SCTRL_P2SMB       0x00000004  /* 1 = stereo */
145 #define SCTRL_P2FMT       0x0000000c  /* format mask */
146 #define SCTRL_SH_P2FMT    2
147 #define SCTRL_P1SEB       0x00000002  /* 1 = 16bit */
148 #define SCTRL_P1SMB       0x00000001  /* 1 = stereo */
149 #define SCTRL_P1FMT       0x00000003  /* format mask */
150 #define SCTRL_SH_P1FMT    0
151 
152 /* End blatant GPL violation */
153 
154 #define NB_CHANNELS 3
155 #define DAC1_CHANNEL 0
156 #define DAC2_CHANNEL 1
157 #define ADC_CHANNEL 2
158 
159 #define IO_READ_PROTO(n) \
160 static uint32_t n (void *opaque, uint32_t addr)
161 #define IO_WRITE_PROTO(n) \
162 static void n (void *opaque, uint32_t addr, uint32_t val)
163 
164 static void es1370_dac1_callback (void *opaque, int free);
165 static void es1370_dac2_callback (void *opaque, int free);
166 static void es1370_adc_callback (void *opaque, int avail);
167 
168 #ifdef DEBUG_ES1370
169 
170 #define ldebug(...) AUD_log ("es1370", __VA_ARGS__)
171 
print_ctl(uint32_t val)172 static void print_ctl (uint32_t val)
173 {
174     char buf[1024];
175 
176     buf[0] = '\0';
177 #define a(n) if (val & CTRL_##n) strcat (buf, " "#n)
178     a (ADC_STOP);
179     a (XCTL1);
180     a (OPEN);
181     a (MSFMTSEL);
182     a (M_SBB);
183     a (DAC_SYNC);
184     a (CCB_INTRM);
185     a (M_CB);
186     a (XCTL0);
187     a (BREQ);
188     a (DAC1_EN);
189     a (DAC2_EN);
190     a (ADC_EN);
191     a (UART_EN);
192     a (JYSTK_EN);
193     a (CDC_EN);
194     a (SERR_DIS);
195 #undef a
196     AUD_log ("es1370", "ctl - PCLKDIV %d(DAC2 freq %d), freq %d,%s\n",
197              (val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV,
198              DAC2_DIVTOSR ((val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV),
199              dac1_samplerate[(val & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL],
200              buf);
201 }
202 
print_sctl(uint32_t val)203 static void print_sctl (uint32_t val)
204 {
205     static const char *fmt_names[] = {"8M", "8S", "16M", "16S"};
206     char buf[1024];
207 
208     buf[0] = '\0';
209 
210 #define a(n) if (val & SCTRL_##n) strcat (buf, " "#n)
211 #define b(n) if (!(val & SCTRL_##n)) strcat (buf, " "#n)
212     b (R1LOOPSEL);
213     b (P2LOOPSEL);
214     b (P1LOOPSEL);
215     a (P2PAUSE);
216     a (P1PAUSE);
217     a (R1INTEN);
218     a (P2INTEN);
219     a (P1INTEN);
220     a (P1SCTRLD);
221     a (P2DACSEN);
222     if (buf[0]) {
223         strcat (buf, "\n        ");
224     }
225     else {
226         buf[0] = ' ';
227         buf[1] = '\0';
228     }
229 #undef b
230 #undef a
231     AUD_log ("es1370",
232              "%s"
233              "p2_end_inc %d, p2_st_inc %d, r1_fmt %s, p2_fmt %s, p1_fmt %s\n",
234              buf,
235              (val & SCTRL_P2ENDINC) >> SCTRL_SH_P2ENDINC,
236              (val & SCTRL_P2STINC) >> SCTRL_SH_P2STINC,
237              fmt_names [(val >> SCTRL_SH_R1FMT) & 3],
238              fmt_names [(val >> SCTRL_SH_P2FMT) & 3],
239              fmt_names [(val >> SCTRL_SH_P1FMT) & 3]
240         );
241 }
242 #else
243 #define ldebug(...)
244 #define print_ctl(...)
245 #define print_sctl(...)
246 #endif
247 
248 #ifdef VERBOSE_ES1370
249 #define dolog(...) AUD_log ("es1370", __VA_ARGS__)
250 #else
251 #define dolog(...)
252 #endif
253 
254 #ifndef SILENT_ES1370
255 #define lwarn(...) AUD_log ("es1370: warning", __VA_ARGS__)
256 #else
257 #define lwarn(...)
258 #endif
259 
260 struct chan {
261     uint32_t shift;
262     uint32_t leftover;
263     uint32_t scount;
264     uint32_t frame_addr;
265     uint32_t frame_cnt;
266 };
267 
268 typedef struct ES1370State {
269     PCIDevice dev;
270     QEMUSoundCard card;
271     struct chan chan[NB_CHANNELS];
272     SWVoiceOut *dac_voice[2];
273     SWVoiceIn *adc_voice;
274 
275     uint32_t ctl;
276     uint32_t status;
277     uint32_t mempage;
278     uint32_t codec;
279     uint32_t sctl;
280 } ES1370State;
281 
282 struct chan_bits {
283     uint32_t ctl_en;
284     uint32_t stat_int;
285     uint32_t sctl_pause;
286     uint32_t sctl_inten;
287     uint32_t sctl_fmt;
288     uint32_t sctl_sh_fmt;
289     uint32_t sctl_loopsel;
290     void (*calc_freq) (ES1370State *s, uint32_t ctl,
291                        uint32_t *old_freq, uint32_t *new_freq);
292 };
293 
294 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
295                                    uint32_t *old_freq, uint32_t *new_freq);
296 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
297                                            uint32_t *old_freq,
298                                            uint32_t *new_freq);
299 
300 static const struct chan_bits es1370_chan_bits[] = {
301     {CTRL_DAC1_EN, STAT_DAC1, SCTRL_P1PAUSE, SCTRL_P1INTEN,
302      SCTRL_P1FMT, SCTRL_SH_P1FMT, SCTRL_P1LOOPSEL,
303      es1370_dac1_calc_freq},
304 
305     {CTRL_DAC2_EN, STAT_DAC2, SCTRL_P2PAUSE, SCTRL_P2INTEN,
306      SCTRL_P2FMT, SCTRL_SH_P2FMT, SCTRL_P2LOOPSEL,
307      es1370_dac2_and_adc_calc_freq},
308 
309     {CTRL_ADC_EN, STAT_ADC, 0, SCTRL_R1INTEN,
310      SCTRL_R1FMT, SCTRL_SH_R1FMT, SCTRL_R1LOOPSEL,
311      es1370_dac2_and_adc_calc_freq}
312 };
313 
es1370_update_status(ES1370State * s,uint32_t new_status)314 static void es1370_update_status (ES1370State *s, uint32_t new_status)
315 {
316     uint32_t level = new_status & (STAT_DAC1 | STAT_DAC2 | STAT_ADC);
317 
318     if (level) {
319         s->status = new_status | STAT_INTR;
320     }
321     else {
322         s->status = new_status & ~STAT_INTR;
323     }
324     qemu_set_irq (s->dev.irq[0], !!level);
325 }
326 
es1370_reset(ES1370State * s)327 static void es1370_reset (ES1370State *s)
328 {
329     size_t i;
330 
331     s->ctl = 1;
332     s->status = 0x60;
333     s->mempage = 0;
334     s->codec = 0;
335     s->sctl = 0;
336 
337     for (i = 0; i < NB_CHANNELS; ++i) {
338         struct chan *d = &s->chan[i];
339         d->scount = 0;
340         d->leftover = 0;
341         if (i == ADC_CHANNEL) {
342             AUD_close_in (&s->card, s->adc_voice);
343             s->adc_voice = NULL;
344         }
345         else {
346             AUD_close_out (&s->card, s->dac_voice[i]);
347             s->dac_voice[i] = NULL;
348         }
349     }
350     qemu_irq_lower (s->dev.irq[0]);
351 }
352 
es1370_maybe_lower_irq(ES1370State * s,uint32_t sctl)353 static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl)
354 {
355     uint32_t new_status = s->status;
356 
357     if (!(sctl & SCTRL_P1INTEN) && (s->sctl & SCTRL_P1INTEN)) {
358         new_status &= ~STAT_DAC1;
359     }
360 
361     if (!(sctl & SCTRL_P2INTEN) && (s->sctl & SCTRL_P2INTEN)) {
362         new_status &= ~STAT_DAC2;
363     }
364 
365     if (!(sctl & SCTRL_R1INTEN) && (s->sctl & SCTRL_R1INTEN)) {
366         new_status &= ~STAT_ADC;
367     }
368 
369     if (new_status != s->status) {
370         es1370_update_status (s, new_status);
371     }
372 }
373 
es1370_dac1_calc_freq(ES1370State * s,uint32_t ctl,uint32_t * old_freq,uint32_t * new_freq)374 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
375                                    uint32_t *old_freq, uint32_t *new_freq)
376 
377 {
378     *old_freq = dac1_samplerate[(s->ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
379     *new_freq = dac1_samplerate[(ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
380 }
381 
es1370_dac2_and_adc_calc_freq(ES1370State * s,uint32_t ctl,uint32_t * old_freq,uint32_t * new_freq)382 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
383                                            uint32_t *old_freq,
384                                            uint32_t *new_freq)
385 
386 {
387     uint32_t old_pclkdiv, new_pclkdiv;
388 
389     new_pclkdiv = (ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
390     old_pclkdiv = (s->ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
391     *new_freq = DAC2_DIVTOSR (new_pclkdiv);
392     *old_freq = DAC2_DIVTOSR (old_pclkdiv);
393 }
394 
es1370_update_voices(ES1370State * s,uint32_t ctl,uint32_t sctl)395 static void es1370_update_voices (ES1370State *s, uint32_t ctl, uint32_t sctl)
396 {
397     size_t i;
398     uint32_t old_freq, new_freq, old_fmt, new_fmt;
399 
400     for (i = 0; i < NB_CHANNELS; ++i) {
401         struct chan *d = &s->chan[i];
402         const struct chan_bits *b = &es1370_chan_bits[i];
403 
404         new_fmt = (sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
405         old_fmt = (s->sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
406 
407         b->calc_freq (s, ctl, &old_freq, &new_freq);
408 
409         if ((old_fmt != new_fmt) || (old_freq != new_freq)) {
410             d->shift = (new_fmt & 1) + (new_fmt >> 1);
411             ldebug ("channel %d, freq = %d, nchannels %d, fmt %d, shift %d\n",
412                     i,
413                     new_freq,
414                     1 << (new_fmt & 1),
415                     (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8,
416                     d->shift);
417             if (new_freq) {
418                 struct audsettings as;
419 
420                 as.freq = new_freq;
421                 as.nchannels = 1 << (new_fmt & 1);
422                 as.fmt = (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8;
423                 as.endianness = 0;
424 
425                 if (i == ADC_CHANNEL) {
426                     s->adc_voice =
427                         AUD_open_in (
428                             &s->card,
429                             s->adc_voice,
430                             "es1370.adc",
431                             s,
432                             es1370_adc_callback,
433                             &as
434                             );
435                 }
436                 else {
437                     s->dac_voice[i] =
438                         AUD_open_out (
439                             &s->card,
440                             s->dac_voice[i],
441                             i ? "es1370.dac2" : "es1370.dac1",
442                             s,
443                             i ? es1370_dac2_callback : es1370_dac1_callback,
444                             &as
445                             );
446                 }
447             }
448         }
449 
450         if (((ctl ^ s->ctl) & b->ctl_en)
451             || ((sctl ^ s->sctl) & b->sctl_pause)) {
452             int on = (ctl & b->ctl_en) && !(sctl & b->sctl_pause);
453 
454             if (i == ADC_CHANNEL) {
455                 AUD_set_active_in (s->adc_voice, on);
456             }
457             else {
458                 AUD_set_active_out (s->dac_voice[i], on);
459             }
460         }
461     }
462 
463     s->ctl = ctl;
464     s->sctl = sctl;
465 }
466 
es1370_fixup(ES1370State * s,uint32_t addr)467 static inline uint32_t es1370_fixup (ES1370State *s, uint32_t addr)
468 {
469     addr &= 0xff;
470     if (addr >= 0x30 && addr <= 0x3f)
471         addr |= s->mempage << 8;
472     return addr;
473 }
474 
IO_WRITE_PROTO(es1370_writeb)475 IO_WRITE_PROTO (es1370_writeb)
476 {
477     ES1370State *s = opaque;
478     uint32_t shift, mask;
479 
480     addr = es1370_fixup (s, addr);
481 
482     switch (addr) {
483     case ES1370_REG_CONTROL:
484     case ES1370_REG_CONTROL + 1:
485     case ES1370_REG_CONTROL + 2:
486     case ES1370_REG_CONTROL + 3:
487         shift = (addr - ES1370_REG_CONTROL) << 3;
488         mask = 0xff << shift;
489         val = (s->ctl & ~mask) | ((val & 0xff) << shift);
490         es1370_update_voices (s, val, s->sctl);
491         print_ctl (val);
492         break;
493     case ES1370_REG_MEMPAGE:
494         s->mempage = val;
495         break;
496     case ES1370_REG_SERIAL_CONTROL:
497     case ES1370_REG_SERIAL_CONTROL + 1:
498     case ES1370_REG_SERIAL_CONTROL + 2:
499     case ES1370_REG_SERIAL_CONTROL + 3:
500         shift = (addr - ES1370_REG_SERIAL_CONTROL) << 3;
501         mask = 0xff << shift;
502         val = (s->sctl & ~mask) | ((val & 0xff) << shift);
503         es1370_maybe_lower_irq (s, val);
504         es1370_update_voices (s, s->ctl, val);
505         print_sctl (val);
506         break;
507     default:
508         lwarn ("writeb %#x <- %#x\n", addr, val);
509         break;
510     }
511 }
512 
IO_WRITE_PROTO(es1370_writew)513 IO_WRITE_PROTO (es1370_writew)
514 {
515     ES1370State *s = opaque;
516     addr = es1370_fixup (s, addr);
517     uint32_t shift, mask;
518     struct chan *d = &s->chan[0];
519 
520     switch (addr) {
521     case ES1370_REG_CODEC:
522         dolog ("ignored codec write address %#x, data %#x\n",
523                (val >> 8) & 0xff, val & 0xff);
524         s->codec = val;
525         break;
526 
527     case ES1370_REG_CONTROL:
528     case ES1370_REG_CONTROL + 2:
529         shift = (addr != ES1370_REG_CONTROL) << 4;
530         mask = 0xffff << shift;
531         val = (s->ctl & ~mask) | ((val & 0xffff) << shift);
532         es1370_update_voices (s, val, s->sctl);
533         print_ctl (val);
534         break;
535 
536     case ES1370_REG_ADC_SCOUNT:
537         d++;
538     case ES1370_REG_DAC2_SCOUNT:
539         d++;
540     case ES1370_REG_DAC1_SCOUNT:
541         d->scount = (d->scount & ~0xffff) | (val & 0xffff);
542         break;
543 
544     default:
545         lwarn ("writew %#x <- %#x\n", addr, val);
546         break;
547     }
548 }
549 
IO_WRITE_PROTO(es1370_writel)550 IO_WRITE_PROTO (es1370_writel)
551 {
552     ES1370State *s = opaque;
553     struct chan *d = &s->chan[0];
554 
555     addr = es1370_fixup (s, addr);
556 
557     switch (addr) {
558     case ES1370_REG_CONTROL:
559         es1370_update_voices (s, val, s->sctl);
560         print_ctl (val);
561         break;
562 
563     case ES1370_REG_MEMPAGE:
564         s->mempage = val & 0xf;
565         break;
566 
567     case ES1370_REG_SERIAL_CONTROL:
568         es1370_maybe_lower_irq (s, val);
569         es1370_update_voices (s, s->ctl, val);
570         print_sctl (val);
571         break;
572 
573     case ES1370_REG_ADC_SCOUNT:
574         d++;
575     case ES1370_REG_DAC2_SCOUNT:
576         d++;
577     case ES1370_REG_DAC1_SCOUNT:
578         d->scount = (val & 0xffff) | (d->scount & ~0xffff);
579         ldebug ("chan %d CURR_SAMP_CT %d, SAMP_CT %d\n",
580                 d - &s->chan[0], val >> 16, (val & 0xffff));
581         break;
582 
583     case ES1370_REG_ADC_FRAMEADR:
584         d++;
585     case ES1370_REG_DAC2_FRAMEADR:
586         d++;
587     case ES1370_REG_DAC1_FRAMEADR:
588         d->frame_addr = val;
589         ldebug ("chan %d frame address %#x\n", d - &s->chan[0], val);
590         break;
591 
592     case ES1370_REG_PHANTOM_FRAMECNT:
593         lwarn ("writing to phantom frame count %#x\n", val);
594         break;
595     case ES1370_REG_PHANTOM_FRAMEADR:
596         lwarn ("writing to phantom frame address %#x\n", val);
597         break;
598 
599     case ES1370_REG_ADC_FRAMECNT:
600         d++;
601     case ES1370_REG_DAC2_FRAMECNT:
602         d++;
603     case ES1370_REG_DAC1_FRAMECNT:
604         d->frame_cnt = val;
605         d->leftover = 0;
606         ldebug ("chan %d frame count %d, buffer size %d\n",
607                 d - &s->chan[0], val >> 16, val & 0xffff);
608         break;
609 
610     default:
611         lwarn ("writel %#x <- %#x\n", addr, val);
612         break;
613     }
614 }
615 
IO_READ_PROTO(es1370_readb)616 IO_READ_PROTO (es1370_readb)
617 {
618     ES1370State *s = opaque;
619     uint32_t val;
620 
621     addr = es1370_fixup (s, addr);
622 
623     switch (addr) {
624     case 0x1b:                  /* Legacy */
625         lwarn ("Attempt to read from legacy register\n");
626         val = 5;
627         break;
628     case ES1370_REG_MEMPAGE:
629         val = s->mempage;
630         break;
631     case ES1370_REG_CONTROL + 0:
632     case ES1370_REG_CONTROL + 1:
633     case ES1370_REG_CONTROL + 2:
634     case ES1370_REG_CONTROL + 3:
635         val = s->ctl >> ((addr - ES1370_REG_CONTROL) << 3);
636         break;
637     case ES1370_REG_STATUS + 0:
638     case ES1370_REG_STATUS + 1:
639     case ES1370_REG_STATUS + 2:
640     case ES1370_REG_STATUS + 3:
641         val = s->status >> ((addr - ES1370_REG_STATUS) << 3);
642         break;
643     default:
644         val = ~0;
645         lwarn ("readb %#x -> %#x\n", addr, val);
646         break;
647     }
648     return val;
649 }
650 
IO_READ_PROTO(es1370_readw)651 IO_READ_PROTO (es1370_readw)
652 {
653     ES1370State *s = opaque;
654     struct chan *d = &s->chan[0];
655     uint32_t val;
656 
657     addr = es1370_fixup (s, addr);
658 
659     switch (addr) {
660     case ES1370_REG_ADC_SCOUNT + 2:
661         d++;
662     case ES1370_REG_DAC2_SCOUNT + 2:
663         d++;
664     case ES1370_REG_DAC1_SCOUNT + 2:
665         val = d->scount >> 16;
666         break;
667 
668     case ES1370_REG_ADC_FRAMECNT:
669         d++;
670     case ES1370_REG_DAC2_FRAMECNT:
671         d++;
672     case ES1370_REG_DAC1_FRAMECNT:
673         val = d->frame_cnt & 0xffff;
674         break;
675 
676     case ES1370_REG_ADC_FRAMECNT + 2:
677         d++;
678     case ES1370_REG_DAC2_FRAMECNT + 2:
679         d++;
680     case ES1370_REG_DAC1_FRAMECNT + 2:
681         val = d->frame_cnt >> 16;
682         break;
683 
684     default:
685         val = ~0;
686         lwarn ("readw %#x -> %#x\n", addr, val);
687         break;
688     }
689 
690     return val;
691 }
692 
IO_READ_PROTO(es1370_readl)693 IO_READ_PROTO (es1370_readl)
694 {
695     ES1370State *s = opaque;
696     uint32_t val;
697     struct chan *d = &s->chan[0];
698 
699     addr = es1370_fixup (s, addr);
700 
701     switch (addr) {
702     case ES1370_REG_CONTROL:
703         val = s->ctl;
704         break;
705     case ES1370_REG_STATUS:
706         val = s->status;
707         break;
708     case ES1370_REG_MEMPAGE:
709         val = s->mempage;
710         break;
711     case ES1370_REG_CODEC:
712         val = s->codec;
713         break;
714     case ES1370_REG_SERIAL_CONTROL:
715         val = s->sctl;
716         break;
717 
718     case ES1370_REG_ADC_SCOUNT:
719         d++;
720     case ES1370_REG_DAC2_SCOUNT:
721         d++;
722     case ES1370_REG_DAC1_SCOUNT:
723         val = d->scount;
724 #ifdef DEBUG_ES1370
725         {
726             uint32_t curr_count = d->scount >> 16;
727             uint32_t count = d->scount & 0xffff;
728 
729             curr_count <<= d->shift;
730             count <<= d->shift;
731             dolog ("read scount curr %d, total %d\n", curr_count, count);
732         }
733 #endif
734         break;
735 
736     case ES1370_REG_ADC_FRAMECNT:
737         d++;
738     case ES1370_REG_DAC2_FRAMECNT:
739         d++;
740     case ES1370_REG_DAC1_FRAMECNT:
741         val = d->frame_cnt;
742 #ifdef DEBUG_ES1370
743         {
744             uint32_t size = ((d->frame_cnt & 0xffff) + 1) << 2;
745             uint32_t curr = ((d->frame_cnt >> 16) + 1) << 2;
746             if (curr > size)
747                 dolog ("read framecnt curr %d, size %d %d\n", curr, size,
748                        curr > size);
749         }
750 #endif
751         break;
752 
753     case ES1370_REG_ADC_FRAMEADR:
754         d++;
755     case ES1370_REG_DAC2_FRAMEADR:
756         d++;
757     case ES1370_REG_DAC1_FRAMEADR:
758         val = d->frame_addr;
759         break;
760 
761     case ES1370_REG_PHANTOM_FRAMECNT:
762         val = ~0U;
763         lwarn ("reading from phantom frame count\n");
764         break;
765     case ES1370_REG_PHANTOM_FRAMEADR:
766         val = ~0U;
767         lwarn ("reading from phantom frame address\n");
768         break;
769 
770     default:
771         val = ~0U;
772         lwarn ("readl %#x -> %#x\n", addr, val);
773         break;
774     }
775     return val;
776 }
777 
778 
es1370_transfer_audio(ES1370State * s,struct chan * d,int loop_sel,int max,int * irq)779 static void es1370_transfer_audio (ES1370State *s, struct chan *d, int loop_sel,
780                                    int max, int *irq)
781 {
782     uint8_t tmpbuf[4096];
783     uint32_t addr = d->frame_addr;
784     int sc = d->scount & 0xffff;
785     int csc = d->scount >> 16;
786     int csc_bytes = (csc + 1) << d->shift;
787     int cnt = d->frame_cnt >> 16;
788     int size = d->frame_cnt & 0xffff;
789     int left = ((size - cnt + 1) << 2) + d->leftover;
790     int transfered = 0;
791     int temp = audio_MIN (max, audio_MIN (left, csc_bytes));
792     int index = d - &s->chan[0];
793 
794     addr += (cnt << 2) + d->leftover;
795 
796     if (index == ADC_CHANNEL) {
797         while (temp) {
798             int acquired, to_copy;
799 
800             to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
801             acquired = AUD_read (s->adc_voice, tmpbuf, to_copy);
802             if (!acquired)
803                 break;
804 
805             cpu_physical_memory_write (addr, tmpbuf, acquired);
806 
807             temp -= acquired;
808             addr += acquired;
809             transfered += acquired;
810         }
811     }
812     else {
813         SWVoiceOut *voice = s->dac_voice[index];
814 
815         while (temp) {
816             int copied, to_copy;
817 
818             to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
819             cpu_physical_memory_read (addr, tmpbuf, to_copy);
820             copied = AUD_write (voice, tmpbuf, to_copy);
821             if (!copied)
822                 break;
823             temp -= copied;
824             addr += copied;
825             transfered += copied;
826         }
827     }
828 
829     if (csc_bytes == transfered) {
830         *irq = 1;
831         d->scount = sc | (sc << 16);
832         ldebug ("sc = %d, rate = %f\n",
833                 (sc + 1) << d->shift,
834                 (sc + 1) / (double) 44100);
835     }
836     else {
837         *irq = 0;
838         d->scount = sc | (((csc_bytes - transfered - 1) >> d->shift) << 16);
839     }
840 
841     cnt += (transfered + d->leftover) >> 2;
842 
843     if (s->sctl & loop_sel) {
844         /* Bah, how stupid is that having a 0 represent true value?
845            i just spent few hours on this shit */
846         AUD_log ("es1370: warning", "non looping mode\n");
847     }
848     else {
849         d->frame_cnt = size;
850 
851         if ((uint32_t) cnt <= d->frame_cnt)
852             d->frame_cnt |= cnt << 16;
853     }
854 
855     d->leftover = (transfered + d->leftover) & 3;
856 }
857 
es1370_run_channel(ES1370State * s,size_t chan,int free_or_avail)858 static void es1370_run_channel (ES1370State *s, size_t chan, int free_or_avail)
859 {
860     uint32_t new_status = s->status;
861     int max_bytes, irq;
862     struct chan *d = &s->chan[chan];
863     const struct chan_bits *b = &es1370_chan_bits[chan];
864 
865     if (!(s->ctl & b->ctl_en) || (s->sctl & b->sctl_pause)) {
866         return;
867     }
868 
869     max_bytes = free_or_avail;
870     max_bytes &= ~((1 << d->shift) - 1);
871     if (!max_bytes) {
872         return;
873     }
874 
875     es1370_transfer_audio (s, d, b->sctl_loopsel, max_bytes, &irq);
876 
877     if (irq) {
878         if (s->sctl & b->sctl_inten) {
879             new_status |= b->stat_int;
880         }
881     }
882 
883     if (new_status != s->status) {
884         es1370_update_status (s, new_status);
885     }
886 }
887 
es1370_dac1_callback(void * opaque,int free)888 static void es1370_dac1_callback (void *opaque, int free)
889 {
890     ES1370State *s = opaque;
891 
892     es1370_run_channel (s, DAC1_CHANNEL, free);
893 }
894 
es1370_dac2_callback(void * opaque,int free)895 static void es1370_dac2_callback (void *opaque, int free)
896 {
897     ES1370State *s = opaque;
898 
899     es1370_run_channel (s, DAC2_CHANNEL, free);
900 }
901 
es1370_adc_callback(void * opaque,int avail)902 static void es1370_adc_callback (void *opaque, int avail)
903 {
904     ES1370State *s = opaque;
905 
906     es1370_run_channel (s, ADC_CHANNEL, avail);
907 }
908 
es1370_map(PCIDevice * pci_dev,int region_num,pcibus_t addr,pcibus_t size,int type)909 static void es1370_map (PCIDevice *pci_dev, int region_num,
910                         pcibus_t addr, pcibus_t size, int type)
911 {
912     ES1370State *s = DO_UPCAST (ES1370State, dev, pci_dev);
913 
914     (void) region_num;
915     (void) size;
916     (void) type;
917 
918     register_ioport_write (addr, 0x40 * 4, 1, es1370_writeb, s);
919     register_ioport_write (addr, 0x40 * 2, 2, es1370_writew, s);
920     register_ioport_write (addr, 0x40, 4, es1370_writel, s);
921 
922     register_ioport_read (addr, 0x40 * 4, 1, es1370_readb, s);
923     register_ioport_read (addr, 0x40 * 2, 2, es1370_readw, s);
924     register_ioport_read (addr, 0x40, 4, es1370_readl, s);
925 }
926 
927 static const VMStateDescription vmstate_es1370_channel = {
928     .name = "es1370_channel",
929     .version_id = 2,
930     .minimum_version_id = 2,
931     .minimum_version_id_old = 2,
932     .fields      = (VMStateField []) {
933         VMSTATE_UINT32(shift, struct chan),
934         VMSTATE_UINT32(leftover, struct chan),
935         VMSTATE_UINT32(scount, struct chan),
936         VMSTATE_UINT32(frame_addr, struct chan),
937         VMSTATE_UINT32(frame_cnt, struct chan),
938         VMSTATE_END_OF_LIST()
939     }
940 };
941 
es1370_post_load(void * opaque,int version_id)942 static int es1370_post_load (void *opaque, int version_id)
943 {
944     uint32_t ctl, sctl;
945     ES1370State *s = opaque;
946     size_t i;
947 
948     for (i = 0; i < NB_CHANNELS; ++i) {
949         if (i == ADC_CHANNEL) {
950             if (s->adc_voice) {
951                 AUD_close_in (&s->card, s->adc_voice);
952                 s->adc_voice = NULL;
953             }
954         }
955         else {
956             if (s->dac_voice[i]) {
957                 AUD_close_out (&s->card, s->dac_voice[i]);
958                 s->dac_voice[i] = NULL;
959             }
960         }
961     }
962 
963     ctl = s->ctl;
964     sctl = s->sctl;
965     s->ctl = 0;
966     s->sctl = 0;
967     es1370_update_voices (s, ctl, sctl);
968     return 0;
969 }
970 
971 static const VMStateDescription vmstate_es1370 = {
972     .name = "es1370",
973     .version_id = 2,
974     .minimum_version_id = 2,
975     .minimum_version_id_old = 2,
976     .post_load = es1370_post_load,
977     .fields      = (VMStateField []) {
978         VMSTATE_PCI_DEVICE(dev, ES1370State),
979         VMSTATE_STRUCT_ARRAY(chan, ES1370State, NB_CHANNELS, 2,
980                              vmstate_es1370_channel, struct chan),
981         VMSTATE_UINT32(ctl, ES1370State),
982         VMSTATE_UINT32(status, ES1370State),
983         VMSTATE_UINT32(mempage, ES1370State),
984         VMSTATE_UINT32(codec, ES1370State),
985         VMSTATE_UINT32(sctl, ES1370State),
986         VMSTATE_END_OF_LIST()
987     }
988 };
989 
es1370_on_reset(void * opaque)990 static void es1370_on_reset (void *opaque)
991 {
992     ES1370State *s = opaque;
993     es1370_reset (s);
994 }
995 
es1370_initfn(PCIDevice * dev)996 static int es1370_initfn (PCIDevice *dev)
997 {
998     ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
999     uint8_t *c = s->dev.config;
1000 
1001     pci_config_set_vendor_id (c, PCI_VENDOR_ID_ENSONIQ);
1002     pci_config_set_device_id (c, PCI_DEVICE_ID_ENSONIQ_ES1370);
1003     c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_SLOW >> 8;
1004     pci_config_set_class (c, PCI_CLASS_MULTIMEDIA_AUDIO);
1005 
1006 #if 1
1007     c[PCI_SUBSYSTEM_VENDOR_ID] = 0x42;
1008     c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x49;
1009     c[PCI_SUBSYSTEM_ID] = 0x4c;
1010     c[PCI_SUBSYSTEM_ID + 1] = 0x4c;
1011 #else
1012     c[PCI_SUBSYSTEM_VENDOR_ID] = 0x74;
1013     c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x12;
1014     c[PCI_SUBSYSTEM_ID] = 0x71;
1015     c[PCI_SUBSYSTEM_ID + 1] = 0x13;
1016     c[PCI_CAPABILITY_LIST] = 0xdc;
1017     c[PCI_INTERRUPT_LINE] = 10;
1018     c[0xdc] = 0x00;
1019 #endif
1020 
1021     /* TODO: RST# value should be 0. */
1022     c[PCI_INTERRUPT_PIN] = 1;
1023     c[PCI_MIN_GNT] = 0x0c;
1024     c[PCI_MAX_LAT] = 0x80;
1025 
1026     pci_register_bar (&s->dev, 0, 256, PCI_BASE_ADDRESS_SPACE_IO, es1370_map);
1027     qemu_register_reset (es1370_on_reset, s);
1028 
1029     AUD_register_card ("es1370", &s->card);
1030     es1370_reset (s);
1031     return 0;
1032 }
1033 
es1370_init(PCIBus * bus)1034 int es1370_init (PCIBus *bus)
1035 {
1036     pci_create_simple (bus, -1, "ES1370");
1037     return 0;
1038 }
1039 
1040 static PCIDeviceInfo es1370_info = {
1041     .qdev.name    = "ES1370",
1042     .qdev.desc    = "ENSONIQ AudioPCI ES1370",
1043     .qdev.size    = sizeof (ES1370State),
1044     .qdev.vmsd    = &vmstate_es1370,
1045     .init         = es1370_initfn,
1046 };
1047 
es1370_register(void)1048 static void es1370_register (void)
1049 {
1050     pci_qdev_register (&es1370_info);
1051 }
1052 device_init (es1370_register);
1053 
1054