xref: /illumos-kvm-cmd/hw/acpi_piix4.c (revision 68396ea9)
1 /*
2  * ACPI implementation
3  *
4  * Copyright (c) 2006 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License version 2 as published by the Free Software Foundation.
9  *
10  * This library is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * Lesser General Public License for more details.
14  *
15  * You should have received a copy of the GNU Lesser General Public
16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
17  */
18 #include "hw.h"
19 #include "pc.h"
20 #include "apm.h"
21 #include "pm_smbus.h"
22 #include "pci.h"
23 #include "acpi.h"
24 #include "sysemu.h"
25 #include "range.h"
26 
27 //#define DEBUG
28 
29 #ifdef DEBUG
30 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
31 #else
32 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
33 #endif
34 
35 #define ACPI_DBG_IO_ADDR  0xb044
36 
37 #define GPE_BASE 0xafe0
38 #define PROC_BASE 0xaf00
39 #define PCI_BASE 0xae00
40 #define PCI_EJ_BASE 0xae08
41 #define PCI_RMV_BASE 0xae0c
42 
43 #define PIIX4_CPU_HOTPLUG_STATUS 4
44 #define PIIX4_PCI_HOTPLUG_STATUS 2
45 
46 struct gpe_regs {
47     uint16_t sts; /* status */
48     uint16_t en;  /* enabled */
49     uint8_t cpus_sts[32];
50 };
51 
52 struct pci_status {
53     uint32_t up;
54     uint32_t down;
55 };
56 
57 typedef struct PIIX4PMState {
58     PCIDevice dev;
59     IORange ioport;
60     uint16_t pmsts;
61     uint16_t pmen;
62     uint16_t pmcntrl;
63 
64     APMState apm;
65 
66     QEMUTimer *tmr_timer;
67     int64_t tmr_overflow_time;
68 
69     PMSMBus smb;
70     uint32_t smb_io_base;
71 
72     qemu_irq irq;
73     qemu_irq cmos_s3;
74     qemu_irq smi_irq;
75     int kvm_enabled;
76 
77     /* for pci hotplug */
78     struct gpe_regs gpe;
79     struct pci_status pci0_status;
80     uint32_t pci0_hotplug_enable;
81 } PIIX4PMState;
82 
83 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
84 
85 #define ACPI_ENABLE 0xf1
86 #define ACPI_DISABLE 0xf0
87 
get_pmtmr(PIIX4PMState * s)88 static uint32_t get_pmtmr(PIIX4PMState *s)
89 {
90     uint32_t d;
91     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
92     return d & 0xffffff;
93 }
94 
get_pmsts(PIIX4PMState * s)95 static int get_pmsts(PIIX4PMState *s)
96 {
97     int64_t d;
98 
99     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
100                  get_ticks_per_sec());
101     if (d >= s->tmr_overflow_time)
102         s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
103     return s->pmsts;
104 }
105 
pm_update_sci(PIIX4PMState * s)106 static void pm_update_sci(PIIX4PMState *s)
107 {
108     int sci_level, pmsts;
109     int64_t expire_time;
110 
111     pmsts = get_pmsts(s);
112     sci_level = (((pmsts & s->pmen) &
113                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
114                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
115                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
116                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
117         (((s->gpe.sts & s->gpe.en) &
118           (PIIX4_CPU_HOTPLUG_STATUS | PIIX4_PCI_HOTPLUG_STATUS)) != 0);
119 
120     qemu_set_irq(s->irq, sci_level);
121     /* schedule a timer interruption if needed */
122     if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
123         !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
124         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
125                                PM_TIMER_FREQUENCY);
126         qemu_mod_timer(s->tmr_timer, expire_time);
127     } else {
128         qemu_del_timer(s->tmr_timer);
129     }
130 }
131 
pm_tmr_timer(void * opaque)132 static void pm_tmr_timer(void *opaque)
133 {
134     PIIX4PMState *s = opaque;
135     pm_update_sci(s);
136 }
137 
pm_ioport_write(IORange * ioport,uint64_t addr,unsigned width,uint64_t val)138 static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
139                             uint64_t val)
140 {
141     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
142 
143     if (width != 2) {
144         PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
145                       (unsigned)addr, width, (unsigned)val);
146     }
147 
148     switch(addr) {
149     case 0x00:
150         {
151             int64_t d;
152             int pmsts;
153             pmsts = get_pmsts(s);
154             if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
155                 /* if TMRSTS is reset, then compute the new overflow time */
156                 d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
157                              get_ticks_per_sec());
158                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
159             }
160             s->pmsts &= ~val;
161             pm_update_sci(s);
162         }
163         break;
164     case 0x02:
165         s->pmen = val;
166         pm_update_sci(s);
167         break;
168     case 0x04:
169         {
170             int sus_typ;
171             s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
172             if (val & ACPI_BITMASK_SLEEP_ENABLE) {
173                 /* change suspend type */
174                 sus_typ = (val >> 10) & 7;
175                 switch(sus_typ) {
176                 case 0: /* soft power off */
177                     qemu_system_shutdown_request();
178                     break;
179                 case 1:
180                     /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
181                        Pretend that resume was caused by power button */
182                     s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
183                                  ACPI_BITMASK_POWER_BUTTON_STATUS);
184                     qemu_system_reset_request();
185                     if (s->cmos_s3) {
186                         qemu_irq_raise(s->cmos_s3);
187                     }
188                 default:
189                     break;
190                 }
191             }
192         }
193         break;
194     default:
195         break;
196     }
197     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
198 }
199 
pm_ioport_read(IORange * ioport,uint64_t addr,unsigned width,uint64_t * data)200 static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
201                             uint64_t *data)
202 {
203     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
204     uint32_t val;
205 
206     switch(addr) {
207     case 0x00:
208         val = get_pmsts(s);
209         break;
210     case 0x02:
211         val = s->pmen;
212         break;
213     case 0x04:
214         val = s->pmcntrl;
215         break;
216     case 0x08:
217         val = get_pmtmr(s);
218         break;
219     default:
220         val = 0;
221         break;
222     }
223     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
224     *data = val;
225 }
226 
227 static const IORangeOps pm_iorange_ops = {
228     .read = pm_ioport_read,
229     .write = pm_ioport_write,
230 };
231 
apm_ctrl_changed(uint32_t val,void * arg)232 static void apm_ctrl_changed(uint32_t val, void *arg)
233 {
234     PIIX4PMState *s = arg;
235 
236     /* ACPI specs 3.0, 4.7.2.5 */
237     if (val == ACPI_ENABLE) {
238         s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
239     } else if (val == ACPI_DISABLE) {
240         s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
241     }
242 
243     if (s->dev.config[0x5b] & (1 << 1)) {
244         if (s->smi_irq) {
245             qemu_irq_raise(s->smi_irq);
246         }
247     }
248 }
249 
acpi_dbg_writel(void * opaque,uint32_t addr,uint32_t val)250 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
251 {
252     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
253 }
254 
pm_io_space_update(PIIX4PMState * s)255 static void pm_io_space_update(PIIX4PMState *s)
256 {
257     uint32_t pm_io_base;
258 
259     if (s->dev.config[0x80] & 1) {
260         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
261         pm_io_base &= 0xffc0;
262 
263         /* XXX: need to improve memory and ioport allocation */
264         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
265         iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
266         ioport_register(&s->ioport);
267     }
268 }
269 
pm_write_config(PCIDevice * d,uint32_t address,uint32_t val,int len)270 static void pm_write_config(PCIDevice *d,
271                             uint32_t address, uint32_t val, int len)
272 {
273     pci_default_write_config(d, address, val, len);
274     if (range_covers_byte(address, len, 0x80))
275         pm_io_space_update((PIIX4PMState *)d);
276 }
277 
vmstate_acpi_post_load(void * opaque,int version_id)278 static int vmstate_acpi_post_load(void *opaque, int version_id)
279 {
280     PIIX4PMState *s = opaque;
281 
282     pm_io_space_update(s);
283     return 0;
284 }
285 
286 static const VMStateDescription vmstate_gpe = {
287     .name = "gpe",
288     .version_id = 1,
289     .minimum_version_id = 1,
290     .minimum_version_id_old = 1,
291     .fields      = (VMStateField []) {
292         VMSTATE_UINT16(sts, struct gpe_regs),
293         VMSTATE_UINT16(en, struct gpe_regs),
294         VMSTATE_END_OF_LIST()
295     }
296 };
297 
298 static const VMStateDescription vmstate_pci_status = {
299     .name = "pci_status",
300     .version_id = 1,
301     .minimum_version_id = 1,
302     .minimum_version_id_old = 1,
303     .fields      = (VMStateField []) {
304         VMSTATE_UINT32(up, struct pci_status),
305         VMSTATE_UINT32(down, struct pci_status),
306         VMSTATE_END_OF_LIST()
307     }
308 };
309 
310 static const VMStateDescription vmstate_acpi = {
311     .name = "piix4_pm",
312     .version_id = 2,
313     .minimum_version_id = 1,
314     .minimum_version_id_old = 1,
315     .post_load = vmstate_acpi_post_load,
316     .fields      = (VMStateField []) {
317         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
318         VMSTATE_UINT16(pmsts, PIIX4PMState),
319         VMSTATE_UINT16(pmen, PIIX4PMState),
320         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
321         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
322         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
323         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
324         VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
325         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
326                        struct pci_status),
327         VMSTATE_END_OF_LIST()
328     }
329 };
330 
piix4_update_hotplug(PIIX4PMState * s)331 static void piix4_update_hotplug(PIIX4PMState *s)
332 {
333     PCIDevice *dev = &s->dev;
334     BusState *bus = qdev_get_parent_bus(&dev->qdev);
335     DeviceState *qdev, *next;
336 
337     s->pci0_hotplug_enable = ~0;
338 
339     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
340         PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
341         PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
342         int slot = PCI_SLOT(pdev->devfn);
343 
344         if (info->no_hotplug) {
345             s->pci0_hotplug_enable &= ~(1 << slot);
346         }
347     }
348 }
349 
piix4_reset(void * opaque)350 static void piix4_reset(void *opaque)
351 {
352     PIIX4PMState *s = opaque;
353     uint8_t *pci_conf = s->dev.config;
354 
355     pci_conf[0x58] = 0;
356     pci_conf[0x59] = 0;
357     pci_conf[0x5a] = 0;
358     pci_conf[0x5b] = 0;
359 
360     if (s->kvm_enabled) {
361         /* Mark SMM as already inited (until KVM supports SMM). */
362         pci_conf[0x5B] = 0x02;
363     }
364     piix4_update_hotplug(s);
365 }
366 
piix4_powerdown(void * opaque,int irq,int power_failing)367 static void piix4_powerdown(void *opaque, int irq, int power_failing)
368 {
369     PIIX4PMState *s = opaque;
370 
371     if (!s) {
372         qemu_system_shutdown_request();
373     } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
374         s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
375         pm_update_sci(s);
376     }
377 }
378 
379 static PIIX4PMState *global_piix4_pm_state; /* cpu hotadd */
380 
piix4_pm_initfn(PCIDevice * dev)381 static int piix4_pm_initfn(PCIDevice *dev)
382 {
383     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
384     uint8_t *pci_conf;
385 
386     /* for cpu hotadd */
387     global_piix4_pm_state = s;
388 
389     pci_conf = s->dev.config;
390     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
391     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
392     pci_conf[0x06] = 0x80;
393     pci_conf[0x07] = 0x02;
394     pci_conf[0x08] = 0x03; // revision number
395     pci_conf[0x09] = 0x00;
396     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
397     pci_conf[0x3d] = 0x01; // interrupt pin 1
398 
399     pci_conf[0x40] = 0x01; /* PM io base read only bit */
400 
401 #if defined(TARGET_IA64)
402     pci_conf[0x40] = 0x41; /* PM io base read only bit */
403     pci_conf[0x41] = 0x1f;
404     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
405     s->pmcntrl = SCI_EN;
406 #endif
407 
408     /* APM */
409     apm_init(&s->apm, apm_ctrl_changed, s);
410 
411     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
412 
413     if (s->kvm_enabled) {
414         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
415          * support SMM mode. */
416         pci_conf[0x5B] = 0x02;
417     }
418 
419     /* XXX: which specification is used ? The i82731AB has different
420        mappings */
421     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
422     pci_conf[0x63] = 0x60;
423     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
424 	(serial_hds[1] != NULL ? 0x90 : 0);
425 
426     pci_conf[0x90] = s->smb_io_base | 1;
427     pci_conf[0x91] = s->smb_io_base >> 8;
428     pci_conf[0xd2] = 0x09;
429     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
430     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
431 
432     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
433 
434     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
435 
436     pm_smbus_init(&s->dev.qdev, &s->smb);
437     qemu_register_reset(piix4_reset, s);
438     piix4_acpi_system_hot_add_init(dev->bus, s);
439 
440     return 0;
441 }
442 
piix4_pm_init(PCIBus * bus,int devfn,uint32_t smb_io_base,qemu_irq sci_irq,qemu_irq cmos_s3,qemu_irq smi_irq,int kvm_enabled)443 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
444                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
445                        int kvm_enabled)
446 {
447     PCIDevice *dev;
448     PIIX4PMState *s;
449 
450     dev = pci_create(bus, devfn, "PIIX4_PM");
451     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
452 
453     s = DO_UPCAST(PIIX4PMState, dev, dev);
454     s->irq = sci_irq;
455     s->cmos_s3 = cmos_s3;
456     s->smi_irq = smi_irq;
457     s->kvm_enabled = kvm_enabled;
458 
459     qdev_init_nofail(&dev->qdev);
460 
461     return s->smb.smbus;
462 }
463 
464 static PCIDeviceInfo piix4_pm_info = {
465     .qdev.name          = "PIIX4_PM",
466     .qdev.desc          = "PM",
467     .qdev.size          = sizeof(PIIX4PMState),
468     .qdev.vmsd          = &vmstate_acpi,
469     .qdev.no_user       = 1,
470     .no_hotplug         = 1,
471     .init               = piix4_pm_initfn,
472     .config_write       = pm_write_config,
473     .qdev.props         = (Property[]) {
474         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
475         DEFINE_PROP_END_OF_LIST(),
476     }
477 };
478 
piix4_pm_register(void)479 static void piix4_pm_register(void)
480 {
481     pci_qdev_register(&piix4_pm_info);
482 }
483 
484 device_init(piix4_pm_register);
485 
gpe_read_val(uint16_t val,uint32_t addr)486 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
487 {
488     if (addr & 1)
489         return (val >> 8) & 0xff;
490     return val & 0xff;
491 }
492 
gpe_readb(void * opaque,uint32_t addr)493 static uint32_t gpe_readb(void *opaque, uint32_t addr)
494 {
495     uint32_t val = 0;
496     PIIX4PMState *s = opaque;
497     struct gpe_regs *g = &s->gpe;
498 
499     switch (addr) {
500         case PROC_BASE ... PROC_BASE+31:
501             val = g->cpus_sts[addr - PROC_BASE];
502             break;
503 
504         case GPE_BASE:
505         case GPE_BASE + 1:
506             val = gpe_read_val(g->sts, addr);
507             break;
508         case GPE_BASE + 2:
509         case GPE_BASE + 3:
510             val = gpe_read_val(g->en, addr);
511             break;
512         default:
513             break;
514     }
515 
516     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
517     return val;
518 }
519 
gpe_write_val(uint16_t * cur,int addr,uint32_t val)520 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
521 {
522     if (addr & 1)
523         *cur = (*cur & 0xff) | (val << 8);
524     else
525         *cur = (*cur & 0xff00) | (val & 0xff);
526 }
527 
gpe_reset_val(uint16_t * cur,int addr,uint32_t val)528 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
529 {
530     uint16_t x1, x0 = val & 0xff;
531     int shift = (addr & 1) ? 8 : 0;
532 
533     x1 = (*cur >> shift) & 0xff;
534 
535     x1 = x1 & ~x0;
536 
537     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
538 }
539 
gpe_writeb(void * opaque,uint32_t addr,uint32_t val)540 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
541 {
542     PIIX4PMState *s = opaque;
543     struct gpe_regs *g = &s->gpe;
544 
545     switch (addr) {
546         case GPE_BASE:
547         case GPE_BASE + 1:
548             gpe_reset_val(&g->sts, addr, val);
549             break;
550         case GPE_BASE + 2:
551         case GPE_BASE + 3:
552             gpe_write_val(&g->en, addr, val);
553             break;
554         default:
555             break;
556     }
557 
558     pm_update_sci(s);
559 
560     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
561 }
562 
pcihotplug_read(void * opaque,uint32_t addr)563 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
564 {
565     uint32_t val = 0;
566     struct pci_status *g = opaque;
567     switch (addr) {
568         case PCI_BASE:
569             val = g->up;
570             break;
571         case PCI_BASE + 4:
572             val = g->down;
573             break;
574         default:
575             break;
576     }
577 
578     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
579     return val;
580 }
581 
pcihotplug_write(void * opaque,uint32_t addr,uint32_t val)582 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
583 {
584     struct pci_status *g = opaque;
585     switch (addr) {
586         case PCI_BASE:
587             g->up = val;
588             break;
589         case PCI_BASE + 4:
590             g->down = val;
591             break;
592    }
593 
594     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
595 }
596 
pciej_read(void * opaque,uint32_t addr)597 static uint32_t pciej_read(void *opaque, uint32_t addr)
598 {
599     PIIX4_DPRINTF("pciej read %x\n", addr);
600     return 0;
601 }
602 
pciej_write(void * opaque,uint32_t addr,uint32_t val)603 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
604 {
605     BusState *bus = opaque;
606     DeviceState *qdev, *next;
607     PCIDevice *dev;
608     int slot = ffs(val) - 1;
609 
610     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
611         dev = DO_UPCAST(PCIDevice, qdev, qdev);
612         if (PCI_SLOT(dev->devfn) == slot) {
613             qdev_free(qdev);
614         }
615     }
616 
617 
618     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
619 }
620 
pcirmv_read(void * opaque,uint32_t addr)621 static uint32_t pcirmv_read(void *opaque, uint32_t addr)
622 {
623     PIIX4PMState *s = opaque;
624 
625     return s->pci0_hotplug_enable;
626 }
627 
pcirmv_write(void * opaque,uint32_t addr,uint32_t val)628 static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
629 {
630     return;
631 }
632 
633 extern const char *global_cpu_model;
634 
635 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
636                                 PCIHotplugState state);
637 
piix4_acpi_system_hot_add_init(PCIBus * bus,PIIX4PMState * s)638 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
639 {
640     struct pci_status *pci0_status = &s->pci0_status;
641     int i = 0, cpus = smp_cpus;
642 
643     while (cpus > 0) {
644         s->gpe.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
645         cpus -= 8;
646     }
647 
648     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
649     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, s);
650 
651     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s);
652     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, s);
653 
654     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
655     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
656 
657     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
658     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
659 
660     register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
661     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
662 
663     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
664 }
665 
666 #if defined(TARGET_I386)
enable_processor(struct gpe_regs * g,int cpu)667 static void enable_processor(struct gpe_regs *g, int cpu)
668 {
669     g->sts |= PIIX4_CPU_HOTPLUG_STATUS;
670     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
671 }
672 
disable_processor(struct gpe_regs * g,int cpu)673 static void disable_processor(struct gpe_regs *g, int cpu)
674 {
675     g->sts |= PIIX4_CPU_HOTPLUG_STATUS;
676     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
677 }
678 
qemu_system_cpu_hot_add(int cpu,int state)679 void qemu_system_cpu_hot_add(int cpu, int state)
680 {
681     CPUState *env;
682     PIIX4PMState *s = global_piix4_pm_state;
683 
684     if (state && !qemu_get_cpu(cpu)) {
685         env = pc_new_cpu(global_cpu_model);
686         if (!env) {
687             fprintf(stderr, "cpu %d creation failed\n", cpu);
688             return;
689         }
690         env->cpuid_apic_id = cpu;
691     }
692 
693     if (state)
694         enable_processor(&s->gpe, cpu);
695     else
696         disable_processor(&s->gpe, cpu);
697 
698     pm_update_sci(s);
699 }
700 #endif
701 
enable_device(PIIX4PMState * s,int slot)702 static void enable_device(PIIX4PMState *s, int slot)
703 {
704     s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
705     s->pci0_status.up |= (1 << slot);
706 }
707 
disable_device(PIIX4PMState * s,int slot)708 static void disable_device(PIIX4PMState *s, int slot)
709 {
710     s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
711     s->pci0_status.down |= (1 << slot);
712 }
713 
piix4_device_hotplug(DeviceState * qdev,PCIDevice * dev,PCIHotplugState state)714 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
715 				PCIHotplugState state)
716 {
717     int slot = PCI_SLOT(dev->devfn);
718     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
719                                 DO_UPCAST(PCIDevice, qdev, qdev));
720 
721     /* Don't send event when device is enabled during qemu machine creation:
722      * it is present on boot, no hotplug event is necessary. We do send an
723      * event when the device is disabled later. */
724     if (state == PCI_COLDPLUG_ENABLED) {
725         return 0;
726     }
727 
728     s->pci0_status.up = 0;
729     s->pci0_status.down = 0;
730     if (state == PCI_HOTPLUG_ENABLED) {
731         enable_device(s, slot);
732     } else {
733         disable_device(s, slot);
734     }
735 
736     pm_update_sci(s);
737 
738     return 0;
739 }
740