xref: /illumos-kvm-cmd/cris-dis.c (revision 68396ea9)
1 /* Disassembler code for CRIS.
2    Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
3    Contributed by Axis Communications AB, Lund, Sweden.
4    Written by Hans-Peter Nilsson.
5 
6    This file is part of the GNU binutils and GDB, the GNU debugger.
7 
8    This program is free software; you can redistribute it and/or modify it
9    under the terms of the GNU General Public License as published by the
10    Free Software Foundation; either version 2, or (at your option) any later
11    version.
12 
13    This program is distributed in the hope that it will be useful, but WITHOUT
14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16    more details.
17 
18    You should have received a copy of the GNU General Public License
19    along with this program; if not, see <http://www.gnu.org/licenses/>. */
20 
21 #include "qemu-common.h"
22 #include "dis-asm.h"
23 //#include "sysdep.h"
24 #include "target-cris/opcode-cris.h"
25 //#include "libiberty.h"
26 
27 #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
28 
29 /* cris-opc.c -- Table of opcodes for the CRIS processor.
30    Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
31    Contributed by Axis Communications AB, Lund, Sweden.
32    Originally written for GAS 1.38.1 by Mikael Asker.
33    Reorganized by Hans-Peter Nilsson.
34 
35 This file is part of GAS, GDB and the GNU binutils.
36 
37 GAS, GDB, and GNU binutils is free software; you can redistribute it
38 and/or modify it under the terms of the GNU General Public License as
39 published by the Free Software Foundation; either version 2, or (at your
40 option) any later version.
41 
42 GAS, GDB, and GNU binutils are distributed in the hope that they will be
43 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
44 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
45 GNU General Public License for more details.
46 
47 You should have received a copy of the GNU General Public License
48 along with this program; if not, see <http://www.gnu.org/licenses/>.  */
49 
50 #ifndef NULL
51 #define NULL (0)
52 #endif
53 
54 /* This table isn't used for CRISv32 and the size of immediate operands.  */
55 const struct cris_spec_reg
56 cris_spec_regs[] =
57 {
58   {"bz",  0,  1, cris_ver_v32p,	   NULL},
59   {"p0",  0,  1, 0,		   NULL},
60   {"vr",  1,  1, 0,		   NULL},
61   {"p1",  1,  1, 0,		   NULL},
62   {"pid", 2,  1, cris_ver_v32p,    NULL},
63   {"p2",  2,  1, cris_ver_v32p,	   NULL},
64   {"p2",  2,  1, cris_ver_warning, NULL},
65   {"srs", 3,  1, cris_ver_v32p,    NULL},
66   {"p3",  3,  1, cris_ver_v32p,	   NULL},
67   {"p3",  3,  1, cris_ver_warning, NULL},
68   {"wz",  4,  2, cris_ver_v32p,	   NULL},
69   {"p4",  4,  2, 0,		   NULL},
70   {"ccr", 5,  2, cris_ver_v0_10,   NULL},
71   {"exs", 5,  4, cris_ver_v32p,	   NULL},
72   {"p5",  5,  2, cris_ver_v0_10,   NULL},
73   {"p5",  5,  4, cris_ver_v32p,	   NULL},
74   {"dcr0",6,  2, cris_ver_v0_3,	   NULL},
75   {"eda", 6,  4, cris_ver_v32p,	   NULL},
76   {"p6",  6,  2, cris_ver_v0_3,	   NULL},
77   {"p6",  6,  4, cris_ver_v32p,	   NULL},
78   {"dcr1/mof", 7, 4, cris_ver_v10p,
79    "Register `dcr1/mof' with ambiguous size specified.  Guessing 4 bytes"},
80   {"dcr1/mof", 7, 2, cris_ver_v0_3,
81    "Register `dcr1/mof' with ambiguous size specified.  Guessing 2 bytes"},
82   {"mof", 7,  4, cris_ver_v10p,	   NULL},
83   {"dcr1",7,  2, cris_ver_v0_3,	   NULL},
84   {"p7",  7,  4, cris_ver_v10p,	   NULL},
85   {"p7",  7,  2, cris_ver_v0_3,	   NULL},
86   {"dz",  8,  4, cris_ver_v32p,	   NULL},
87   {"p8",  8,  4, 0,		   NULL},
88   {"ibr", 9,  4, cris_ver_v0_10,   NULL},
89   {"ebp", 9,  4, cris_ver_v32p,	   NULL},
90   {"p9",  9,  4, 0,		   NULL},
91   {"irp", 10, 4, cris_ver_v0_10,   NULL},
92   {"erp", 10, 4, cris_ver_v32p,	   NULL},
93   {"p10", 10, 4, 0,		   NULL},
94   {"srp", 11, 4, 0,		   NULL},
95   {"p11", 11, 4, 0,		   NULL},
96   /* For disassembly use only.  Accept at assembly with a warning.  */
97   {"bar/dtp0", 12, 4, cris_ver_warning,
98    "Ambiguous register `bar/dtp0' specified"},
99   {"nrp", 12, 4, cris_ver_v32p,	   NULL},
100   {"bar", 12, 4, cris_ver_v8_10,   NULL},
101   {"dtp0",12, 4, cris_ver_v0_3,	   NULL},
102   {"p12", 12, 4, 0,		   NULL},
103   /* For disassembly use only.  Accept at assembly with a warning.  */
104   {"dccr/dtp1",13, 4, cris_ver_warning,
105    "Ambiguous register `dccr/dtp1' specified"},
106   {"ccs", 13, 4, cris_ver_v32p,	   NULL},
107   {"dccr",13, 4, cris_ver_v8_10,   NULL},
108   {"dtp1",13, 4, cris_ver_v0_3,	   NULL},
109   {"p13", 13, 4, 0,		   NULL},
110   {"brp", 14, 4, cris_ver_v3_10,   NULL},
111   {"usp", 14, 4, cris_ver_v32p,	   NULL},
112   {"p14", 14, 4, cris_ver_v3p,	   NULL},
113   {"usp", 15, 4, cris_ver_v10,	   NULL},
114   {"spc", 15, 4, cris_ver_v32p,	   NULL},
115   {"p15", 15, 4, cris_ver_v10p,	   NULL},
116   {NULL, 0, 0, cris_ver_version_all, NULL}
117 };
118 
119 /* Add version specifiers to this table when necessary.
120    The (now) regular coding of register names suggests a simpler
121    implementation.  */
122 const struct cris_support_reg cris_support_regs[] =
123 {
124   {"s0", 0},
125   {"s1", 1},
126   {"s2", 2},
127   {"s3", 3},
128   {"s4", 4},
129   {"s5", 5},
130   {"s6", 6},
131   {"s7", 7},
132   {"s8", 8},
133   {"s9", 9},
134   {"s10", 10},
135   {"s11", 11},
136   {"s12", 12},
137   {"s13", 13},
138   {"s14", 14},
139   {"s15", 15},
140   {NULL, 0}
141 };
142 
143 /* All CRIS opcodes are 16 bits.
144 
145    - The match component is a mask saying which bits must match a
146      particular opcode in order for an instruction to be an instance
147      of that opcode.
148 
149    - The args component is a string containing characters symbolically
150      matching the operands of an instruction.  Used for both assembly
151      and disassembly.
152 
153      Operand-matching characters:
154      [ ] , space
155         Verbatim.
156      A	The string "ACR" (case-insensitive).
157      B	Not really an operand.  It causes a "BDAP -size,SP" prefix to be
158 	output for the PUSH alias-instructions and recognizes a push-
159 	prefix at disassembly.  This letter isn't recognized for v32.
160 	Must be followed by a R or P letter.
161      !	Non-match pattern, will not match if there's a prefix insn.
162      b	Non-matching operand, used for branches with 16-bit
163 	displacement. Only recognized by the disassembler.
164      c	5-bit unsigned immediate in bits <4:0>.
165      C	4-bit unsigned immediate in bits <3:0>.
166      d  At assembly, optionally (as in put other cases before this one)
167 	".d" or ".D" at the start of the operands, followed by one space
168 	character.  At disassembly, nothing.
169      D	General register in bits <15:12> and <3:0>.
170      f	List of flags in bits <15:12> and <3:0>.
171      i	6-bit signed immediate in bits <5:0>.
172      I	6-bit unsigned immediate in bits <5:0>.
173      M	Size modifier (B, W or D) for CLEAR instructions.
174      m	Size modifier (B, W or D) in bits <5:4>
175      N  A 32-bit dword, like in the difference between s and y.
176         This has no effect on bits in the opcode.  Can also be expressed
177 	as "[pc+]" in input.
178      n  As N, but PC-relative (to the start of the instruction).
179      o	[-128..127] word offset in bits <7:1> and <0>.  Used by 8-bit
180 	branch instructions.
181      O	[-128..127] offset in bits <7:0>.  Also matches a comma and a
182 	general register after the expression, in bits <15:12>.  Used
183 	only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
184      P	Special register in bits <15:12>.
185      p	Indicates that the insn is a prefix insn.  Must be first
186 	character.
187      Q  As O, but don't relax; force an 8-bit offset.
188      R	General register in bits <15:12>.
189      r	General register in bits <3:0>.
190      S	Source operand in bit <10> and a prefix; a 3-operand prefix
191 	without side-effect.
192      s	Source operand in bits <10> and <3:0>, optionally with a
193 	side-effect prefix, except [pc] (the name, not R15 as in ACR)
194 	isn't allowed for v32 and higher.
195      T  Support register in bits <15:12>.
196      u  4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
197      U  Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
198 	Not recognized at disassembly.
199      x	Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
200      y	Like 's' but do not allow an integer at assembly.
201      Y	The difference s-y; only an integer is allowed.
202      z	Size modifier (B or W) in bit <4>.  */
203 
204 
205 /* Please note the order of the opcodes in this table is significant.
206    The assembler requires that all instances of the same mnemonic must
207    be consecutive.  If they aren't, the assembler might not recognize
208    them, or may indicate an internal error.
209 
210    The disassembler should not normally care about the order of the
211    opcodes, but will prefer an earlier alternative if the "match-score"
212    (see cris-dis.c) is computed as equal.
213 
214    It should not be significant for proper execution that this table is
215    in alphabetical order, but please follow that convention for an easy
216    overview.  */
217 
218 const struct cris_opcode
219 cris_opcodes[] =
220 {
221   {"abs",     0x06B0, 0x0940,		  "r,R",     0, SIZE_NONE,     0,
222    cris_abs_op},
223 
224   {"add",     0x0600, 0x09c0,		  "m r,R",   0, SIZE_NONE,     0,
225    cris_reg_mode_add_sub_cmp_and_or_move_op},
226 
227   {"add",     0x0A00, 0x01c0,		  "m s,R",   0, SIZE_FIELD,    0,
228    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
229 
230   {"add",     0x0A00, 0x01c0,		  "m S,D",   0, SIZE_NONE,
231    cris_ver_v0_10,
232    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
233 
234   {"add",     0x0a00, 0x05c0,		  "m S,R,r", 0, SIZE_NONE,
235    cris_ver_v0_10,
236    cris_three_operand_add_sub_cmp_and_or_op},
237 
238   {"add",     0x0A00, 0x01c0,		  "m s,R",   0, SIZE_FIELD,
239    cris_ver_v32p,
240    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
241 
242   {"addc",    0x0570, 0x0A80,		  "r,R",     0, SIZE_FIX_32,
243    cris_ver_v32p,
244    cris_not_implemented_op},
245 
246   {"addc",    0x09A0, 0x0250,		  "s,R",     0, SIZE_FIX_32,
247    cris_ver_v32p,
248    cris_not_implemented_op},
249 
250   {"addi",    0x0540, 0x0A80,		  "x,r,A",   0, SIZE_NONE,
251    cris_ver_v32p,
252    cris_addi_op},
253 
254   {"addi",    0x0500, 0x0Ac0,		  "x,r",     0, SIZE_NONE,     0,
255    cris_addi_op},
256 
257   /* This collates after "addo", but we want to disassemble as "addoq",
258      not "addo".  */
259   {"addoq",   0x0100, 0x0E00,		  "Q,A",     0, SIZE_NONE,
260    cris_ver_v32p,
261    cris_not_implemented_op},
262 
263   {"addo",    0x0940, 0x0280,		  "m s,R,A", 0, SIZE_FIELD_SIGNED,
264    cris_ver_v32p,
265    cris_not_implemented_op},
266 
267   /* This must be located after the insn above, lest we misinterpret
268      "addo.b -1,r0,acr" as "addo .b-1,r0,acr".  FIXME: Sounds like a
269      parser bug.  */
270   {"addo",   0x0100, 0x0E00,		  "O,A",     0, SIZE_NONE,
271    cris_ver_v32p,
272    cris_not_implemented_op},
273 
274   {"addq",    0x0200, 0x0Dc0,		  "I,R",     0, SIZE_NONE,     0,
275    cris_quick_mode_add_sub_op},
276 
277   {"adds",    0x0420, 0x0Bc0,		  "z r,R",   0, SIZE_NONE,     0,
278    cris_reg_mode_add_sub_cmp_and_or_move_op},
279 
280   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
281   {"adds",    0x0820, 0x03c0,		  "z s,R",   0, SIZE_FIELD,    0,
282    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
283 
284   {"adds",    0x0820, 0x03c0,		  "z S,D",   0, SIZE_NONE,
285    cris_ver_v0_10,
286    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
287 
288   {"adds",    0x0820, 0x07c0,		  "z S,R,r", 0, SIZE_NONE,
289    cris_ver_v0_10,
290    cris_three_operand_add_sub_cmp_and_or_op},
291 
292   {"addu",    0x0400, 0x0be0,		  "z r,R",   0, SIZE_NONE,     0,
293    cris_reg_mode_add_sub_cmp_and_or_move_op},
294 
295   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
296   {"addu",    0x0800, 0x03e0,		  "z s,R",   0, SIZE_FIELD,    0,
297    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
298 
299   {"addu",    0x0800, 0x03e0,		  "z S,D",   0, SIZE_NONE,
300    cris_ver_v0_10,
301    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
302 
303   {"addu",    0x0800, 0x07e0,		  "z S,R,r", 0, SIZE_NONE,
304    cris_ver_v0_10,
305    cris_three_operand_add_sub_cmp_and_or_op},
306 
307   {"and",     0x0700, 0x08C0,		  "m r,R",   0, SIZE_NONE,     0,
308    cris_reg_mode_add_sub_cmp_and_or_move_op},
309 
310   {"and",     0x0B00, 0x00C0,		  "m s,R",   0, SIZE_FIELD,    0,
311    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
312 
313   {"and",     0x0B00, 0x00C0,		  "m S,D",   0, SIZE_NONE,
314    cris_ver_v0_10,
315    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
316 
317   {"and",     0x0B00, 0x04C0,		  "m S,R,r", 0, SIZE_NONE,
318    cris_ver_v0_10,
319    cris_three_operand_add_sub_cmp_and_or_op},
320 
321   {"andq",    0x0300, 0x0CC0,		  "i,R",     0, SIZE_NONE,     0,
322    cris_quick_mode_and_cmp_move_or_op},
323 
324   {"asr",     0x0780, 0x0840,		  "m r,R",   0, SIZE_NONE,     0,
325    cris_asr_op},
326 
327   {"asrq",    0x03a0, 0x0c40,		  "c,R",     0, SIZE_NONE,     0,
328    cris_asrq_op},
329 
330   {"ax",      0x15B0, 0xEA4F,		  "",	     0, SIZE_NONE,     0,
331    cris_ax_ei_setf_op},
332 
333   /* FIXME: Should use branch #defines.  */
334   {"b",	      0x0dff, 0x0200,		  "b",	     1, SIZE_NONE,     0,
335    cris_sixteen_bit_offset_branch_op},
336 
337   {"ba",
338    BA_QUICK_OPCODE,
339    0x0F00+(0xF-CC_A)*0x1000,		  "o",	     1, SIZE_NONE,     0,
340    cris_eight_bit_offset_branch_op},
341 
342   /* Needs to come after the usual "ba o", which might be relaxed to
343      this one.  */
344   {"ba",     BA_DWORD_OPCODE,
345    0xffff & (~BA_DWORD_OPCODE),		  "n",	     0, SIZE_FIX_32,
346    cris_ver_v32p,
347    cris_none_reg_mode_jump_op},
348 
349   {"bas",     0x0EBF, 0x0140,		  "n,P",     0, SIZE_FIX_32,
350    cris_ver_v32p,
351    cris_none_reg_mode_jump_op},
352 
353   {"basc",     0x0EFF, 0x0100,		  "n,P",     0, SIZE_FIX_32,
354    cris_ver_v32p,
355    cris_none_reg_mode_jump_op},
356 
357   {"bcc",
358    BRANCH_QUICK_OPCODE+CC_CC*0x1000,
359    0x0f00+(0xF-CC_CC)*0x1000,		  "o",	     1, SIZE_NONE,     0,
360    cris_eight_bit_offset_branch_op},
361 
362   {"bcs",
363    BRANCH_QUICK_OPCODE+CC_CS*0x1000,
364    0x0f00+(0xF-CC_CS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
365    cris_eight_bit_offset_branch_op},
366 
367   {"bdap",
368    BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS,  "pm s,R",  0, SIZE_FIELD_SIGNED,
369    cris_ver_v0_10,
370    cris_bdap_prefix},
371 
372   {"bdap",
373    BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS,  "pO",	     0, SIZE_NONE,
374    cris_ver_v0_10,
375    cris_quick_mode_bdap_prefix},
376 
377   {"beq",
378    BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
379    0x0f00+(0xF-CC_EQ)*0x1000,		  "o",	     1, SIZE_NONE,     0,
380    cris_eight_bit_offset_branch_op},
381 
382   /* This is deliberately put before "bext" to trump it, even though not
383      in alphabetical order, since we don't do excluding version checks
384      for v0..v10.  */
385   {"bwf",
386    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
387    0x0f00+(0xF-CC_EXT)*0x1000,		  "o",	     1, SIZE_NONE,
388    cris_ver_v10,
389    cris_eight_bit_offset_branch_op},
390 
391   {"bext",
392    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
393    0x0f00+(0xF-CC_EXT)*0x1000,		  "o",	     1, SIZE_NONE,
394    cris_ver_v0_3,
395    cris_eight_bit_offset_branch_op},
396 
397   {"bge",
398    BRANCH_QUICK_OPCODE+CC_GE*0x1000,
399    0x0f00+(0xF-CC_GE)*0x1000,		  "o",	     1, SIZE_NONE,     0,
400    cris_eight_bit_offset_branch_op},
401 
402   {"bgt",
403    BRANCH_QUICK_OPCODE+CC_GT*0x1000,
404    0x0f00+(0xF-CC_GT)*0x1000,		  "o",	     1, SIZE_NONE,     0,
405    cris_eight_bit_offset_branch_op},
406 
407   {"bhi",
408    BRANCH_QUICK_OPCODE+CC_HI*0x1000,
409    0x0f00+(0xF-CC_HI)*0x1000,		  "o",	     1, SIZE_NONE,     0,
410    cris_eight_bit_offset_branch_op},
411 
412   {"bhs",
413    BRANCH_QUICK_OPCODE+CC_HS*0x1000,
414    0x0f00+(0xF-CC_HS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
415    cris_eight_bit_offset_branch_op},
416 
417   {"biap", BIAP_OPCODE, BIAP_Z_BITS,	  "pm r,R",  0, SIZE_NONE,
418    cris_ver_v0_10,
419    cris_biap_prefix},
420 
421   {"ble",
422    BRANCH_QUICK_OPCODE+CC_LE*0x1000,
423    0x0f00+(0xF-CC_LE)*0x1000,		  "o",	     1, SIZE_NONE,     0,
424    cris_eight_bit_offset_branch_op},
425 
426   {"blo",
427    BRANCH_QUICK_OPCODE+CC_LO*0x1000,
428    0x0f00+(0xF-CC_LO)*0x1000,		  "o",	     1, SIZE_NONE,     0,
429    cris_eight_bit_offset_branch_op},
430 
431   {"bls",
432    BRANCH_QUICK_OPCODE+CC_LS*0x1000,
433    0x0f00+(0xF-CC_LS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
434    cris_eight_bit_offset_branch_op},
435 
436   {"blt",
437    BRANCH_QUICK_OPCODE+CC_LT*0x1000,
438    0x0f00+(0xF-CC_LT)*0x1000,		  "o",	     1, SIZE_NONE,     0,
439    cris_eight_bit_offset_branch_op},
440 
441   {"bmi",
442    BRANCH_QUICK_OPCODE+CC_MI*0x1000,
443    0x0f00+(0xF-CC_MI)*0x1000,		  "o",	     1, SIZE_NONE,     0,
444    cris_eight_bit_offset_branch_op},
445 
446   {"bmod",    0x0ab0, 0x0140,		  "s,R",     0, SIZE_FIX_32,
447    cris_ver_sim_v0_10,
448    cris_not_implemented_op},
449 
450   {"bmod",    0x0ab0, 0x0140,		  "S,D",     0, SIZE_NONE,
451    cris_ver_sim_v0_10,
452    cris_not_implemented_op},
453 
454   {"bmod",    0x0ab0, 0x0540,		  "S,R,r",   0, SIZE_NONE,
455    cris_ver_sim_v0_10,
456    cris_not_implemented_op},
457 
458   {"bne",
459    BRANCH_QUICK_OPCODE+CC_NE*0x1000,
460    0x0f00+(0xF-CC_NE)*0x1000,		  "o",	     1, SIZE_NONE,     0,
461    cris_eight_bit_offset_branch_op},
462 
463   {"bound",   0x05c0, 0x0A00,		  "m r,R",   0, SIZE_NONE,     0,
464    cris_two_operand_bound_op},
465   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
466   {"bound",   0x09c0, 0x0200,		  "m s,R",   0, SIZE_FIELD,
467    cris_ver_v0_10,
468    cris_two_operand_bound_op},
469   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
470   {"bound",   0x0dcf, 0x0200,		  "m Y,R",   0, SIZE_FIELD,    0,
471    cris_two_operand_bound_op},
472   {"bound",   0x09c0, 0x0200,		  "m S,D",   0, SIZE_NONE,
473    cris_ver_v0_10,
474    cris_two_operand_bound_op},
475   {"bound",   0x09c0, 0x0600,		  "m S,R,r", 0, SIZE_NONE,
476    cris_ver_v0_10,
477    cris_three_operand_bound_op},
478 
479   {"bpl",
480    BRANCH_QUICK_OPCODE+CC_PL*0x1000,
481    0x0f00+(0xF-CC_PL)*0x1000,		  "o",	     1, SIZE_NONE,     0,
482    cris_eight_bit_offset_branch_op},
483 
484   {"break",   0xe930, 0x16c0,		  "C",	     0, SIZE_NONE,
485    cris_ver_v3p,
486    cris_break_op},
487 
488   {"bsb",
489    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
490    0x0f00+(0xF-CC_EXT)*0x1000,		  "o",	     1, SIZE_NONE,
491    cris_ver_v32p,
492    cris_eight_bit_offset_branch_op},
493 
494   {"bsr",     0xBEBF, 0x4140,		  "n",	     0, SIZE_FIX_32,
495    cris_ver_v32p,
496    cris_none_reg_mode_jump_op},
497 
498   {"bsrc",     0xBEFF, 0x4100,		  "n",	     0, SIZE_FIX_32,
499    cris_ver_v32p,
500    cris_none_reg_mode_jump_op},
501 
502   {"bstore",  0x0af0, 0x0100,		  "s,R",     0, SIZE_FIX_32,
503    cris_ver_warning,
504    cris_not_implemented_op},
505 
506   {"bstore",  0x0af0, 0x0100,		  "S,D",     0, SIZE_NONE,
507    cris_ver_warning,
508    cris_not_implemented_op},
509 
510   {"bstore",  0x0af0, 0x0500,		  "S,R,r",   0, SIZE_NONE,
511    cris_ver_warning,
512    cris_not_implemented_op},
513 
514   {"btst",    0x04F0, 0x0B00,		  "r,R",     0, SIZE_NONE,     0,
515    cris_btst_nop_op},
516   {"btstq",   0x0380, 0x0C60,		  "c,R",     0, SIZE_NONE,     0,
517    cris_btst_nop_op},
518 
519   {"bvc",
520    BRANCH_QUICK_OPCODE+CC_VC*0x1000,
521    0x0f00+(0xF-CC_VC)*0x1000,		  "o",	     1, SIZE_NONE,     0,
522    cris_eight_bit_offset_branch_op},
523 
524   {"bvs",
525    BRANCH_QUICK_OPCODE+CC_VS*0x1000,
526    0x0f00+(0xF-CC_VS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
527    cris_eight_bit_offset_branch_op},
528 
529   {"clear",   0x0670, 0x3980,		  "M r",     0, SIZE_NONE,     0,
530    cris_reg_mode_clear_op},
531 
532   {"clear",   0x0A70, 0x3180,		  "M y",     0, SIZE_NONE,     0,
533    cris_none_reg_mode_clear_test_op},
534 
535   {"clear",   0x0A70, 0x3180,		  "M S",     0, SIZE_NONE,
536    cris_ver_v0_10,
537    cris_none_reg_mode_clear_test_op},
538 
539   {"clearf",  0x05F0, 0x0A00,		  "f",	     0, SIZE_NONE,     0,
540    cris_clearf_di_op},
541 
542   {"cmp",     0x06C0, 0x0900,		  "m r,R",   0, SIZE_NONE,     0,
543    cris_reg_mode_add_sub_cmp_and_or_move_op},
544 
545   {"cmp",     0x0Ac0, 0x0100,		  "m s,R",   0, SIZE_FIELD,    0,
546    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
547 
548   {"cmp",     0x0Ac0, 0x0100,		  "m S,D",   0, SIZE_NONE,
549    cris_ver_v0_10,
550    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
551 
552   {"cmpq",    0x02C0, 0x0D00,		  "i,R",     0, SIZE_NONE,     0,
553    cris_quick_mode_and_cmp_move_or_op},
554 
555   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
556   {"cmps",    0x08e0, 0x0300,		  "z s,R",   0, SIZE_FIELD,    0,
557    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
558 
559   {"cmps",    0x08e0, 0x0300,		  "z S,D",   0, SIZE_NONE,
560    cris_ver_v0_10,
561    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
562 
563   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
564   {"cmpu",    0x08c0, 0x0320,		  "z s,R" ,  0, SIZE_FIELD,    0,
565    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
566 
567   {"cmpu",    0x08c0, 0x0320,		  "z S,D",   0, SIZE_NONE,
568    cris_ver_v0_10,
569    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
570 
571   {"di",      0x25F0, 0xDA0F,		  "",	     0, SIZE_NONE,     0,
572    cris_clearf_di_op},
573 
574   {"dip",     DIP_OPCODE, DIP_Z_BITS,	  "ps",	     0, SIZE_FIX_32,
575    cris_ver_v0_10,
576    cris_dip_prefix},
577 
578   {"div",     0x0980, 0x0640,		  "m R,r",   0, SIZE_FIELD,    0,
579    cris_not_implemented_op},
580 
581   {"dstep",   0x06f0, 0x0900,		  "r,R",     0, SIZE_NONE,     0,
582    cris_dstep_logshift_mstep_neg_not_op},
583 
584   {"ei",      0x25B0, 0xDA4F,		  "",	     0, SIZE_NONE,     0,
585    cris_ax_ei_setf_op},
586 
587   {"fidxd",    0x0ab0, 0xf540,		  "[r]",     0, SIZE_NONE,
588    cris_ver_v32p,
589    cris_not_implemented_op},
590 
591   {"fidxi",    0x0d30, 0xF2C0,		  "[r]",     0, SIZE_NONE,
592    cris_ver_v32p,
593    cris_not_implemented_op},
594 
595   {"ftagd",    0x1AB0, 0xE540,		  "[r]",     0, SIZE_NONE,
596    cris_ver_v32p,
597    cris_not_implemented_op},
598 
599   {"ftagi",    0x1D30, 0xE2C0,		  "[r]",     0, SIZE_NONE,
600    cris_ver_v32p,
601    cris_not_implemented_op},
602 
603   {"halt",    0xF930, 0x06CF,		  "",	     0, SIZE_NONE,
604    cris_ver_v32p,
605    cris_not_implemented_op},
606 
607   {"jas",    0x09B0, 0x0640,		  "r,P",     0, SIZE_NONE,
608    cris_ver_v32p,
609    cris_reg_mode_jump_op},
610 
611   {"jas",    0x0DBF, 0x0240,		  "N,P",     0, SIZE_FIX_32,
612    cris_ver_v32p,
613    cris_reg_mode_jump_op},
614 
615   {"jasc",    0x0B30, 0x04C0,		  "r,P",     0, SIZE_NONE,
616    cris_ver_v32p,
617    cris_reg_mode_jump_op},
618 
619   {"jasc",    0x0F3F, 0x00C0,		  "N,P",     0, SIZE_FIX_32,
620    cris_ver_v32p,
621    cris_reg_mode_jump_op},
622 
623   {"jbrc",    0x69b0, 0x9640,		  "r",	     0, SIZE_NONE,
624    cris_ver_v8_10,
625    cris_reg_mode_jump_op},
626 
627   {"jbrc",    0x6930, 0x92c0,		  "s",	     0, SIZE_FIX_32,
628    cris_ver_v8_10,
629    cris_none_reg_mode_jump_op},
630 
631   {"jbrc",    0x6930, 0x92c0,		  "S",	     0, SIZE_NONE,
632    cris_ver_v8_10,
633    cris_none_reg_mode_jump_op},
634 
635   {"jir",     0xA9b0, 0x5640,		  "r",	     0, SIZE_NONE,
636    cris_ver_v8_10,
637    cris_reg_mode_jump_op},
638 
639   {"jir",     0xA930, 0x52c0,		  "s",	     0, SIZE_FIX_32,
640    cris_ver_v8_10,
641    cris_none_reg_mode_jump_op},
642 
643   {"jir",     0xA930, 0x52c0,		  "S",	     0, SIZE_NONE,
644    cris_ver_v8_10,
645    cris_none_reg_mode_jump_op},
646 
647   {"jirc",    0x29b0, 0xd640,		  "r",	     0, SIZE_NONE,
648    cris_ver_v8_10,
649    cris_reg_mode_jump_op},
650 
651   {"jirc",    0x2930, 0xd2c0,		  "s",	     0, SIZE_FIX_32,
652    cris_ver_v8_10,
653    cris_none_reg_mode_jump_op},
654 
655   {"jirc",    0x2930, 0xd2c0,		  "S",	     0, SIZE_NONE,
656    cris_ver_v8_10,
657    cris_none_reg_mode_jump_op},
658 
659   {"jsr",     0xB9b0, 0x4640,		  "r",	     0, SIZE_NONE,     0,
660    cris_reg_mode_jump_op},
661 
662   {"jsr",     0xB930, 0x42c0,		  "s",	     0, SIZE_FIX_32,
663    cris_ver_v0_10,
664    cris_none_reg_mode_jump_op},
665 
666   {"jsr",     0xBDBF, 0x4240,		  "N",	     0, SIZE_FIX_32,
667    cris_ver_v32p,
668    cris_none_reg_mode_jump_op},
669 
670   {"jsr",     0xB930, 0x42c0,		  "S",	     0, SIZE_NONE,
671    cris_ver_v0_10,
672    cris_none_reg_mode_jump_op},
673 
674   {"jsrc",    0x39b0, 0xc640,		  "r",	     0, SIZE_NONE,
675    cris_ver_v8_10,
676    cris_reg_mode_jump_op},
677 
678   {"jsrc",    0x3930, 0xc2c0,		  "s",	     0, SIZE_FIX_32,
679    cris_ver_v8_10,
680    cris_none_reg_mode_jump_op},
681 
682   {"jsrc",    0x3930, 0xc2c0,		  "S",	     0, SIZE_NONE,
683    cris_ver_v8_10,
684    cris_none_reg_mode_jump_op},
685 
686   {"jsrc",    0xBB30, 0x44C0,		  "r",       0, SIZE_NONE,
687    cris_ver_v32p,
688    cris_reg_mode_jump_op},
689 
690   {"jsrc",    0xBF3F, 0x40C0,		  "N",	     0, SIZE_FIX_32,
691    cris_ver_v32p,
692    cris_reg_mode_jump_op},
693 
694   {"jump",    0x09b0, 0xF640,		  "r",	     0, SIZE_NONE,     0,
695    cris_reg_mode_jump_op},
696 
697   {"jump",
698    JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "s",	     0, SIZE_FIX_32,
699    cris_ver_v0_10,
700    cris_none_reg_mode_jump_op},
701 
702   {"jump",
703    JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "S",	     0, SIZE_NONE,
704    cris_ver_v0_10,
705    cris_none_reg_mode_jump_op},
706 
707   {"jump",    0x09F0, 0x060F,		  "P",	     0, SIZE_NONE,
708    cris_ver_v32p,
709    cris_none_reg_mode_jump_op},
710 
711   {"jump",
712    JUMP_PC_INCR_OPCODE_V32,
713    (0xffff & ~JUMP_PC_INCR_OPCODE_V32),	  "N",	     0, SIZE_FIX_32,
714    cris_ver_v32p,
715    cris_none_reg_mode_jump_op},
716 
717   {"jmpu",    0x8930, 0x72c0,		  "s",	     0, SIZE_FIX_32,
718    cris_ver_v10,
719    cris_none_reg_mode_jump_op},
720 
721   {"jmpu",    0x8930, 0x72c0,		   "S",	     0, SIZE_NONE,
722    cris_ver_v10,
723    cris_none_reg_mode_jump_op},
724 
725   {"lapc",    0x0970, 0x0680,		  "U,R",    0, SIZE_NONE,
726    cris_ver_v32p,
727    cris_not_implemented_op},
728 
729   {"lapc",    0x0D7F, 0x0280,		  "dn,R",    0, SIZE_FIX_32,
730    cris_ver_v32p,
731    cris_not_implemented_op},
732 
733   {"lapcq",   0x0970, 0x0680,		  "u,R",     0, SIZE_NONE,
734    cris_ver_v32p,
735    cris_addi_op},
736 
737   {"lsl",     0x04C0, 0x0B00,		  "m r,R",   0, SIZE_NONE,     0,
738    cris_dstep_logshift_mstep_neg_not_op},
739 
740   {"lslq",    0x03c0, 0x0C20,		  "c,R",     0, SIZE_NONE,     0,
741    cris_dstep_logshift_mstep_neg_not_op},
742 
743   {"lsr",     0x07C0, 0x0800,		  "m r,R",   0, SIZE_NONE,     0,
744    cris_dstep_logshift_mstep_neg_not_op},
745 
746   {"lsrq",    0x03e0, 0x0C00,		  "c,R",     0, SIZE_NONE,     0,
747    cris_dstep_logshift_mstep_neg_not_op},
748 
749   {"lz",      0x0730, 0x08C0,		  "r,R",     0, SIZE_NONE,
750    cris_ver_v3p,
751    cris_not_implemented_op},
752 
753   {"mcp",      0x07f0, 0x0800,		  "P,r",     0, SIZE_NONE,
754    cris_ver_v32p,
755    cris_not_implemented_op},
756 
757   {"move",    0x0640, 0x0980,		  "m r,R",   0, SIZE_NONE,     0,
758    cris_reg_mode_add_sub_cmp_and_or_move_op},
759 
760   {"move",    0x0A40, 0x0180,		  "m s,R",   0, SIZE_FIELD,    0,
761    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
762 
763   {"move",    0x0A40, 0x0180,		  "m S,D",   0, SIZE_NONE,
764    cris_ver_v0_10,
765    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
766 
767   {"move",    0x0630, 0x09c0,		  "r,P",     0, SIZE_NONE,     0,
768    cris_move_to_preg_op},
769 
770   {"move",    0x0670, 0x0980,		  "P,r",     0, SIZE_NONE,     0,
771    cris_reg_mode_move_from_preg_op},
772 
773   {"move",    0x0BC0, 0x0000,		  "m R,y",   0, SIZE_FIELD,    0,
774    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
775 
776   {"move",    0x0BC0, 0x0000,		  "m D,S",   0, SIZE_NONE,
777    cris_ver_v0_10,
778    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
779 
780   {"move",
781    MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
782    "s,P",   0, SIZE_SPEC_REG, 0,
783    cris_move_to_preg_op},
784 
785   {"move",    0x0A30, 0x01c0,		  "S,P",     0, SIZE_NONE,
786    cris_ver_v0_10,
787    cris_move_to_preg_op},
788 
789   {"move",    0x0A70, 0x0180,		  "P,y",     0, SIZE_SPEC_REG, 0,
790    cris_none_reg_mode_move_from_preg_op},
791 
792   {"move",    0x0A70, 0x0180,		  "P,S",     0, SIZE_NONE,
793    cris_ver_v0_10,
794    cris_none_reg_mode_move_from_preg_op},
795 
796   {"move",    0x0B70, 0x0480,		  "r,T",     0, SIZE_NONE,
797    cris_ver_v32p,
798    cris_not_implemented_op},
799 
800   {"move",    0x0F70, 0x0080,		  "T,r",     0, SIZE_NONE,
801    cris_ver_v32p,
802    cris_not_implemented_op},
803 
804   {"movem",   0x0BF0, 0x0000,		  "R,y",     0, SIZE_FIX_32,   0,
805    cris_move_reg_to_mem_movem_op},
806 
807   {"movem",   0x0BF0, 0x0000,		  "D,S",     0, SIZE_NONE,
808    cris_ver_v0_10,
809    cris_move_reg_to_mem_movem_op},
810 
811   {"movem",   0x0BB0, 0x0040,		  "s,R",     0, SIZE_FIX_32,   0,
812    cris_move_mem_to_reg_movem_op},
813 
814   {"movem",   0x0BB0, 0x0040,		  "S,D",     0, SIZE_NONE,
815    cris_ver_v0_10,
816    cris_move_mem_to_reg_movem_op},
817 
818   {"moveq",   0x0240, 0x0D80,		  "i,R",     0, SIZE_NONE,     0,
819    cris_quick_mode_and_cmp_move_or_op},
820 
821   {"movs",    0x0460, 0x0B80,		  "z r,R",   0, SIZE_NONE,     0,
822    cris_reg_mode_add_sub_cmp_and_or_move_op},
823 
824   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
825   {"movs",    0x0860, 0x0380,		  "z s,R",   0, SIZE_FIELD,    0,
826    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
827 
828   {"movs",    0x0860, 0x0380,		  "z S,D",   0, SIZE_NONE,
829    cris_ver_v0_10,
830    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
831 
832   {"movu",    0x0440, 0x0Ba0,		  "z r,R",   0, SIZE_NONE,     0,
833    cris_reg_mode_add_sub_cmp_and_or_move_op},
834 
835   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
836   {"movu",    0x0840, 0x03a0,		  "z s,R",   0, SIZE_FIELD,    0,
837    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
838 
839   {"movu",    0x0840, 0x03a0,		  "z S,D",   0, SIZE_NONE,
840    cris_ver_v0_10,
841    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
842 
843   {"mstep",   0x07f0, 0x0800,		  "r,R",     0, SIZE_NONE,
844    cris_ver_v0_10,
845    cris_dstep_logshift_mstep_neg_not_op},
846 
847   {"muls",    0x0d00, 0x02c0,		  "m r,R",   0, SIZE_NONE,
848    cris_ver_v10p,
849    cris_muls_op},
850 
851   {"mulu",    0x0900, 0x06c0,		  "m r,R",   0, SIZE_NONE,
852    cris_ver_v10p,
853    cris_mulu_op},
854 
855   {"neg",     0x0580, 0x0A40,		  "m r,R",   0, SIZE_NONE,     0,
856    cris_dstep_logshift_mstep_neg_not_op},
857 
858   {"nop",     NOP_OPCODE, NOP_Z_BITS,	  "",	     0, SIZE_NONE,
859    cris_ver_v0_10,
860    cris_btst_nop_op},
861 
862   {"nop",     NOP_OPCODE_V32, NOP_Z_BITS_V32, "",    0, SIZE_NONE,
863    cris_ver_v32p,
864    cris_btst_nop_op},
865 
866   {"not",     0x8770, 0x7880,		  "r",	     0, SIZE_NONE,     0,
867    cris_dstep_logshift_mstep_neg_not_op},
868 
869   {"or",      0x0740, 0x0880,		  "m r,R",   0, SIZE_NONE,     0,
870    cris_reg_mode_add_sub_cmp_and_or_move_op},
871 
872   {"or",      0x0B40, 0x0080,		  "m s,R",   0, SIZE_FIELD,    0,
873    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
874 
875   {"or",      0x0B40, 0x0080,		  "m S,D",   0, SIZE_NONE,
876    cris_ver_v0_10,
877    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
878 
879   {"or",      0x0B40, 0x0480,		  "m S,R,r", 0, SIZE_NONE,
880    cris_ver_v0_10,
881    cris_three_operand_add_sub_cmp_and_or_op},
882 
883   {"orq",     0x0340, 0x0C80,		  "i,R",     0, SIZE_NONE,     0,
884    cris_quick_mode_and_cmp_move_or_op},
885 
886   {"pop",     0x0E6E, 0x0191,		  "!R",	     0, SIZE_NONE,
887    cris_ver_v0_10,
888    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
889 
890   {"pop",     0x0e3e, 0x01c1,		  "!P",	     0, SIZE_NONE,
891    cris_ver_v0_10,
892    cris_none_reg_mode_move_from_preg_op},
893 
894   {"push",    0x0FEE, 0x0011,		  "BR",	     0, SIZE_NONE,
895    cris_ver_v0_10,
896    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
897 
898   {"push",    0x0E7E, 0x0181,		  "BP",	     0, SIZE_NONE,
899    cris_ver_v0_10,
900    cris_move_to_preg_op},
901 
902   {"rbf",     0x3b30, 0xc0c0,		  "y",	     0, SIZE_NONE,
903    cris_ver_v10,
904    cris_not_implemented_op},
905 
906   {"rbf",     0x3b30, 0xc0c0,		  "S",	     0, SIZE_NONE,
907    cris_ver_v10,
908    cris_not_implemented_op},
909 
910   {"rfe",     0x2930, 0xD6CF,		  "",	     0, SIZE_NONE,
911    cris_ver_v32p,
912    cris_not_implemented_op},
913 
914   {"rfg",     0x4930, 0xB6CF,		  "",	     0, SIZE_NONE,
915    cris_ver_v32p,
916    cris_not_implemented_op},
917 
918   {"rfn",     0x5930, 0xA6CF,		  "",	     0, SIZE_NONE,
919    cris_ver_v32p,
920    cris_not_implemented_op},
921 
922   {"ret",     0xB67F, 0x4980,		  "",	     1, SIZE_NONE,
923    cris_ver_v0_10,
924    cris_reg_mode_move_from_preg_op},
925 
926   {"ret",     0xB9F0, 0x460F,		  "",	     1, SIZE_NONE,
927    cris_ver_v32p,
928    cris_reg_mode_move_from_preg_op},
929 
930   {"retb",    0xe67f, 0x1980,		  "",	     1, SIZE_NONE,
931    cris_ver_v0_10,
932    cris_reg_mode_move_from_preg_op},
933 
934   {"rete",     0xA9F0, 0x560F,		  "",	     1, SIZE_NONE,
935    cris_ver_v32p,
936    cris_reg_mode_move_from_preg_op},
937 
938   {"reti",    0xA67F, 0x5980,		  "",	     1, SIZE_NONE,
939    cris_ver_v0_10,
940    cris_reg_mode_move_from_preg_op},
941 
942   {"retn",     0xC9F0, 0x360F,		  "",	     1, SIZE_NONE,
943    cris_ver_v32p,
944    cris_reg_mode_move_from_preg_op},
945 
946   {"sbfs",    0x3b70, 0xc080,		  "y",	     0, SIZE_NONE,
947    cris_ver_v10,
948    cris_not_implemented_op},
949 
950   {"sbfs",    0x3b70, 0xc080,		  "S",	     0, SIZE_NONE,
951    cris_ver_v10,
952    cris_not_implemented_op},
953 
954   {"sa",
955    0x0530+CC_A*0x1000,
956    0x0AC0+(0xf-CC_A)*0x1000,		  "r",	     0, SIZE_NONE,     0,
957    cris_scc_op},
958 
959   {"ssb",
960    0x0530+CC_EXT*0x1000,
961    0x0AC0+(0xf-CC_EXT)*0x1000,		  "r",	     0, SIZE_NONE,
962    cris_ver_v32p,
963    cris_scc_op},
964 
965   {"scc",
966    0x0530+CC_CC*0x1000,
967    0x0AC0+(0xf-CC_CC)*0x1000,		  "r",	     0, SIZE_NONE,     0,
968    cris_scc_op},
969 
970   {"scs",
971    0x0530+CC_CS*0x1000,
972    0x0AC0+(0xf-CC_CS)*0x1000,		  "r",	     0, SIZE_NONE,     0,
973    cris_scc_op},
974 
975   {"seq",
976    0x0530+CC_EQ*0x1000,
977    0x0AC0+(0xf-CC_EQ)*0x1000,		  "r",	     0, SIZE_NONE,     0,
978    cris_scc_op},
979 
980   {"setf",    0x05b0, 0x0A40,		  "f",	     0, SIZE_NONE,     0,
981    cris_ax_ei_setf_op},
982 
983   {"sfe",    0x3930, 0xC6CF,		  "",	     0, SIZE_NONE,
984    cris_ver_v32p,
985    cris_not_implemented_op},
986 
987   /* Need to have "swf" in front of "sext" so it is the one displayed in
988      disassembly.  */
989   {"swf",
990    0x0530+CC_EXT*0x1000,
991    0x0AC0+(0xf-CC_EXT)*0x1000,		  "r",	     0, SIZE_NONE,
992    cris_ver_v10,
993    cris_scc_op},
994 
995   {"sext",
996    0x0530+CC_EXT*0x1000,
997    0x0AC0+(0xf-CC_EXT)*0x1000,		  "r",	     0, SIZE_NONE,
998    cris_ver_v0_3,
999    cris_scc_op},
1000 
1001   {"sge",
1002    0x0530+CC_GE*0x1000,
1003    0x0AC0+(0xf-CC_GE)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1004    cris_scc_op},
1005 
1006   {"sgt",
1007    0x0530+CC_GT*0x1000,
1008    0x0AC0+(0xf-CC_GT)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1009    cris_scc_op},
1010 
1011   {"shi",
1012    0x0530+CC_HI*0x1000,
1013    0x0AC0+(0xf-CC_HI)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1014    cris_scc_op},
1015 
1016   {"shs",
1017    0x0530+CC_HS*0x1000,
1018    0x0AC0+(0xf-CC_HS)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1019    cris_scc_op},
1020 
1021   {"sle",
1022    0x0530+CC_LE*0x1000,
1023    0x0AC0+(0xf-CC_LE)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1024    cris_scc_op},
1025 
1026   {"slo",
1027    0x0530+CC_LO*0x1000,
1028    0x0AC0+(0xf-CC_LO)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1029    cris_scc_op},
1030 
1031   {"sls",
1032    0x0530+CC_LS*0x1000,
1033    0x0AC0+(0xf-CC_LS)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1034    cris_scc_op},
1035 
1036   {"slt",
1037    0x0530+CC_LT*0x1000,
1038    0x0AC0+(0xf-CC_LT)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1039    cris_scc_op},
1040 
1041   {"smi",
1042    0x0530+CC_MI*0x1000,
1043    0x0AC0+(0xf-CC_MI)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1044    cris_scc_op},
1045 
1046   {"sne",
1047    0x0530+CC_NE*0x1000,
1048    0x0AC0+(0xf-CC_NE)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1049    cris_scc_op},
1050 
1051   {"spl",
1052    0x0530+CC_PL*0x1000,
1053    0x0AC0+(0xf-CC_PL)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1054    cris_scc_op},
1055 
1056   {"sub",     0x0680, 0x0940,		  "m r,R",   0, SIZE_NONE,     0,
1057    cris_reg_mode_add_sub_cmp_and_or_move_op},
1058 
1059   {"sub",     0x0a80, 0x0140,		  "m s,R",   0, SIZE_FIELD,    0,
1060    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1061 
1062   {"sub",     0x0a80, 0x0140,		  "m S,D",   0, SIZE_NONE,
1063    cris_ver_v0_10,
1064    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1065 
1066   {"sub",     0x0a80, 0x0540,		  "m S,R,r", 0, SIZE_NONE,
1067    cris_ver_v0_10,
1068    cris_three_operand_add_sub_cmp_and_or_op},
1069 
1070   {"subq",    0x0280, 0x0d40,		  "I,R",     0, SIZE_NONE,     0,
1071    cris_quick_mode_add_sub_op},
1072 
1073   {"subs",    0x04a0, 0x0b40,		  "z r,R",   0, SIZE_NONE,     0,
1074    cris_reg_mode_add_sub_cmp_and_or_move_op},
1075 
1076   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
1077   {"subs",    0x08a0, 0x0340,		  "z s,R",   0, SIZE_FIELD,    0,
1078    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1079 
1080   {"subs",    0x08a0, 0x0340,		  "z S,D",   0, SIZE_NONE,
1081    cris_ver_v0_10,
1082    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1083 
1084   {"subs",    0x08a0, 0x0740,		  "z S,R,r", 0, SIZE_NONE,
1085    cris_ver_v0_10,
1086    cris_three_operand_add_sub_cmp_and_or_op},
1087 
1088   {"subu",    0x0480, 0x0b60,		  "z r,R",   0, SIZE_NONE,     0,
1089    cris_reg_mode_add_sub_cmp_and_or_move_op},
1090 
1091   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
1092   {"subu",    0x0880, 0x0360,		  "z s,R",   0, SIZE_FIELD,    0,
1093    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1094 
1095   {"subu",    0x0880, 0x0360,		  "z S,D",   0, SIZE_NONE,
1096    cris_ver_v0_10,
1097    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1098 
1099   {"subu",    0x0880, 0x0760,		  "z S,R,r", 0, SIZE_NONE,
1100    cris_ver_v0_10,
1101    cris_three_operand_add_sub_cmp_and_or_op},
1102 
1103   {"svc",
1104    0x0530+CC_VC*0x1000,
1105    0x0AC0+(0xf-CC_VC)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1106    cris_scc_op},
1107 
1108   {"svs",
1109    0x0530+CC_VS*0x1000,
1110    0x0AC0+(0xf-CC_VS)*0x1000,		  "r",	     0, SIZE_NONE,     0,
1111    cris_scc_op},
1112 
1113   /* The insn "swapn" is the same as "not" and will be disassembled as
1114      such, but the swap* family of mnmonics are generally v8-and-higher
1115      only, so count it in.  */
1116   {"swapn",   0x8770, 0x7880,		  "r",	     0, SIZE_NONE,
1117    cris_ver_v8p,
1118    cris_not_implemented_op},
1119 
1120   {"swapw",   0x4770, 0xb880,		  "r",	     0, SIZE_NONE,
1121    cris_ver_v8p,
1122    cris_not_implemented_op},
1123 
1124   {"swapnw",  0xc770, 0x3880,		  "r",	     0, SIZE_NONE,
1125    cris_ver_v8p,
1126    cris_not_implemented_op},
1127 
1128   {"swapb",   0x2770, 0xd880,		  "r",	     0, SIZE_NONE,
1129    cris_ver_v8p,
1130    cris_not_implemented_op},
1131 
1132   {"swapnb",  0xA770, 0x5880,		  "r",	     0, SIZE_NONE,
1133    cris_ver_v8p,
1134    cris_not_implemented_op},
1135 
1136   {"swapwb",  0x6770, 0x9880,		  "r",	     0, SIZE_NONE,
1137    cris_ver_v8p,
1138    cris_not_implemented_op},
1139 
1140   {"swapnwb", 0xE770, 0x1880,		  "r",	     0, SIZE_NONE,
1141    cris_ver_v8p,
1142    cris_not_implemented_op},
1143 
1144   {"swapr",   0x1770, 0xe880,		  "r",	     0, SIZE_NONE,
1145    cris_ver_v8p,
1146    cris_not_implemented_op},
1147 
1148   {"swapnr",  0x9770, 0x6880,		  "r",	     0, SIZE_NONE,
1149    cris_ver_v8p,
1150    cris_not_implemented_op},
1151 
1152   {"swapwr",  0x5770, 0xa880,		  "r",	     0, SIZE_NONE,
1153    cris_ver_v8p,
1154    cris_not_implemented_op},
1155 
1156   {"swapnwr", 0xd770, 0x2880,		  "r",	     0, SIZE_NONE,
1157    cris_ver_v8p,
1158    cris_not_implemented_op},
1159 
1160   {"swapbr",  0x3770, 0xc880,		  "r",	     0, SIZE_NONE,
1161    cris_ver_v8p,
1162    cris_not_implemented_op},
1163 
1164   {"swapnbr", 0xb770, 0x4880,		  "r",	     0, SIZE_NONE,
1165    cris_ver_v8p,
1166    cris_not_implemented_op},
1167 
1168   {"swapwbr", 0x7770, 0x8880,		  "r",	     0, SIZE_NONE,
1169    cris_ver_v8p,
1170    cris_not_implemented_op},
1171 
1172   {"swapnwbr", 0xf770, 0x0880,		  "r",	     0, SIZE_NONE,
1173    cris_ver_v8p,
1174    cris_not_implemented_op},
1175 
1176   {"test",    0x0640, 0x0980,		  "m D",     0, SIZE_NONE,
1177    cris_ver_v0_10,
1178    cris_reg_mode_test_op},
1179 
1180   {"test",    0x0b80, 0xf040,		  "m y",     0, SIZE_FIELD,    0,
1181    cris_none_reg_mode_clear_test_op},
1182 
1183   {"test",    0x0b80, 0xf040,		  "m S",     0, SIZE_NONE,
1184    cris_ver_v0_10,
1185    cris_none_reg_mode_clear_test_op},
1186 
1187   {"xor",     0x07B0, 0x0840,		  "r,R",     0, SIZE_NONE,     0,
1188    cris_xor_op},
1189 
1190   {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
1191 };
1192 
1193 /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
1194 const char * const
1195 cris_cc_strings[] =
1196 {
1197   "hs",
1198   "lo",
1199   "ne",
1200   "eq",
1201   "vc",
1202   "vs",
1203   "pl",
1204   "mi",
1205   "ls",
1206   "hi",
1207   "ge",
1208   "lt",
1209   "gt",
1210   "le",
1211   "a",
1212   /* This is a placeholder.  In v0, this would be "ext".  In v32, this
1213      is "sb".  See cris_conds15.  */
1214   "wf"
1215 };
1216 
1217 /* Different names and semantics for condition 1111 (0xf).  */
1218 const struct cris_cond15 cris_cond15s[] =
1219 {
1220   /* FIXME: In what version did condition "ext" disappear?  */
1221   {"ext", cris_ver_v0_3},
1222   {"wf", cris_ver_v10},
1223   {"sb", cris_ver_v32p},
1224   {NULL, 0}
1225 };
1226 
1227 
1228 /*
1229  * Local variables:
1230  * eval: (c-set-style "gnu")
1231  * indent-tabs-mode: t
1232  * End:
1233  */
1234 
1235 
1236 /* No instruction will be disassembled longer than this.  In theory, and
1237    in silicon, address prefixes can be cascaded.  In practice, cascading
1238    is not used by GCC, and not supported by the assembler.  */
1239 #ifndef MAX_BYTES_PER_CRIS_INSN
1240 #define MAX_BYTES_PER_CRIS_INSN 8
1241 #endif
1242 
1243 /* Whether or not to decode prefixes, folding it into the following
1244    instruction.  FIXME: Make this optional later.  */
1245 #ifndef PARSE_PREFIX
1246 #define PARSE_PREFIX 1
1247 #endif
1248 
1249 /* Sometimes we prefix all registers with this character.  */
1250 #define REGISTER_PREFIX_CHAR '$'
1251 
1252 /* Whether or not to trace the following sequence:
1253    sub* X,r%d
1254    bound* Y,r%d
1255    adds.w [pc+r%d.w],pc
1256 
1257    This is the assembly form of a switch-statement in C.
1258    The "sub is optional.  If there is none, then X will be zero.
1259    X is the value of the first case,
1260    Y is the number of cases (including default).
1261 
1262    This results in case offsets printed on the form:
1263     case N: -> case_address
1264    where N is an estimation on the corresponding 'case' operand in C,
1265    and case_address is where execution of that case continues after the
1266    sequence presented above.
1267 
1268    The old style of output was to print the offsets as instructions,
1269    which made it hard to follow "case"-constructs in the disassembly,
1270    and caused a lot of annoying warnings about undefined instructions.
1271 
1272    FIXME: Make this optional later.  */
1273 #ifndef TRACE_CASE
1274 #define TRACE_CASE (disdata->trace_case)
1275 #endif
1276 
1277 enum cris_disass_family
1278  { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 };
1279 
1280 /* Stored in the disasm_info->private_data member.  */
1281 struct cris_disasm_data
1282 {
1283   /* Whether to print something less confusing if we find something
1284      matching a switch-construct.  */
1285   bfd_boolean trace_case;
1286 
1287   /* Whether this code is flagged as crisv32.  FIXME: Should be an enum
1288      that includes "compatible".  */
1289   enum cris_disass_family distype;
1290 };
1291 
1292 /* Value of first element in switch.  */
1293 static long case_offset = 0;
1294 
1295 /* How many more case-offsets to print.  */
1296 static long case_offset_counter = 0;
1297 
1298 /* Number of case offsets.  */
1299 static long no_of_case_offsets = 0;
1300 
1301 /* Candidate for next case_offset.  */
1302 static long last_immediate = 0;
1303 
1304 static int cris_constraint
1305   (const char *, unsigned, unsigned, struct cris_disasm_data *);
1306 
1307 /* Parse disassembler options and store state in info.  FIXME: For the
1308    time being, we abuse static variables.  */
1309 
1310 static bfd_boolean
cris_parse_disassembler_options(disassemble_info * info,enum cris_disass_family distype)1311 cris_parse_disassembler_options (disassemble_info *info,
1312 				 enum cris_disass_family distype)
1313 {
1314   struct cris_disasm_data *disdata;
1315 
1316   info->private_data = calloc (1, sizeof (struct cris_disasm_data));
1317   disdata = (struct cris_disasm_data *) info->private_data;
1318   if (disdata == NULL)
1319     return false;
1320 
1321   /* Default true.  */
1322   disdata->trace_case
1323     = (info->disassembler_options == NULL
1324        || (strcmp (info->disassembler_options, "nocase") != 0));
1325 
1326   disdata->distype = distype;
1327   return true;
1328 }
1329 
1330 static const struct cris_spec_reg *
spec_reg_info(unsigned int sreg,enum cris_disass_family distype)1331 spec_reg_info (unsigned int sreg, enum cris_disass_family distype)
1332 {
1333   int i;
1334 
1335   for (i = 0; cris_spec_regs[i].name != NULL; i++)
1336     {
1337       if (cris_spec_regs[i].number == sreg)
1338 	{
1339 	  if (distype == cris_dis_v32)
1340 	    switch (cris_spec_regs[i].applicable_version)
1341 	      {
1342 	      case cris_ver_warning:
1343 	      case cris_ver_version_all:
1344 	      case cris_ver_v3p:
1345 	      case cris_ver_v8p:
1346 	      case cris_ver_v10p:
1347 	      case cris_ver_v32p:
1348 		/* No ambiguous sizes or register names with CRISv32.  */
1349 		if (cris_spec_regs[i].warning == NULL)
1350 		  return &cris_spec_regs[i];
1351 	      default:
1352 		;
1353 	      }
1354 	  else if (cris_spec_regs[i].applicable_version != cris_ver_v32p)
1355 	    return &cris_spec_regs[i];
1356 	}
1357     }
1358 
1359   return NULL;
1360 }
1361 
1362 /* Return the number of bits in the argument.  */
1363 
1364 static int
number_of_bits(unsigned int val)1365 number_of_bits (unsigned int val)
1366 {
1367   int bits;
1368 
1369   for (bits = 0; val != 0; val &= val - 1)
1370     bits++;
1371 
1372   return bits;
1373 }
1374 
1375 /* Get an entry in the opcode-table.  */
1376 
1377 static const struct cris_opcode *
get_opcode_entry(unsigned int insn,unsigned int prefix_insn,struct cris_disasm_data * disdata)1378 get_opcode_entry (unsigned int insn,
1379 		  unsigned int prefix_insn,
1380 		  struct cris_disasm_data *disdata)
1381 {
1382   /* For non-prefixed insns, we keep a table of pointers, indexed by the
1383      insn code.  Each entry is initialized when found to be NULL.  */
1384   static const struct cris_opcode **opc_table = NULL;
1385 
1386   const struct cris_opcode *max_matchedp = NULL;
1387   const struct cris_opcode **prefix_opc_table = NULL;
1388 
1389   /* We hold a table for each prefix that need to be handled differently.  */
1390   static const struct cris_opcode **dip_prefixes = NULL;
1391   static const struct cris_opcode **bdapq_m1_prefixes = NULL;
1392   static const struct cris_opcode **bdapq_m2_prefixes = NULL;
1393   static const struct cris_opcode **bdapq_m4_prefixes = NULL;
1394   static const struct cris_opcode **rest_prefixes = NULL;
1395 
1396   /* Allocate and clear the opcode-table.  */
1397   if (opc_table == NULL)
1398     {
1399       opc_table = qemu_malloc (65536 * sizeof (opc_table[0]));
1400 
1401       memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *));
1402 
1403       dip_prefixes
1404 	= qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1405 
1406       memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0]));
1407 
1408       bdapq_m1_prefixes
1409 	= qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1410 
1411       memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0]));
1412 
1413       bdapq_m2_prefixes
1414 	= qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1415 
1416       memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0]));
1417 
1418       bdapq_m4_prefixes
1419 	= qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1420 
1421       memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0]));
1422 
1423       rest_prefixes
1424 	= qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1425 
1426       memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0]));
1427     }
1428 
1429   /* Get the right table if this is a prefix.
1430      This code is connected to cris_constraints in that it knows what
1431      prefixes play a role in recognition of patterns; the necessary
1432      state is reflected by which table is used.  If constraints
1433      involving match or non-match of prefix insns are changed, then this
1434      probably needs changing too.  */
1435   if (prefix_insn != NO_CRIS_PREFIX)
1436     {
1437       const struct cris_opcode *popcodep
1438 	= (opc_table[prefix_insn] != NULL
1439 	   ? opc_table[prefix_insn]
1440 	   : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata));
1441 
1442       if (popcodep == NULL)
1443 	return NULL;
1444 
1445       if (popcodep->match == BDAP_QUICK_OPCODE)
1446 	{
1447 	  /* Since some offsets are recognized with "push" macros, we
1448 	     have to have different tables for them.  */
1449 	  int offset = (prefix_insn & 255);
1450 
1451 	  if (offset > 127)
1452 	    offset -= 256;
1453 
1454 	  switch (offset)
1455 	    {
1456 	    case -4:
1457 	      prefix_opc_table = bdapq_m4_prefixes;
1458 	      break;
1459 
1460 	    case -2:
1461 	      prefix_opc_table = bdapq_m2_prefixes;
1462 	      break;
1463 
1464 	    case -1:
1465 	      prefix_opc_table = bdapq_m1_prefixes;
1466 	      break;
1467 
1468 	    default:
1469 	      prefix_opc_table = rest_prefixes;
1470 	      break;
1471 	    }
1472 	}
1473       else if (popcodep->match == DIP_OPCODE)
1474 	/* We don't allow postincrement when the prefix is DIP, so use a
1475 	   different table for DIP.  */
1476 	prefix_opc_table = dip_prefixes;
1477       else
1478 	prefix_opc_table = rest_prefixes;
1479     }
1480 
1481   if (prefix_insn != NO_CRIS_PREFIX
1482       && prefix_opc_table[insn] != NULL)
1483     max_matchedp = prefix_opc_table[insn];
1484   else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL)
1485     max_matchedp = opc_table[insn];
1486   else
1487     {
1488       const struct cris_opcode *opcodep;
1489       int max_level_of_match = -1;
1490 
1491       for (opcodep = cris_opcodes;
1492 	   opcodep->name != NULL;
1493 	   opcodep++)
1494 	{
1495 	  int level_of_match;
1496 
1497 	  if (disdata->distype == cris_dis_v32)
1498 	    {
1499 	      switch (opcodep->applicable_version)
1500 		{
1501 		case cris_ver_version_all:
1502 		  break;
1503 
1504 		case cris_ver_v0_3:
1505 		case cris_ver_v0_10:
1506 		case cris_ver_v3_10:
1507 		case cris_ver_sim_v0_10:
1508 		case cris_ver_v8_10:
1509 		case cris_ver_v10:
1510 		case cris_ver_warning:
1511 		  continue;
1512 
1513 		case cris_ver_v3p:
1514 		case cris_ver_v8p:
1515 		case cris_ver_v10p:
1516 		case cris_ver_v32p:
1517 		  break;
1518 
1519 		case cris_ver_v8:
1520 		  abort ();
1521 		default:
1522 		  abort ();
1523 		}
1524 	    }
1525 	  else
1526 	    {
1527 	      switch (opcodep->applicable_version)
1528 		{
1529 		case cris_ver_version_all:
1530 		case cris_ver_v0_3:
1531 		case cris_ver_v3p:
1532 		case cris_ver_v0_10:
1533 		case cris_ver_v8p:
1534 		case cris_ver_v8_10:
1535 		case cris_ver_v10:
1536 		case cris_ver_sim_v0_10:
1537 		case cris_ver_v10p:
1538 		case cris_ver_warning:
1539 		  break;
1540 
1541 		case cris_ver_v32p:
1542 		  continue;
1543 
1544 		case cris_ver_v8:
1545 		  abort ();
1546 		default:
1547 		  abort ();
1548 		}
1549 	    }
1550 
1551 	  /* We give a double lead for bits matching the template in
1552 	     cris_opcodes.  Not even, because then "move p8,r10" would
1553 	     be given 2 bits lead over "clear.d r10".  When there's a
1554 	     tie, the first entry in the table wins.  This is
1555 	     deliberate, to avoid a more complicated recognition
1556 	     formula.  */
1557 	  if ((opcodep->match & insn) == opcodep->match
1558 	      && (opcodep->lose & insn) == 0
1559 	      && ((level_of_match
1560 		   = cris_constraint (opcodep->args,
1561 				      insn,
1562 				      prefix_insn,
1563 				      disdata))
1564 		  >= 0)
1565 	      && ((level_of_match
1566 		   += 2 * number_of_bits (opcodep->match
1567 					  | opcodep->lose))
1568 			  > max_level_of_match))
1569 		    {
1570 		      max_matchedp = opcodep;
1571 		      max_level_of_match = level_of_match;
1572 
1573 		      /* If there was a full match, never mind looking
1574 			 further.  */
1575 		      if (level_of_match >= 2 * 16)
1576 			break;
1577 		    }
1578 		}
1579       /* Fill in the new entry.
1580 
1581 	 If there are changes to the opcode-table involving prefixes, and
1582 	 disassembly then does not work correctly, try removing the
1583 	 else-clause below that fills in the prefix-table.  If that
1584 	 helps, you need to change the prefix_opc_table setting above, or
1585 	 something related.  */
1586       if (prefix_insn == NO_CRIS_PREFIX)
1587 	opc_table[insn] = max_matchedp;
1588       else
1589 	prefix_opc_table[insn] = max_matchedp;
1590     }
1591 
1592   return max_matchedp;
1593 }
1594 
1595 /* Return -1 if the constraints of a bitwise-matched instruction say
1596    that there is no match.  Otherwise return a nonnegative number
1597    indicating the confidence in the match (higher is better).  */
1598 
1599 static int
cris_constraint(const char * cs,unsigned int insn,unsigned int prefix_insn,struct cris_disasm_data * disdata)1600 cris_constraint (const char *cs,
1601 		 unsigned int insn,
1602 		 unsigned int prefix_insn,
1603 		 struct cris_disasm_data *disdata)
1604 {
1605   int retval = 0;
1606   int tmp;
1607   int prefix_ok = 0;
1608   const char *s;
1609 
1610   for (s = cs; *s; s++)
1611     switch (*s)
1612       {
1613       case '!':
1614 	/* Do not recognize "pop" if there's a prefix and then only for
1615            v0..v10.  */
1616 	if (prefix_insn != NO_CRIS_PREFIX
1617 	    || disdata->distype != cris_dis_v0_v10)
1618 	  return -1;
1619 	break;
1620 
1621       case 'U':
1622 	/* Not recognized at disassembly.  */
1623 	return -1;
1624 
1625       case 'M':
1626 	/* Size modifier for "clear", i.e. special register 0, 4 or 8.
1627 	   Check that it is one of them.  Only special register 12 could
1628 	   be mismatched, but checking for matches is more logical than
1629 	   checking for mismatches when there are only a few cases.  */
1630 	tmp = ((insn >> 12) & 0xf);
1631 	if (tmp != 0 && tmp != 4 && tmp != 8)
1632 	  return -1;
1633 	break;
1634 
1635       case 'm':
1636 	if ((insn & 0x30) == 0x30)
1637 	  return -1;
1638 	break;
1639 
1640       case 'S':
1641 	/* A prefix operand without side-effect.  */
1642 	if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0)
1643 	  {
1644 	    prefix_ok = 1;
1645 	    break;
1646 	  }
1647 	else
1648 	  return -1;
1649 
1650       case 's':
1651       case 'y':
1652       case 'Y':
1653 	/* If this is a prefixed insn with postincrement (side-effect),
1654 	   the prefix must not be DIP.  */
1655 	if (prefix_insn != NO_CRIS_PREFIX)
1656 	  {
1657 	    if (insn & 0x400)
1658 	      {
1659 		const struct cris_opcode *prefix_opcodep
1660 		  = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1661 
1662 		if (prefix_opcodep->match == DIP_OPCODE)
1663 		  return -1;
1664 	      }
1665 
1666 	    prefix_ok = 1;
1667 	  }
1668 	break;
1669 
1670       case 'B':
1671 	/* If we don't fall through, then the prefix is ok.  */
1672 	prefix_ok = 1;
1673 
1674 	/* A "push" prefix.  Check for valid "push" size.
1675 	   In case of special register, it may be != 4.  */
1676 	if (prefix_insn != NO_CRIS_PREFIX)
1677 	  {
1678 	    /* Match the prefix insn to BDAPQ.  */
1679 	    const struct cris_opcode *prefix_opcodep
1680 	      = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1681 
1682 	    if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
1683 	      {
1684 		int pushsize = (prefix_insn & 255);
1685 
1686 		if (pushsize > 127)
1687 		  pushsize -= 256;
1688 
1689 		if (s[1] == 'P')
1690 		  {
1691 		    unsigned int spec_reg = (insn >> 12) & 15;
1692 		    const struct cris_spec_reg *sregp
1693 		      = spec_reg_info (spec_reg, disdata->distype);
1694 
1695 		    /* For a special-register, the "prefix size" must
1696 		       match the size of the register.  */
1697 		    if (sregp && sregp->reg_size == (unsigned int) -pushsize)
1698 		      break;
1699 		  }
1700 		else if (s[1] == 'R')
1701 		  {
1702 		    if ((insn & 0x30) == 0x20 && pushsize == -4)
1703 		      break;
1704 		  }
1705 		/* FIXME:  Should abort here; next constraint letter
1706 		   *must* be 'P' or 'R'.  */
1707 	      }
1708 	  }
1709 	return -1;
1710 
1711       case 'D':
1712 	retval = (((insn >> 12) & 15) == (insn & 15));
1713 	if (!retval)
1714 	  return -1;
1715 	else
1716 	  retval += 4;
1717 	break;
1718 
1719       case 'P':
1720 	{
1721 	  const struct cris_spec_reg *sregp
1722 	    = spec_reg_info ((insn >> 12) & 15, disdata->distype);
1723 
1724 	  /* Since we match four bits, we will give a value of 4-1 = 3
1725 	     in a match.  If there is a corresponding exact match of a
1726 	     special register in another pattern, it will get a value of
1727 	     4, which will be higher.  This should be correct in that an
1728 	     exact pattern would match better than a general pattern.
1729 
1730 	     Note that there is a reason for not returning zero; the
1731 	     pattern for "clear" is partly  matched in the bit-pattern
1732 	     (the two lower bits must be zero), while the bit-pattern
1733 	     for a move from a special register is matched in the
1734 	     register constraint.  */
1735 
1736 	  if (sregp != NULL)
1737 	    {
1738 	      retval += 3;
1739 	      break;
1740 	    }
1741 	  else
1742 	    return -1;
1743 	}
1744       }
1745 
1746   if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok)
1747     return -1;
1748 
1749   return retval;
1750 }
1751 
1752 /* Format number as hex with a leading "0x" into outbuffer.  */
1753 
1754 static char *
format_hex(unsigned long number,char * outbuffer,struct cris_disasm_data * disdata)1755 format_hex (unsigned long number,
1756 	    char *outbuffer,
1757 	    struct cris_disasm_data *disdata)
1758 {
1759   /* Truncate negative numbers on >32-bit hosts.  */
1760   number &= 0xffffffff;
1761 
1762   sprintf (outbuffer, "0x%lx", number);
1763 
1764   /* Save this value for the "case" support.  */
1765   if (TRACE_CASE)
1766     last_immediate = number;
1767 
1768   return outbuffer + strlen (outbuffer);
1769 }
1770 
1771 /* Format number as decimal into outbuffer.  Parameter signedp says
1772    whether the number should be formatted as signed (!= 0) or
1773    unsigned (== 0).  */
1774 
1775 static char *
format_dec(long number,char * outbuffer,int signedp)1776 format_dec (long number, char *outbuffer, int signedp)
1777 {
1778   last_immediate = number;
1779   sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
1780 
1781   return outbuffer + strlen (outbuffer);
1782 }
1783 
1784 /* Format the name of the general register regno into outbuffer.  */
1785 
1786 static char *
format_reg(struct cris_disasm_data * disdata,int regno,char * outbuffer_start,bfd_boolean with_reg_prefix)1787 format_reg (struct cris_disasm_data *disdata,
1788 	    int regno,
1789 	    char *outbuffer_start,
1790 	    bfd_boolean with_reg_prefix)
1791 {
1792   char *outbuffer = outbuffer_start;
1793 
1794   if (with_reg_prefix)
1795     *outbuffer++ = REGISTER_PREFIX_CHAR;
1796 
1797   switch (regno)
1798     {
1799     case 15:
1800       /* For v32, there is no context in which we output PC.  */
1801       if (disdata->distype == cris_dis_v32)
1802 	strcpy (outbuffer, "acr");
1803       else
1804 	strcpy (outbuffer, "pc");
1805       break;
1806 
1807     case 14:
1808       strcpy (outbuffer, "sp");
1809       break;
1810 
1811     default:
1812       sprintf (outbuffer, "r%d", regno);
1813       break;
1814     }
1815 
1816   return outbuffer_start + strlen (outbuffer_start);
1817 }
1818 
1819 /* Format the name of a support register into outbuffer.  */
1820 
1821 static char *
format_sup_reg(unsigned int regno,char * outbuffer_start,bfd_boolean with_reg_prefix)1822 format_sup_reg (unsigned int regno,
1823 		char *outbuffer_start,
1824 		bfd_boolean with_reg_prefix)
1825 {
1826   char *outbuffer = outbuffer_start;
1827   int i;
1828 
1829   if (with_reg_prefix)
1830     *outbuffer++ = REGISTER_PREFIX_CHAR;
1831 
1832   for (i = 0; cris_support_regs[i].name != NULL; i++)
1833     if (cris_support_regs[i].number == regno)
1834       {
1835 	sprintf (outbuffer, "%s", cris_support_regs[i].name);
1836 	return outbuffer_start + strlen (outbuffer_start);
1837       }
1838 
1839   /* There's supposed to be register names covering all numbers, though
1840      some may be generic names.  */
1841   sprintf (outbuffer, "format_sup_reg-BUG");
1842   return outbuffer_start + strlen (outbuffer_start);
1843 }
1844 
1845 /* Return the length of an instruction.  */
1846 
1847 static unsigned
bytes_to_skip(unsigned int insn,const struct cris_opcode * matchedp,enum cris_disass_family distype,const struct cris_opcode * prefix_matchedp)1848 bytes_to_skip (unsigned int insn,
1849 	       const struct cris_opcode *matchedp,
1850 	       enum cris_disass_family distype,
1851 	       const struct cris_opcode *prefix_matchedp)
1852 {
1853   /* Each insn is a word plus "immediate" operands.  */
1854   unsigned to_skip = 2;
1855   const char *template = matchedp->args;
1856   const char *s;
1857 
1858   for (s = template; *s; s++)
1859     if ((*s == 's' || *s == 'N' || *s == 'Y')
1860 	&& (insn & 0x400) && (insn & 15) == 15
1861 	&& prefix_matchedp == NULL)
1862       {
1863 	/* Immediate via [pc+], so we have to check the size of the
1864 	   operand.  */
1865 	int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3));
1866 
1867 	if (matchedp->imm_oprnd_size == SIZE_FIX_32)
1868 	  to_skip += 4;
1869 	else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG)
1870 	  {
1871 	    const struct cris_spec_reg *sregp
1872 	      = spec_reg_info ((insn >> 12) & 15, distype);
1873 
1874 	    /* FIXME: Improve error handling; should have been caught
1875 	       earlier.  */
1876 	    if (sregp == NULL)
1877 	      return 2;
1878 
1879 	    /* PC is incremented by two, not one, for a byte.  Except on
1880 	       CRISv32, where constants are always DWORD-size for
1881 	       special registers.  */
1882 	    to_skip +=
1883 	      distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1;
1884 	  }
1885 	else
1886 	  to_skip += (mode_size + 1) & ~1;
1887       }
1888     else if (*s == 'n')
1889       to_skip += 4;
1890     else if (*s == 'b')
1891       to_skip += 2;
1892 
1893   return to_skip;
1894 }
1895 
1896 /* Print condition code flags.  */
1897 
1898 static char *
print_flags(struct cris_disasm_data * disdata,unsigned int insn,char * cp)1899 print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp)
1900 {
1901   /* Use the v8 (Etrax 100) flag definitions for disassembly.
1902      The differences with v0 (Etrax 1..4) vs. Svinto are:
1903       v0 'd' <=> v8 'm'
1904       v0 'e' <=> v8 'b'.
1905      FIXME: Emit v0..v3 flag names somehow.  */
1906   static const char v8_fnames[] = "cvznxibm";
1907   static const char v32_fnames[] = "cvznxiup";
1908   const char *fnames
1909     = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames;
1910 
1911   unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15));
1912   int i;
1913 
1914   for (i = 0; i < 8; i++)
1915     if (flagbits & (1 << i))
1916       *cp++ = fnames[i];
1917 
1918   return cp;
1919 }
1920 
1921 /* Print out an insn with its operands, and update the info->insn_type
1922    fields.  The prefix_opcodep and the rest hold a prefix insn that is
1923    supposed to be output as an address mode.  */
1924 
1925 static void
print_with_operands(const struct cris_opcode * opcodep,unsigned int insn,unsigned char * buffer,bfd_vma addr,disassemble_info * info,const struct cris_opcode * prefix_opcodep,unsigned int prefix_insn,unsigned char * prefix_buffer,bfd_boolean with_reg_prefix)1926 print_with_operands (const struct cris_opcode *opcodep,
1927 		     unsigned int insn,
1928 		     unsigned char *buffer,
1929 		     bfd_vma addr,
1930 		     disassemble_info *info,
1931 		     /* If a prefix insn was before this insn (and is supposed
1932 			to be output as an address), here is a description of
1933 			it.  */
1934 		     const struct cris_opcode *prefix_opcodep,
1935 		     unsigned int prefix_insn,
1936 		     unsigned char *prefix_buffer,
1937 		     bfd_boolean with_reg_prefix)
1938 {
1939   /* Get a buffer of somewhat reasonable size where we store
1940      intermediate parts of the insn.  */
1941   char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2];
1942   char *tp = temp;
1943   static const char mode_char[] = "bwd?";
1944   const char *s;
1945   const char *cs;
1946   struct cris_disasm_data *disdata
1947     = (struct cris_disasm_data *) info->private_data;
1948 
1949   /* Print out the name first thing we do.  */
1950   (*info->fprintf_func) (info->stream, "%s", opcodep->name);
1951 
1952   cs = opcodep->args;
1953   s = cs;
1954 
1955   /* Ignore any prefix indicator.  */
1956   if (*s == 'p')
1957     s++;
1958 
1959   if (*s == 'm' || *s == 'M' || *s == 'z')
1960     {
1961       *tp++ = '.';
1962 
1963       /* Get the size-letter.  */
1964       *tp++ = *s == 'M'
1965 	? (insn & 0x8000 ? 'd'
1966 	   : insn & 0x4000 ? 'w' : 'b')
1967 	: mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)];
1968 
1969       /* Ignore the size and the space character that follows.  */
1970       s += 2;
1971     }
1972 
1973   /* Add a space if this isn't a long-branch, because for those will add
1974      the condition part of the name later.  */
1975   if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256))
1976     *tp++ = ' ';
1977 
1978   /* Fill in the insn-type if deducible from the name (and there's no
1979      better way).  */
1980   if (opcodep->name[0] == 'j')
1981     {
1982       if (CONST_STRNEQ (opcodep->name, "jsr"))
1983 	/* It's "jsr" or "jsrc".  */
1984 	info->insn_type = dis_jsr;
1985       else
1986 	/* Any other jump-type insn is considered a branch.  */
1987 	info->insn_type = dis_branch;
1988     }
1989 
1990   /* We might know some more fields right now.  */
1991   info->branch_delay_insns = opcodep->delayed;
1992 
1993   /* Handle operands.  */
1994   for (; *s; s++)
1995     {
1996     switch (*s)
1997       {
1998       case 'T':
1999 	tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix);
2000 	break;
2001 
2002       case 'A':
2003 	if (with_reg_prefix)
2004 	  *tp++ = REGISTER_PREFIX_CHAR;
2005 	*tp++ = 'a';
2006 	*tp++ = 'c';
2007 	*tp++ = 'r';
2008 	break;
2009 
2010       case '[':
2011       case ']':
2012       case ',':
2013 	*tp++ = *s;
2014 	break;
2015 
2016       case '!':
2017 	/* Ignore at this point; used at earlier stages to avoid
2018 	   recognition if there's a prefix at something that in other
2019 	   ways looks like a "pop".  */
2020 	break;
2021 
2022       case 'd':
2023 	/* Ignore.  This is an optional ".d " on the large one of
2024 	   relaxable insns.  */
2025 	break;
2026 
2027       case 'B':
2028 	/* This was the prefix that made this a "push".  We've already
2029 	   handled it by recognizing it, so signal that the prefix is
2030 	   handled by setting it to NULL.  */
2031 	prefix_opcodep = NULL;
2032 	break;
2033 
2034       case 'D':
2035       case 'r':
2036 	tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2037 	break;
2038 
2039       case 'R':
2040 	tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2041 	break;
2042 
2043       case 'n':
2044 	{
2045 	  /* Like N but pc-relative to the start of the insn.  */
2046 	  unsigned long number
2047 	    = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2048 	       + buffer[5] * 0x1000000 + addr);
2049 
2050 	  /* Finish off and output previous formatted bytes.  */
2051 	  *tp = 0;
2052 	  if (temp[0])
2053 	    (*info->fprintf_func) (info->stream, "%s", temp);
2054 	  tp = temp;
2055 
2056 	  (*info->print_address_func) ((bfd_vma) number, info);
2057 	}
2058 	break;
2059 
2060       case 'u':
2061 	{
2062 	  /* Like n but the offset is bits <3:0> in the instruction.  */
2063 	  unsigned long number = (buffer[0] & 0xf) * 2 + addr;
2064 
2065 	  /* Finish off and output previous formatted bytes.  */
2066 	  *tp = 0;
2067 	  if (temp[0])
2068 	    (*info->fprintf_func) (info->stream, "%s", temp);
2069 	  tp = temp;
2070 
2071 	  (*info->print_address_func) ((bfd_vma) number, info);
2072 	}
2073 	break;
2074 
2075       case 'N':
2076       case 'y':
2077       case 'Y':
2078       case 'S':
2079       case 's':
2080 	/* Any "normal" memory operand.  */
2081 	if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL)
2082 	  {
2083 	    /* We're looking at [pc+], i.e. we need to output an immediate
2084 	       number, where the size can depend on different things.  */
2085 	    long number;
2086 	    int signedp
2087 	      = ((*cs == 'z' && (insn & 0x20))
2088 		 || opcodep->match == BDAP_QUICK_OPCODE);
2089 	    int nbytes;
2090 
2091 	    if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2092 	      nbytes = 4;
2093 	    else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2094 	      {
2095 		const struct cris_spec_reg *sregp
2096 		  = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2097 
2098 		/* A NULL return should have been as a non-match earlier,
2099 		   so catch it as an internal error in the error-case
2100 		   below.  */
2101 		if (sregp == NULL)
2102 		  /* Whatever non-valid size.  */
2103 		  nbytes = 42;
2104 		else
2105 		  /* PC is always incremented by a multiple of two.
2106 		     For CRISv32, immediates are always 4 bytes for
2107 		     special registers.  */
2108 		  nbytes = disdata->distype == cris_dis_v32
2109 		    ? 4 : (sregp->reg_size + 1) & ~1;
2110 	      }
2111 	    else
2112 	      {
2113 		int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3));
2114 
2115 		if (mode_size == 1)
2116 		  nbytes = 2;
2117 		else
2118 		  nbytes = mode_size;
2119 	      }
2120 
2121 	    switch (nbytes)
2122 	      {
2123 	      case 1:
2124 		number = buffer[2];
2125 		if (signedp && number > 127)
2126 		  number -= 256;
2127 		break;
2128 
2129 	      case 2:
2130 		number = buffer[2] + buffer[3] * 256;
2131 		if (signedp && number > 32767)
2132 		  number -= 65536;
2133 		break;
2134 
2135 	      case 4:
2136 		number
2137 		  = buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2138 		  + buffer[5] * 0x1000000;
2139 		break;
2140 
2141 	      default:
2142 		strcpy (tp, "bug");
2143 		tp += 3;
2144 		number = 42;
2145 	      }
2146 
2147 	    if ((*cs == 'z' && (insn & 0x20))
2148 		|| (opcodep->match == BDAP_QUICK_OPCODE
2149 		    && (nbytes <= 2 || buffer[1 + nbytes] == 0)))
2150 	      tp = format_dec (number, tp, signedp);
2151 	    else
2152 	      {
2153 		unsigned int highbyte = (number >> 24) & 0xff;
2154 
2155 		/* Either output this as an address or as a number.  If it's
2156 		   a dword with the same high-byte as the address of the
2157 		   insn, assume it's an address, and also if it's a non-zero
2158 		   non-0xff high-byte.  If this is a jsr or a jump, then
2159 		   it's definitely an address.  */
2160 		if (nbytes == 4
2161 		    && (highbyte == ((addr >> 24) & 0xff)
2162 			|| (highbyte != 0 && highbyte != 0xff)
2163 			|| info->insn_type == dis_branch
2164 			|| info->insn_type == dis_jsr))
2165 		  {
2166 		    /* Finish off and output previous formatted bytes.  */
2167 		    *tp = 0;
2168 		    tp = temp;
2169 		    if (temp[0])
2170 		      (*info->fprintf_func) (info->stream, "%s", temp);
2171 
2172 		    (*info->print_address_func) ((bfd_vma) number, info);
2173 
2174 		    info->target = number;
2175 		  }
2176 		else
2177 		  tp = format_hex (number, tp, disdata);
2178 	      }
2179 	  }
2180 	else
2181 	  {
2182 	    /* Not an immediate number.  Then this is a (possibly
2183 	       prefixed) memory operand.  */
2184 	    if (info->insn_type != dis_nonbranch)
2185 	      {
2186 		int mode_size
2187 		  = 1 << ((insn >> 4)
2188 			  & (opcodep->args[0] == 'z' ? 1 : 3));
2189 		int size;
2190 		info->insn_type = dis_dref;
2191 		info->flags |= CRIS_DIS_FLAG_MEMREF;
2192 
2193 		if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2194 		  size = 4;
2195 		else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2196 		  {
2197 		    const struct cris_spec_reg *sregp
2198 		      = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2199 
2200 		    /* FIXME: Improve error handling; should have been caught
2201 		       earlier.  */
2202 		    if (sregp == NULL)
2203 		      size = 4;
2204 		    else
2205 		      size = sregp->reg_size;
2206 		  }
2207 		else
2208 		  size = mode_size;
2209 
2210 		info->data_size = size;
2211 	      }
2212 
2213 	    *tp++ = '[';
2214 
2215 	    if (prefix_opcodep
2216 		/* We don't match dip with a postincremented field
2217 		   as a side-effect address mode.  */
2218 		&& ((insn & 0x400) == 0
2219 		    || prefix_opcodep->match != DIP_OPCODE))
2220 	      {
2221 		if (insn & 0x400)
2222 		  {
2223 		    tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2224 		    *tp++ = '=';
2225 		  }
2226 
2227 
2228 		/* We mainly ignore the prefix format string when the
2229 		   address-mode syntax is output.  */
2230 		switch (prefix_opcodep->match)
2231 		  {
2232 		  case DIP_OPCODE:
2233 		    /* It's [r], [r+] or [pc+].  */
2234 		    if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2235 		      {
2236 			/* It's [pc+].  This cannot possibly be anything
2237 			   but an address.  */
2238 			unsigned long number
2239 			  = prefix_buffer[2] + prefix_buffer[3] * 256
2240 			  + prefix_buffer[4] * 65536
2241 			  + prefix_buffer[5] * 0x1000000;
2242 
2243 			info->target = (bfd_vma) number;
2244 
2245 			/* Finish off and output previous formatted
2246 			   data.  */
2247 			*tp = 0;
2248 			tp = temp;
2249 			if (temp[0])
2250 			  (*info->fprintf_func) (info->stream, "%s", temp);
2251 
2252 			(*info->print_address_func) ((bfd_vma) number, info);
2253 		      }
2254 		    else
2255 		      {
2256 			/* For a memref in an address, we use target2.
2257 			   In this case, target is zero.  */
2258 			info->flags
2259 			  |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2260 			      | CRIS_DIS_FLAG_MEM_TARGET2_MEM);
2261 
2262 			info->target2 = prefix_insn & 15;
2263 
2264 			*tp++ = '[';
2265 			tp = format_reg (disdata, prefix_insn & 15, tp,
2266 					 with_reg_prefix);
2267 			if (prefix_insn & 0x400)
2268 			  *tp++ = '+';
2269 			*tp++ = ']';
2270 		      }
2271 		    break;
2272 
2273 		  case BDAP_QUICK_OPCODE:
2274 		    {
2275 		      int number;
2276 
2277 		      number = prefix_buffer[0];
2278 		      if (number > 127)
2279 			number -= 256;
2280 
2281 		      /* Output "reg+num" or, if num < 0, "reg-num".  */
2282 		      tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2283 				       with_reg_prefix);
2284 		      if (number >= 0)
2285 			*tp++ = '+';
2286 		      tp = format_dec (number, tp, 1);
2287 
2288 		      info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2289 		      info->target = (prefix_insn >> 12) & 15;
2290 		      info->target2 = (bfd_vma) number;
2291 		      break;
2292 		    }
2293 
2294 		  case BIAP_OPCODE:
2295 		    /* Output "r+R.m".  */
2296 		    tp = format_reg (disdata, prefix_insn & 15, tp,
2297 				     with_reg_prefix);
2298 		    *tp++ = '+';
2299 		    tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2300 				     with_reg_prefix);
2301 		    *tp++ = '.';
2302 		    *tp++ = mode_char[(prefix_insn >> 4) & 3];
2303 
2304 		    info->flags
2305 		      |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2306 			  | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2307 
2308 			  | ((prefix_insn & 0x8000)
2309 			     ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4
2310 			     : ((prefix_insn & 0x8000)
2311 				? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0)));
2312 
2313 		    /* Is it the casejump?  It's a "adds.w [pc+r%d.w],pc".  */
2314 		    if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f)
2315 		      /* Then start interpreting data as offsets.  */
2316 		      case_offset_counter = no_of_case_offsets;
2317 		    break;
2318 
2319 		  case BDAP_INDIR_OPCODE:
2320 		    /* Output "r+s.m", or, if "s" is [pc+], "r+s" or
2321 		       "r-s".  */
2322 		    tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2323 				     with_reg_prefix);
2324 
2325 		    if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2326 		      {
2327 			long number;
2328 			unsigned int nbytes;
2329 
2330 			/* It's a value.  Get its size.  */
2331 			int mode_size = 1 << ((prefix_insn >> 4) & 3);
2332 
2333 			if (mode_size == 1)
2334 			  nbytes = 2;
2335 			else
2336 			  nbytes = mode_size;
2337 
2338 			switch (nbytes)
2339 			  {
2340 			  case 1:
2341 			    number = prefix_buffer[2];
2342 			    if (number > 127)
2343 			      number -= 256;
2344 			    break;
2345 
2346 			  case 2:
2347 			    number = prefix_buffer[2] + prefix_buffer[3] * 256;
2348 			    if (number > 32767)
2349 			      number -= 65536;
2350 			    break;
2351 
2352 			  case 4:
2353 			    number
2354 			      = prefix_buffer[2] + prefix_buffer[3] * 256
2355 			      + prefix_buffer[4] * 65536
2356 			      + prefix_buffer[5] * 0x1000000;
2357 			    break;
2358 
2359 			  default:
2360 			    strcpy (tp, "bug");
2361 			    tp += 3;
2362 			    number = 42;
2363 			  }
2364 
2365 			info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2366 			info->target2 = (bfd_vma) number;
2367 
2368 			/* If the size is dword, then assume it's an
2369 			   address.  */
2370 			if (nbytes == 4)
2371 			  {
2372 			    /* Finish off and output previous formatted
2373 			       bytes.  */
2374 			    *tp++ = '+';
2375 			    *tp = 0;
2376 			    tp = temp;
2377 			    (*info->fprintf_func) (info->stream, "%s", temp);
2378 
2379 			    (*info->print_address_func) ((bfd_vma) number, info);
2380 			  }
2381 			else
2382 			  {
2383 			    if (number >= 0)
2384 			      *tp++ = '+';
2385 			    tp = format_dec (number, tp, 1);
2386 			  }
2387 		      }
2388 		    else
2389 		      {
2390 			/* Output "r+[R].m" or "r+[R+].m".  */
2391 			*tp++ = '+';
2392 			*tp++ = '[';
2393 			tp = format_reg (disdata, prefix_insn & 15, tp,
2394 					 with_reg_prefix);
2395 			if (prefix_insn & 0x400)
2396 			  *tp++ = '+';
2397 			*tp++ = ']';
2398 			*tp++ = '.';
2399 			*tp++ = mode_char[(prefix_insn >> 4) & 3];
2400 
2401 			info->flags
2402 			  |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2403 			      | CRIS_DIS_FLAG_MEM_TARGET2_MEM
2404 			      | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2405 
2406 			      | (((prefix_insn >> 4) == 2)
2407 				 ? 0
2408 				 : (((prefix_insn >> 4) & 3) == 1
2409 				    ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD
2410 				    : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE)));
2411 		      }
2412 		    break;
2413 
2414 		  default:
2415 		    (*info->fprintf_func) (info->stream, "?prefix-bug");
2416 		  }
2417 
2418 		/* To mark that the prefix is used, reset it.  */
2419 		prefix_opcodep = NULL;
2420 	      }
2421 	    else
2422 	      {
2423 		tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2424 
2425 		info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2426 		info->target = insn & 15;
2427 
2428 		if (insn & 0x400)
2429 		  *tp++ = '+';
2430 	      }
2431 	    *tp++ = ']';
2432 	  }
2433 	break;
2434 
2435       case 'x':
2436 	tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2437 	*tp++ = '.';
2438 	*tp++ = mode_char[(insn >> 4) & 3];
2439 	break;
2440 
2441       case 'I':
2442 	tp = format_dec (insn & 63, tp, 0);
2443 	break;
2444 
2445       case 'b':
2446 	{
2447 	  int where = buffer[2] + buffer[3] * 256;
2448 
2449 	  if (where > 32767)
2450 	    where -= 65536;
2451 
2452 	  where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4);
2453 
2454 	  if (insn == BA_PC_INCR_OPCODE)
2455 	    info->insn_type = dis_branch;
2456 	  else
2457 	    info->insn_type = dis_condbranch;
2458 
2459 	  info->target = (bfd_vma) where;
2460 
2461 	  *tp = 0;
2462 	  tp = temp;
2463 	  (*info->fprintf_func) (info->stream, "%s%s ",
2464 				 temp, cris_cc_strings[insn >> 12]);
2465 
2466 	  (*info->print_address_func) ((bfd_vma) where, info);
2467 	}
2468       break;
2469 
2470     case 'c':
2471       tp = format_dec (insn & 31, tp, 0);
2472       break;
2473 
2474     case 'C':
2475       tp = format_dec (insn & 15, tp, 0);
2476       break;
2477 
2478     case 'o':
2479       {
2480 	long offset = insn & 0xfe;
2481 	bfd_vma target;
2482 
2483 	if (insn & 1)
2484 	  offset |= ~0xff;
2485 
2486 	if (opcodep->match == BA_QUICK_OPCODE)
2487 	  info->insn_type = dis_branch;
2488 	else
2489 	  info->insn_type = dis_condbranch;
2490 
2491 	target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset;
2492 	info->target = target;
2493 	*tp = 0;
2494 	tp = temp;
2495 	(*info->fprintf_func) (info->stream, "%s", temp);
2496 	(*info->print_address_func) (target, info);
2497       }
2498       break;
2499 
2500     case 'Q':
2501     case 'O':
2502       {
2503 	long number = buffer[0];
2504 
2505 	if (number > 127)
2506 	  number = number - 256;
2507 
2508 	tp = format_dec (number, tp, 1);
2509 	*tp++ = ',';
2510 	tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2511       }
2512       break;
2513 
2514     case 'f':
2515       tp = print_flags (disdata, insn, tp);
2516       break;
2517 
2518     case 'i':
2519       tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1);
2520       break;
2521 
2522     case 'P':
2523       {
2524 	const struct cris_spec_reg *sregp
2525 	  = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2526 
2527 	if (sregp->name == NULL)
2528 	  /* Should have been caught as a non-match eariler.  */
2529 	  *tp++ = '?';
2530 	else
2531 	  {
2532 	    if (with_reg_prefix)
2533 	      *tp++ = REGISTER_PREFIX_CHAR;
2534 	    strcpy (tp, sregp->name);
2535 	    tp += strlen (tp);
2536 	  }
2537       }
2538       break;
2539 
2540     default:
2541       strcpy (tp, "???");
2542       tp += 3;
2543     }
2544   }
2545 
2546   *tp = 0;
2547 
2548   if (prefix_opcodep)
2549     (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")",
2550 			   prefix_opcodep->name, prefix_opcodep->args);
2551 
2552   (*info->fprintf_func) (info->stream, "%s", temp);
2553 
2554   /* Get info for matching case-tables, if we don't have any active.
2555      We assume that the last constant seen is used; either in the insn
2556      itself or in a "move.d const,rN, sub.d rN,rM"-like sequence.  */
2557   if (TRACE_CASE && case_offset_counter == 0)
2558     {
2559       if (CONST_STRNEQ (opcodep->name, "sub"))
2560 	case_offset = last_immediate;
2561 
2562       /* It could also be an "add", if there are negative case-values.  */
2563       else if (CONST_STRNEQ (opcodep->name, "add"))
2564 	/* The first case is the negated operand to the add.  */
2565 	case_offset = -last_immediate;
2566 
2567       /* A bound insn will tell us the number of cases.  */
2568       else if (CONST_STRNEQ (opcodep->name, "bound"))
2569 	no_of_case_offsets = last_immediate + 1;
2570 
2571       /* A jump or jsr or branch breaks the chain of insns for a
2572 	 case-table, so assume default first-case again.  */
2573       else if (info->insn_type == dis_jsr
2574 	       || info->insn_type == dis_branch
2575 	       || info->insn_type == dis_condbranch)
2576 	case_offset = 0;
2577     }
2578 }
2579 
2580 
2581 /* Print the CRIS instruction at address memaddr on stream.  Returns
2582    length of the instruction, in bytes.  Prefix register names with `$' if
2583    WITH_REG_PREFIX.  */
2584 
2585 static int
print_insn_cris_generic(bfd_vma memaddr,disassemble_info * info,bfd_boolean with_reg_prefix)2586 print_insn_cris_generic (bfd_vma memaddr,
2587 			 disassemble_info *info,
2588 			 bfd_boolean with_reg_prefix)
2589 {
2590   int nbytes;
2591   unsigned int insn;
2592   const struct cris_opcode *matchedp;
2593   int advance = 0;
2594   struct cris_disasm_data *disdata
2595     = (struct cris_disasm_data *) info->private_data;
2596 
2597   /* No instruction will be disassembled as longer than this number of
2598      bytes; stacked prefixes will not be expanded.  */
2599   unsigned char buffer[MAX_BYTES_PER_CRIS_INSN];
2600   unsigned char *bufp;
2601   int status = 0;
2602   bfd_vma addr;
2603 
2604   /* There will be an "out of range" error after the last instruction.
2605      Reading pairs of bytes in decreasing number, we hope that we will get
2606      at least the amount that we will consume.
2607 
2608      If we can't get any data, or we do not get enough data, we print
2609      the error message.  */
2610 
2611   nbytes = info->buffer_length;
2612   if (nbytes > MAX_BYTES_PER_CRIS_INSN)
2613 	  nbytes = MAX_BYTES_PER_CRIS_INSN;
2614   status = (*info->read_memory_func) (memaddr, buffer, nbytes, info);
2615 
2616   /* If we did not get all we asked for, then clear the rest.
2617      Hopefully this makes a reproducible result in case of errors.  */
2618   if (nbytes != MAX_BYTES_PER_CRIS_INSN)
2619     memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes);
2620 
2621   addr = memaddr;
2622   bufp = buffer;
2623 
2624   /* Set some defaults for the insn info.  */
2625   info->insn_info_valid = 1;
2626   info->branch_delay_insns = 0;
2627   info->data_size = 0;
2628   info->insn_type = dis_nonbranch;
2629   info->flags = 0;
2630   info->target = 0;
2631   info->target2 = 0;
2632 
2633   /* If we got any data, disassemble it.  */
2634   if (nbytes != 0)
2635     {
2636       matchedp = NULL;
2637 
2638       insn = bufp[0] + bufp[1] * 256;
2639 
2640       /* If we're in a case-table, don't disassemble the offsets.  */
2641       if (TRACE_CASE && case_offset_counter != 0)
2642 	{
2643 	  info->insn_type = dis_noninsn;
2644 	  advance += 2;
2645 
2646 	  /* If to print data as offsets, then shortcut here.  */
2647 	  (*info->fprintf_func) (info->stream, "case %ld%s: -> ",
2648 				 case_offset + no_of_case_offsets
2649 				 - case_offset_counter,
2650 				 case_offset_counter == 1 ? "/default" :
2651 				 "");
2652 
2653 	  (*info->print_address_func) ((bfd_vma)
2654 				       ((short) (insn)
2655 					+ (long) (addr
2656 						  - (no_of_case_offsets
2657 						     - case_offset_counter)
2658 						  * 2)), info);
2659 	  case_offset_counter--;
2660 
2661 	  /* The default case start (without a "sub" or "add") must be
2662 	     zero.  */
2663 	  if (case_offset_counter == 0)
2664 	    case_offset = 0;
2665 	}
2666       else if (insn == 0)
2667 	{
2668 	  /* We're often called to disassemble zeroes.  While this is a
2669 	     valid "bcc .+2" insn, it is also useless enough and enough
2670 	     of a nuiscance that we will just output "bcc .+2" for it
2671 	     and signal it as a noninsn.  */
2672 	  (*info->fprintf_func) (info->stream,
2673 				 disdata->distype == cris_dis_v32
2674 				 ? "bcc ." : "bcc .+2");
2675 	  info->insn_type = dis_noninsn;
2676 	  advance += 2;
2677 	}
2678       else
2679 	{
2680 	  const struct cris_opcode *prefix_opcodep = NULL;
2681 	  unsigned char *prefix_buffer = bufp;
2682 	  unsigned int prefix_insn = insn;
2683 	  int prefix_size = 0;
2684 
2685 	  matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata);
2686 
2687 	  /* Check if we're supposed to write out prefixes as address
2688 	     modes and if this was a prefix.  */
2689 	  if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p')
2690 	    {
2691 	      /* If it's a prefix, put it into the prefix vars and get the
2692 		 main insn.  */
2693 	      prefix_size = bytes_to_skip (prefix_insn, matchedp,
2694 					   disdata->distype, NULL);
2695 	      prefix_opcodep = matchedp;
2696 
2697 	      insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256;
2698 	      matchedp = get_opcode_entry (insn, prefix_insn, disdata);
2699 
2700 	      if (matchedp != NULL)
2701 		{
2702 		  addr += prefix_size;
2703 		  bufp += prefix_size;
2704 		  advance += prefix_size;
2705 		}
2706 	      else
2707 		{
2708 		  /* The "main" insn wasn't valid, at least not when
2709 		     prefixed.  Put back things enough to output the
2710 		     prefix insn only, as a normal insn.  */
2711 		  matchedp = prefix_opcodep;
2712 		  insn = prefix_insn;
2713 		  prefix_opcodep = NULL;
2714 		}
2715 	    }
2716 
2717 	  if (matchedp == NULL)
2718 	    {
2719 	      (*info->fprintf_func) (info->stream, "??0x%x", insn);
2720 	      advance += 2;
2721 
2722 	      info->insn_type = dis_noninsn;
2723 	    }
2724 	  else
2725 	    {
2726 	      advance
2727 		+= bytes_to_skip (insn, matchedp, disdata->distype,
2728 				  prefix_opcodep);
2729 
2730 	      /* The info_type and assorted fields will be set according
2731 		 to the operands.   */
2732 	      print_with_operands (matchedp, insn, bufp, addr, info,
2733 				   prefix_opcodep, prefix_insn,
2734 				   prefix_buffer, with_reg_prefix);
2735 	    }
2736 	}
2737     }
2738   else
2739     info->insn_type = dis_noninsn;
2740 
2741   /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error
2742      status when reading that much, and the insn decoding indicated a
2743      length exceeding what we read, there is an error.  */
2744   if (status != 0 && (nbytes == 0 || advance > nbytes))
2745     {
2746       (*info->memory_error_func) (status, memaddr, info);
2747       return -1;
2748     }
2749 
2750   /* Max supported insn size with one folded prefix insn.  */
2751   info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN;
2752 
2753   /* I would like to set this to a fixed value larger than the actual
2754      number of bytes to print in order to avoid spaces between bytes,
2755      but objdump.c (2.9.1) does not like that, so we print 16-bit
2756      chunks, which is the next choice.  */
2757   info->bytes_per_chunk = 2;
2758 
2759   /* Printing bytes in order of increasing addresses makes sense,
2760      especially on a little-endian target.
2761      This is completely the opposite of what you think; setting this to
2762      BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N
2763      we want.  */
2764   info->display_endian = BFD_ENDIAN_BIG;
2765 
2766   return advance;
2767 }
2768 
2769 /* Disassemble, prefixing register names with `$'.  CRIS v0..v10.  */
2770 static int
print_insn_cris_with_register_prefix(bfd_vma vma,disassemble_info * info)2771 print_insn_cris_with_register_prefix (bfd_vma vma,
2772 				      disassemble_info *info)
2773 {
2774   if (info->private_data == NULL
2775       && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2776     return -1;
2777   return print_insn_cris_generic (vma, info, true);
2778 }
2779 /* Disassemble, prefixing register names with `$'.  CRIS v32.  */
2780 
2781 static int
print_insn_crisv32_with_register_prefix(bfd_vma vma,disassemble_info * info)2782 print_insn_crisv32_with_register_prefix (bfd_vma vma,
2783 					 disassemble_info *info)
2784 {
2785   if (info->private_data == NULL
2786       && !cris_parse_disassembler_options (info, cris_dis_v32))
2787     return -1;
2788   return print_insn_cris_generic (vma, info, true);
2789 }
2790 
2791 #if 0
2792 /* Disassemble, prefixing register names with `$'.
2793    Common v10 and v32 subset.  */
2794 
2795 static int
2796 print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
2797 					     disassemble_info *info)
2798 {
2799   if (info->private_data == NULL
2800       && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2801     return -1;
2802   return print_insn_cris_generic (vma, info, true);
2803 }
2804 
2805 /* Disassemble, no prefixes on register names.  CRIS v0..v10.  */
2806 
2807 static int
2808 print_insn_cris_without_register_prefix (bfd_vma vma,
2809 					 disassemble_info *info)
2810 {
2811   if (info->private_data == NULL
2812       && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2813     return -1;
2814   return print_insn_cris_generic (vma, info, false);
2815 }
2816 
2817 /* Disassemble, no prefixes on register names.  CRIS v32.  */
2818 
2819 static int
2820 print_insn_crisv32_without_register_prefix (bfd_vma vma,
2821 					    disassemble_info *info)
2822 {
2823   if (info->private_data == NULL
2824       && !cris_parse_disassembler_options (info, cris_dis_v32))
2825     return -1;
2826   return print_insn_cris_generic (vma, info, false);
2827 }
2828 
2829 /* Disassemble, no prefixes on register names.
2830    Common v10 and v32 subset.  */
2831 
2832 static int
2833 print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
2834 						disassemble_info *info)
2835 {
2836   if (info->private_data == NULL
2837       && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2838     return -1;
2839   return print_insn_cris_generic (vma, info, false);
2840 }
2841 #endif
2842 
2843 int
print_insn_crisv10(bfd_vma vma,disassemble_info * info)2844 print_insn_crisv10 (bfd_vma vma,
2845 		    disassemble_info *info)
2846 {
2847   return print_insn_cris_with_register_prefix(vma, info);
2848 }
2849 
2850 int
print_insn_crisv32(bfd_vma vma,disassemble_info * info)2851 print_insn_crisv32 (bfd_vma vma,
2852 		    disassemble_info *info)
2853 {
2854   return print_insn_crisv32_with_register_prefix(vma, info);
2855 }
2856 
2857 /* Return a disassembler-function that prints registers with a `$' prefix,
2858    or one that prints registers without a prefix.
2859    FIXME: We should improve the solution to avoid the multitude of
2860    functions seen above.  */
2861 #if 0
2862 disassembler_ftype
2863 cris_get_disassembler (bfd *abfd)
2864 {
2865   /* If there's no bfd in sight, we return what is valid as input in all
2866      contexts if fed back to the assembler: disassembly *with* register
2867      prefix.  Unfortunately this will be totally wrong for v32.  */
2868   if (abfd == NULL)
2869     return print_insn_cris_with_register_prefix;
2870 
2871   if (bfd_get_symbol_leading_char (abfd) == 0)
2872     {
2873       if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2874 	return print_insn_crisv32_with_register_prefix;
2875       if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2876 	return print_insn_crisv10_v32_with_register_prefix;
2877 
2878       /* We default to v10.  This may be specifically specified in the
2879 	 bfd mach, but is also the default setting.  */
2880       return print_insn_cris_with_register_prefix;
2881     }
2882 
2883   if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2884     return print_insn_crisv32_without_register_prefix;
2885   if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2886     return print_insn_crisv10_v32_without_register_prefix;
2887   return print_insn_cris_without_register_prefix;
2888 }
2889 #endif
2890 /* Local variables:
2891    eval: (c-set-style "gnu")
2892    indent-tabs-mode: t
2893    End:  */
2894