xref: /illumos-kvm-cmd/alpha-dis.c (revision 68396ea9)
1 /* alpha-dis.c -- Disassemble Alpha AXP instructions
2    Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3    Contributed by Richard Henderson <rth@tamu.edu>,
4    patterned after the PPC opcode handling written by Ian Lance Taylor.
5 
6 This file is part of GDB, GAS, and the GNU binutils.
7 
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12 
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
16 the GNU General Public License for more details.
17 
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING.  If not, see
20 <http://www.gnu.org/licenses/>. */
21 
22 #include <stdio.h>
23 #include "dis-asm.h"
24 
25 /* MAX is redefined below, so remove any previous definition. */
26 #undef MAX
27 
28 /* The opcode table is an array of struct alpha_opcode.  */
29 
30 struct alpha_opcode
31 {
32   /* The opcode name.  */
33   const char *name;
34 
35   /* The opcode itself.  Those bits which will be filled in with
36      operands are zeroes.  */
37   unsigned opcode;
38 
39   /* The opcode mask.  This is used by the disassembler.  This is a
40      mask containing ones indicating those bits which must match the
41      opcode field, and zeroes indicating those bits which need not
42      match (and are presumably filled in by operands).  */
43   unsigned mask;
44 
45   /* One bit flags for the opcode.  These are primarily used to
46      indicate specific processors and environments support the
47      instructions.  The defined values are listed below. */
48   unsigned flags;
49 
50   /* An array of operand codes.  Each code is an index into the
51      operand table.  They appear in the order which the operands must
52      appear in assembly code, and are terminated by a zero.  */
53   unsigned char operands[4];
54 };
55 
56 /* The table itself is sorted by major opcode number, and is otherwise
57    in the order in which the disassembler should consider
58    instructions.  */
59 extern const struct alpha_opcode alpha_opcodes[];
60 extern const unsigned alpha_num_opcodes;
61 
62 /* Values defined for the flags field of a struct alpha_opcode.  */
63 
64 /* CPU Availability */
65 #define AXP_OPCODE_BASE  0x0001  /* Base architecture -- all cpus.  */
66 #define AXP_OPCODE_EV4   0x0002  /* EV4 specific PALcode insns.  */
67 #define AXP_OPCODE_EV5   0x0004  /* EV5 specific PALcode insns.  */
68 #define AXP_OPCODE_EV6   0x0008  /* EV6 specific PALcode insns.  */
69 #define AXP_OPCODE_BWX   0x0100  /* Byte/word extension (amask bit 0).  */
70 #define AXP_OPCODE_CIX   0x0200  /* "Count" extension (amask bit 1).  */
71 #define AXP_OPCODE_MAX   0x0400  /* Multimedia extension (amask bit 8).  */
72 
73 #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
74 
75 /* A macro to extract the major opcode from an instruction.  */
76 #define AXP_OP(i)	(((i) >> 26) & 0x3F)
77 
78 /* The total number of major opcodes. */
79 #define AXP_NOPS	0x40
80 
81 
82 /* The operands table is an array of struct alpha_operand.  */
83 
84 struct alpha_operand
85 {
86   /* The number of bits in the operand.  */
87   unsigned int bits : 5;
88 
89   /* How far the operand is left shifted in the instruction.  */
90   unsigned int shift : 5;
91 
92   /* The default relocation type for this operand.  */
93   signed int default_reloc : 16;
94 
95   /* One bit syntax flags.  */
96   unsigned int flags : 16;
97 
98   /* Insertion function.  This is used by the assembler.  To insert an
99      operand value into an instruction, check this field.
100 
101      If it is NULL, execute
102          i |= (op & ((1 << o->bits) - 1)) << o->shift;
103      (i is the instruction which we are filling in, o is a pointer to
104      this structure, and op is the opcode value; this assumes twos
105      complement arithmetic).
106 
107      If this field is not NULL, then simply call it with the
108      instruction and the operand value.  It will return the new value
109      of the instruction.  If the ERRMSG argument is not NULL, then if
110      the operand value is illegal, *ERRMSG will be set to a warning
111      string (the operand will be inserted in any case).  If the
112      operand value is legal, *ERRMSG will be unchanged (most operands
113      can accept any value).  */
114   unsigned (*insert) (unsigned instruction, int op,
115                       const char **errmsg);
116 
117   /* Extraction function.  This is used by the disassembler.  To
118      extract this operand type from an instruction, check this field.
119 
120      If it is NULL, compute
121          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
122 	 if ((o->flags & AXP_OPERAND_SIGNED) != 0
123 	     && (op & (1 << (o->bits - 1))) != 0)
124 	   op -= 1 << o->bits;
125      (i is the instruction, o is a pointer to this structure, and op
126      is the result; this assumes twos complement arithmetic).
127 
128      If this field is not NULL, then simply call it with the
129      instruction value.  It will return the value of the operand.  If
130      the INVALID argument is not NULL, *INVALID will be set to
131      non-zero if this operand type can not actually be extracted from
132      this operand (i.e., the instruction does not match).  If the
133      operand is valid, *INVALID will not be changed.  */
134   int (*extract) (unsigned instruction, int *invalid);
135 };
136 
137 /* Elements in the table are retrieved by indexing with values from
138    the operands field of the alpha_opcodes table.  */
139 
140 extern const struct alpha_operand alpha_operands[];
141 extern const unsigned alpha_num_operands;
142 
143 /* Values defined for the flags field of a struct alpha_operand.  */
144 
145 /* Mask for selecting the type for typecheck purposes */
146 #define AXP_OPERAND_TYPECHECK_MASK					\
147   (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR |		\
148    AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | 	\
149    AXP_OPERAND_UNSIGNED)
150 
151 /* This operand does not actually exist in the assembler input.  This
152    is used to support extended mnemonics, for which two operands fields
153    are identical.  The assembler should call the insert function with
154    any op value.  The disassembler should call the extract function,
155    ignore the return value, and check the value placed in the invalid
156    argument.  */
157 #define AXP_OPERAND_FAKE	01
158 
159 /* The operand should be wrapped in parentheses rather than separated
160    from the previous by a comma.  This is used for the load and store
161    instructions which want their operands to look like "Ra,disp(Rb)".  */
162 #define AXP_OPERAND_PARENS	02
163 
164 /* Used in combination with PARENS, this suppresses the suppression of
165    the comma.  This is used for "jmp Ra,(Rb),hint".  */
166 #define AXP_OPERAND_COMMA	04
167 
168 /* This operand names an integer register.  */
169 #define AXP_OPERAND_IR		010
170 
171 /* This operand names a floating point register.  */
172 #define AXP_OPERAND_FPR		020
173 
174 /* This operand is a relative branch displacement.  The disassembler
175    prints these symbolically if possible.  */
176 #define AXP_OPERAND_RELATIVE	040
177 
178 /* This operand takes signed values.  */
179 #define AXP_OPERAND_SIGNED	0100
180 
181 /* This operand takes unsigned values.  This exists primarily so that
182    a flags value of 0 can be treated as end-of-arguments.  */
183 #define AXP_OPERAND_UNSIGNED	0200
184 
185 /* Suppress overflow detection on this field.  This is used for hints. */
186 #define AXP_OPERAND_NOOVERFLOW	0400
187 
188 /* Mask for optional argument default value.  */
189 #define AXP_OPERAND_OPTIONAL_MASK 07000
190 
191 /* This operand defaults to zero.  This is used for jump hints.  */
192 #define AXP_OPERAND_DEFAULT_ZERO 01000
193 
194 /* This operand should default to the first (real) operand and is used
195    in conjunction with AXP_OPERAND_OPTIONAL.  This allows
196    "and $0,3,$0" to be written as "and $0,3", etc.  I don't like
197    it, but it's what DEC does.  */
198 #define AXP_OPERAND_DEFAULT_FIRST 02000
199 
200 /* Similarly, this operand should default to the second (real) operand.
201    This allows "negl $0" instead of "negl $0,$0".  */
202 #define AXP_OPERAND_DEFAULT_SECOND 04000
203 
204 
205 /* Register common names */
206 
207 #define AXP_REG_V0	0
208 #define AXP_REG_T0	1
209 #define AXP_REG_T1	2
210 #define AXP_REG_T2	3
211 #define AXP_REG_T3	4
212 #define AXP_REG_T4	5
213 #define AXP_REG_T5	6
214 #define AXP_REG_T6	7
215 #define AXP_REG_T7	8
216 #define AXP_REG_S0	9
217 #define AXP_REG_S1	10
218 #define AXP_REG_S2	11
219 #define AXP_REG_S3	12
220 #define AXP_REG_S4	13
221 #define AXP_REG_S5	14
222 #define AXP_REG_FP	15
223 #define AXP_REG_A0	16
224 #define AXP_REG_A1	17
225 #define AXP_REG_A2	18
226 #define AXP_REG_A3	19
227 #define AXP_REG_A4	20
228 #define AXP_REG_A5	21
229 #define AXP_REG_T8	22
230 #define AXP_REG_T9	23
231 #define AXP_REG_T10	24
232 #define AXP_REG_T11	25
233 #define AXP_REG_RA	26
234 #define AXP_REG_PV	27
235 #define AXP_REG_T12	27
236 #define AXP_REG_AT	28
237 #define AXP_REG_GP	29
238 #define AXP_REG_SP	30
239 #define AXP_REG_ZERO	31
240 
241 #define bfd_mach_alpha_ev4  0x10
242 #define bfd_mach_alpha_ev5  0x20
243 #define bfd_mach_alpha_ev6  0x30
244 
245 enum bfd_reloc_code_real {
246     BFD_RELOC_23_PCREL_S2,
247     BFD_RELOC_ALPHA_HINT
248 };
249 
250 /* This file holds the Alpha AXP opcode table.  The opcode table includes
251    almost all of the extended instruction mnemonics.  This permits the
252    disassembler to use them, and simplifies the assembler logic, at the
253    cost of increasing the table size.  The table is strictly constant
254    data, so the compiler should be able to put it in the text segment.
255 
256    This file also holds the operand table.  All knowledge about inserting
257    and extracting operands from instructions is kept in this file.
258 
259    The information for the base instruction set was compiled from the
260    _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
261    version 2.
262 
263    The information for the post-ev5 architecture extensions BWX, CIX and
264    MAX came from version 3 of this same document, which is also available
265    on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
266    /literature/alphahb2.pdf
267 
268    The information for the EV4 PALcode instructions was compiled from
269    _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
270    Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
271    revision dated June 1994.
272 
273    The information for the EV5 PALcode instructions was compiled from
274    _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
275    Order Number EC-QAEQB-TE, preliminary revision dated April 1995.  */
276 
277 /* Local insertion and extraction functions */
278 
279 static unsigned insert_rba (unsigned, int, const char **);
280 static unsigned insert_rca (unsigned, int, const char **);
281 static unsigned insert_za (unsigned, int, const char **);
282 static unsigned insert_zb (unsigned, int, const char **);
283 static unsigned insert_zc (unsigned, int, const char **);
284 static unsigned insert_bdisp (unsigned, int, const char **);
285 static unsigned insert_jhint (unsigned, int, const char **);
286 static unsigned insert_ev6hwjhint (unsigned, int, const char **);
287 
288 static int extract_rba (unsigned, int *);
289 static int extract_rca (unsigned, int *);
290 static int extract_za (unsigned, int *);
291 static int extract_zb (unsigned, int *);
292 static int extract_zc (unsigned, int *);
293 static int extract_bdisp (unsigned, int *);
294 static int extract_jhint (unsigned, int *);
295 static int extract_ev6hwjhint (unsigned, int *);
296 
297 
298 /* The operands table  */
299 
300 const struct alpha_operand alpha_operands[] =
301 {
302   /* The fields are bits, shift, insert, extract, flags */
303   /* The zero index is used to indicate end-of-list */
304 #define UNUSED		0
305   { 0, 0, 0, 0, 0, 0 },
306 
307   /* The plain integer register fields */
308 #define RA		(UNUSED + 1)
309   { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
310 #define RB		(RA + 1)
311   { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
312 #define RC		(RB + 1)
313   { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
314 
315   /* The plain fp register fields */
316 #define FA		(RC + 1)
317   { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
318 #define FB		(FA + 1)
319   { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
320 #define FC		(FB + 1)
321   { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
322 
323   /* The integer registers when they are ZERO */
324 #define ZA		(FC + 1)
325   { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
326 #define ZB		(ZA + 1)
327   { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
328 #define ZC		(ZB + 1)
329   { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
330 
331   /* The RB field when it needs parentheses */
332 #define PRB		(ZC + 1)
333   { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
334 
335   /* The RB field when it needs parentheses _and_ a preceding comma */
336 #define CPRB		(PRB + 1)
337   { 5, 16, 0,
338     AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
339 
340   /* The RB field when it must be the same as the RA field */
341 #define RBA		(CPRB + 1)
342   { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
343 
344   /* The RC field when it must be the same as the RB field */
345 #define RCA		(RBA + 1)
346   { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
347 
348   /* The RC field when it can *default* to RA */
349 #define DRC1		(RCA + 1)
350   { 5, 0, 0,
351     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
352 
353   /* The RC field when it can *default* to RB */
354 #define DRC2		(DRC1 + 1)
355   { 5, 0, 0,
356     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
357 
358   /* The FC field when it can *default* to RA */
359 #define DFC1		(DRC2 + 1)
360   { 5, 0, 0,
361     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
362 
363   /* The FC field when it can *default* to RB */
364 #define DFC2		(DFC1 + 1)
365   { 5, 0, 0,
366     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
367 
368   /* The unsigned 8-bit literal of Operate format insns */
369 #define LIT		(DFC2 + 1)
370   { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
371 
372   /* The signed 16-bit displacement of Memory format insns.  From here
373      we can't tell what relocation should be used, so don't use a default. */
374 #define MDISP		(LIT + 1)
375   { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
376 
377   /* The signed "23-bit" aligned displacement of Branch format insns */
378 #define BDISP		(MDISP + 1)
379   { 21, 0, BFD_RELOC_23_PCREL_S2,
380     AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
381 
382   /* The 26-bit PALcode function */
383 #define PALFN		(BDISP + 1)
384   { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
385 
386   /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
387 #define JMPHINT		(PALFN + 1)
388   { 14, 0, BFD_RELOC_ALPHA_HINT,
389     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
390     insert_jhint, extract_jhint },
391 
392   /* The optional hint to RET/JSR_COROUTINE */
393 #define RETHINT		(JMPHINT + 1)
394   { 14, 0, -RETHINT,
395     AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
396 
397   /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
398 #define EV4HWDISP	(RETHINT + 1)
399 #define EV6HWDISP	(EV4HWDISP)
400   { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
401 
402   /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
403 #define EV4HWINDEX	(EV4HWDISP + 1)
404   { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
405 
406   /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
407      that occur in DEC PALcode.  */
408 #define EV4EXTHWINDEX	(EV4HWINDEX + 1)
409   { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
410 
411   /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
412 #define EV5HWDISP	(EV4EXTHWINDEX + 1)
413   { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
414 
415   /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
416 #define EV5HWINDEX	(EV5HWDISP + 1)
417   { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
418 
419   /* The 16-bit combined index/scoreboard mask for the ev6
420      hw_m[ft]pr (pal19/pal1d) insns */
421 #define EV6HWINDEX	(EV5HWINDEX + 1)
422   { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
423 
424   /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
425 #define EV6HWJMPHINT	(EV6HWINDEX+ 1)
426   { 8, 0, -EV6HWJMPHINT,
427     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
428     insert_ev6hwjhint, extract_ev6hwjhint }
429 };
430 
431 const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
432 
433 /* The RB field when it is the same as the RA field in the same insn.
434    This operand is marked fake.  The insertion function just copies
435    the RA field into the RB field, and the extraction function just
436    checks that the fields are the same. */
437 
438 /*ARGSUSED*/
439 static unsigned
insert_rba(unsigned insn,int value ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)440 insert_rba(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
441 {
442   return insn | (((insn >> 21) & 0x1f) << 16);
443 }
444 
445 static int
extract_rba(unsigned insn,int * invalid)446 extract_rba(unsigned insn, int *invalid)
447 {
448   if (invalid != (int *) NULL
449       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
450     *invalid = 1;
451   return 0;
452 }
453 
454 
455 /* The same for the RC field */
456 
457 /*ARGSUSED*/
458 static unsigned
insert_rca(unsigned insn,int value ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)459 insert_rca(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
460 {
461   return insn | ((insn >> 21) & 0x1f);
462 }
463 
464 static int
extract_rca(unsigned insn,int * invalid)465 extract_rca(unsigned insn, int *invalid)
466 {
467   if (invalid != (int *) NULL
468       && ((insn >> 21) & 0x1f) != (insn & 0x1f))
469     *invalid = 1;
470   return 0;
471 }
472 
473 
474 /* Fake arguments in which the registers must be set to ZERO */
475 
476 /*ARGSUSED*/
477 static unsigned
insert_za(unsigned insn,int value ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)478 insert_za(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
479 {
480   return insn | (31 << 21);
481 }
482 
483 static int
extract_za(unsigned insn,int * invalid)484 extract_za(unsigned insn, int *invalid)
485 {
486   if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
487     *invalid = 1;
488   return 0;
489 }
490 
491 /*ARGSUSED*/
492 static unsigned
insert_zb(unsigned insn,int value ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)493 insert_zb(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
494 {
495   return insn | (31 << 16);
496 }
497 
498 static int
extract_zb(unsigned insn,int * invalid)499 extract_zb(unsigned insn, int *invalid)
500 {
501   if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
502     *invalid = 1;
503   return 0;
504 }
505 
506 /*ARGSUSED*/
507 static unsigned
insert_zc(unsigned insn,int value ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)508 insert_zc(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
509 {
510   return insn | 31;
511 }
512 
513 static int
extract_zc(unsigned insn,int * invalid)514 extract_zc(unsigned insn, int *invalid)
515 {
516   if (invalid != (int *) NULL && (insn & 0x1f) != 31)
517     *invalid = 1;
518   return 0;
519 }
520 
521 
522 /* The displacement field of a Branch format insn.  */
523 
524 static unsigned
insert_bdisp(unsigned insn,int value,const char ** errmsg)525 insert_bdisp(unsigned insn, int value, const char **errmsg)
526 {
527   if (errmsg != (const char **)NULL && (value & 3))
528     *errmsg = _("branch operand unaligned");
529   return insn | ((value / 4) & 0x1FFFFF);
530 }
531 
532 /*ARGSUSED*/
533 static int
extract_bdisp(unsigned insn,int * invalid ATTRIBUTE_UNUSED)534 extract_bdisp(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
535 {
536   return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
537 }
538 
539 
540 /* The hint field of a JMP/JSR insn.  */
541 
542 static unsigned
insert_jhint(unsigned insn,int value,const char ** errmsg)543 insert_jhint(unsigned insn, int value, const char **errmsg)
544 {
545   if (errmsg != (const char **)NULL && (value & 3))
546     *errmsg = _("jump hint unaligned");
547   return insn | ((value / 4) & 0x3FFF);
548 }
549 
550 /*ARGSUSED*/
551 static int
extract_jhint(unsigned insn,int * invalid ATTRIBUTE_UNUSED)552 extract_jhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
553 {
554   return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
555 }
556 
557 /* The hint field of an EV6 HW_JMP/JSR insn.  */
558 
559 static unsigned
insert_ev6hwjhint(unsigned insn,int value,const char ** errmsg)560 insert_ev6hwjhint(unsigned insn, int value, const char **errmsg)
561 {
562   if (errmsg != (const char **)NULL && (value & 3))
563     *errmsg = _("jump hint unaligned");
564   return insn | ((value / 4) & 0x1FFF);
565 }
566 
567 /*ARGSUSED*/
568 static int
extract_ev6hwjhint(unsigned insn,int * invalid ATTRIBUTE_UNUSED)569 extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
570 {
571   return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
572 }
573 
574 
575 /* Macros used to form opcodes */
576 
577 /* The main opcode */
578 #define OP(x)		(((x) & 0x3F) << 26)
579 #define OP_MASK		0xFC000000
580 
581 /* Branch format instructions */
582 #define BRA_(oo)	OP(oo)
583 #define BRA_MASK	OP_MASK
584 #define BRA(oo)		BRA_(oo), BRA_MASK
585 
586 /* Floating point format instructions */
587 #define FP_(oo,fff)	(OP(oo) | (((fff) & 0x7FF) << 5))
588 #define FP_MASK		(OP_MASK | 0xFFE0)
589 #define FP(oo,fff)	FP_(oo,fff), FP_MASK
590 
591 /* Memory format instructions */
592 #define MEM_(oo)	OP(oo)
593 #define MEM_MASK	OP_MASK
594 #define MEM(oo)		MEM_(oo), MEM_MASK
595 
596 /* Memory/Func Code format instructions */
597 #define MFC_(oo,ffff)	(OP(oo) | ((ffff) & 0xFFFF))
598 #define MFC_MASK	(OP_MASK | 0xFFFF)
599 #define MFC(oo,ffff)	MFC_(oo,ffff), MFC_MASK
600 
601 /* Memory/Branch format instructions */
602 #define MBR_(oo,h)	(OP(oo) | (((h) & 3) << 14))
603 #define MBR_MASK	(OP_MASK | 0xC000)
604 #define MBR(oo,h)	MBR_(oo,h), MBR_MASK
605 
606 /* Operate format instructions.  The OPRL variant specifies a
607    literal second argument. */
608 #define OPR_(oo,ff)	(OP(oo) | (((ff) & 0x7F) << 5))
609 #define OPRL_(oo,ff)	(OPR_((oo),(ff)) | 0x1000)
610 #define OPR_MASK	(OP_MASK | 0x1FE0)
611 #define OPR(oo,ff)	OPR_(oo,ff), OPR_MASK
612 #define OPRL(oo,ff)	OPRL_(oo,ff), OPR_MASK
613 
614 /* Generic PALcode format instructions */
615 #define PCD_(oo)	OP(oo)
616 #define PCD_MASK	OP_MASK
617 #define PCD(oo)		PCD_(oo), PCD_MASK
618 
619 /* Specific PALcode instructions */
620 #define SPCD_(oo,ffff)	(OP(oo) | ((ffff) & 0x3FFFFFF))
621 #define SPCD_MASK	0xFFFFFFFF
622 #define SPCD(oo,ffff)	SPCD_(oo,ffff), SPCD_MASK
623 
624 /* Hardware memory (hw_{ld,st}) instructions */
625 #define EV4HWMEM_(oo,f)	(OP(oo) | (((f) & 0xF) << 12))
626 #define EV4HWMEM_MASK	(OP_MASK | 0xF000)
627 #define EV4HWMEM(oo,f)	EV4HWMEM_(oo,f), EV4HWMEM_MASK
628 
629 #define EV5HWMEM_(oo,f)	(OP(oo) | (((f) & 0x3F) << 10))
630 #define EV5HWMEM_MASK	(OP_MASK | 0xF800)
631 #define EV5HWMEM(oo,f)	EV5HWMEM_(oo,f), EV5HWMEM_MASK
632 
633 #define EV6HWMEM_(oo,f)	(OP(oo) | (((f) & 0xF) << 12))
634 #define EV6HWMEM_MASK	(OP_MASK | 0xF000)
635 #define EV6HWMEM(oo,f)	EV6HWMEM_(oo,f), EV6HWMEM_MASK
636 
637 #define EV6HWMBR_(oo,h)	(OP(oo) | (((h) & 7) << 13))
638 #define EV6HWMBR_MASK	(OP_MASK | 0xE000)
639 #define EV6HWMBR(oo,h)	EV6HWMBR_(oo,h), EV6HWMBR_MASK
640 
641 /* Abbreviations for instruction subsets.  */
642 #define BASE			AXP_OPCODE_BASE
643 #define EV4			AXP_OPCODE_EV4
644 #define EV5			AXP_OPCODE_EV5
645 #define EV6			AXP_OPCODE_EV6
646 #define BWX			AXP_OPCODE_BWX
647 #define CIX			AXP_OPCODE_CIX
648 #define MAX			AXP_OPCODE_MAX
649 
650 /* Common combinations of arguments */
651 #define ARG_NONE		{ 0 }
652 #define ARG_BRA			{ RA, BDISP }
653 #define ARG_FBRA		{ FA, BDISP }
654 #define ARG_FP			{ FA, FB, DFC1 }
655 #define ARG_FPZ1		{ ZA, FB, DFC1 }
656 #define ARG_MEM			{ RA, MDISP, PRB }
657 #define ARG_FMEM		{ FA, MDISP, PRB }
658 #define ARG_OPR			{ RA, RB, DRC1 }
659 #define ARG_OPRL		{ RA, LIT, DRC1 }
660 #define ARG_OPRZ1		{ ZA, RB, DRC1 }
661 #define ARG_OPRLZ1		{ ZA, LIT, RC }
662 #define ARG_PCD			{ PALFN }
663 #define ARG_EV4HWMEM		{ RA, EV4HWDISP, PRB }
664 #define ARG_EV4HWMPR		{ RA, RBA, EV4HWINDEX }
665 #define ARG_EV5HWMEM		{ RA, EV5HWDISP, PRB }
666 #define ARG_EV6HWMEM		{ RA, EV6HWDISP, PRB }
667 
668 /* The opcode table.
669 
670    The format of the opcode table is:
671 
672    NAME OPCODE MASK { OPERANDS }
673 
674    NAME		is the name of the instruction.
675 
676    OPCODE	is the instruction opcode.
677 
678    MASK		is the opcode mask; this is used to tell the disassembler
679             	which bits in the actual opcode must match OPCODE.
680 
681    OPERANDS	is the list of operands.
682 
683    The preceding macros merge the text of the OPCODE and MASK fields.
684 
685    The disassembler reads the table in order and prints the first
686    instruction which matches, so this table is sorted to put more
687    specific instructions before more general instructions.
688 
689    Otherwise, it is sorted by major opcode and minor function code.
690 
691    There are three classes of not-really-instructions in this table:
692 
693    ALIAS	is another name for another instruction.  Some of
694 		these come from the Architecture Handbook, some
695 		come from the original gas opcode tables.  In all
696 		cases, the functionality of the opcode is unchanged.
697 
698    PSEUDO	a stylized code form endorsed by Chapter A.4 of the
699 		Architecture Handbook.
700 
701    EXTRA	a stylized code form found in the original gas tables.
702 
703    And two annotations:
704 
705    EV56 BUT	opcodes that are officially introduced as of the ev56,
706    		but with defined results on previous implementations.
707 
708    EV56 UNA	opcodes that were introduced as of the ev56 with
709    		presumably undefined results on previous implementations
710 		that were not assigned to a particular extension.
711 */
712 
713 const struct alpha_opcode alpha_opcodes[] = {
714   { "halt",		SPCD(0x00,0x0000), BASE, ARG_NONE },
715   { "draina",		SPCD(0x00,0x0002), BASE, ARG_NONE },
716   { "bpt",		SPCD(0x00,0x0080), BASE, ARG_NONE },
717   { "bugchk",		SPCD(0x00,0x0081), BASE, ARG_NONE },
718   { "callsys",		SPCD(0x00,0x0083), BASE, ARG_NONE },
719   { "chmk", 		SPCD(0x00,0x0083), BASE, ARG_NONE },
720   { "imb",		SPCD(0x00,0x0086), BASE, ARG_NONE },
721   { "rduniq",		SPCD(0x00,0x009e), BASE, ARG_NONE },
722   { "wruniq",		SPCD(0x00,0x009f), BASE, ARG_NONE },
723   { "gentrap",		SPCD(0x00,0x00aa), BASE, ARG_NONE },
724   { "call_pal",		PCD(0x00), BASE, ARG_PCD },
725   { "pal",		PCD(0x00), BASE, ARG_PCD },		/* alias */
726 
727   { "lda",		MEM(0x08), BASE, { RA, MDISP, ZB } },	/* pseudo */
728   { "lda",		MEM(0x08), BASE, ARG_MEM },
729   { "ldah",		MEM(0x09), BASE, { RA, MDISP, ZB } },	/* pseudo */
730   { "ldah",		MEM(0x09), BASE, ARG_MEM },
731   { "ldbu",		MEM(0x0A), BWX, ARG_MEM },
732   { "unop",		MEM_(0x0B) | (30 << 16),
733 			MEM_MASK, BASE, { ZA } },		/* pseudo */
734   { "ldq_u",		MEM(0x0B), BASE, ARG_MEM },
735   { "ldwu",		MEM(0x0C), BWX, ARG_MEM },
736   { "stw",		MEM(0x0D), BWX, ARG_MEM },
737   { "stb",		MEM(0x0E), BWX, ARG_MEM },
738   { "stq_u",		MEM(0x0F), BASE, ARG_MEM },
739 
740   { "sextl",		OPR(0x10,0x00), BASE, ARG_OPRZ1 },	/* pseudo */
741   { "sextl",		OPRL(0x10,0x00), BASE, ARG_OPRLZ1 },	/* pseudo */
742   { "addl",		OPR(0x10,0x00), BASE, ARG_OPR },
743   { "addl",		OPRL(0x10,0x00), BASE, ARG_OPRL },
744   { "s4addl",		OPR(0x10,0x02), BASE, ARG_OPR },
745   { "s4addl",		OPRL(0x10,0x02), BASE, ARG_OPRL },
746   { "negl",		OPR(0x10,0x09), BASE, ARG_OPRZ1 },	/* pseudo */
747   { "negl",		OPRL(0x10,0x09), BASE, ARG_OPRLZ1 },	/* pseudo */
748   { "subl",		OPR(0x10,0x09), BASE, ARG_OPR },
749   { "subl",		OPRL(0x10,0x09), BASE, ARG_OPRL },
750   { "s4subl",		OPR(0x10,0x0B), BASE, ARG_OPR },
751   { "s4subl",		OPRL(0x10,0x0B), BASE, ARG_OPRL },
752   { "cmpbge",		OPR(0x10,0x0F), BASE, ARG_OPR },
753   { "cmpbge",		OPRL(0x10,0x0F), BASE, ARG_OPRL },
754   { "s8addl",		OPR(0x10,0x12), BASE, ARG_OPR },
755   { "s8addl",		OPRL(0x10,0x12), BASE, ARG_OPRL },
756   { "s8subl",		OPR(0x10,0x1B), BASE, ARG_OPR },
757   { "s8subl",		OPRL(0x10,0x1B), BASE, ARG_OPRL },
758   { "cmpult",		OPR(0x10,0x1D), BASE, ARG_OPR },
759   { "cmpult",		OPRL(0x10,0x1D), BASE, ARG_OPRL },
760   { "addq",		OPR(0x10,0x20), BASE, ARG_OPR },
761   { "addq",		OPRL(0x10,0x20), BASE, ARG_OPRL },
762   { "s4addq",		OPR(0x10,0x22), BASE, ARG_OPR },
763   { "s4addq",		OPRL(0x10,0x22), BASE, ARG_OPRL },
764   { "negq", 		OPR(0x10,0x29), BASE, ARG_OPRZ1 },	/* pseudo */
765   { "negq", 		OPRL(0x10,0x29), BASE, ARG_OPRLZ1 },	/* pseudo */
766   { "subq",		OPR(0x10,0x29), BASE, ARG_OPR },
767   { "subq",		OPRL(0x10,0x29), BASE, ARG_OPRL },
768   { "s4subq",		OPR(0x10,0x2B), BASE, ARG_OPR },
769   { "s4subq",		OPRL(0x10,0x2B), BASE, ARG_OPRL },
770   { "cmpeq",		OPR(0x10,0x2D), BASE, ARG_OPR },
771   { "cmpeq",		OPRL(0x10,0x2D), BASE, ARG_OPRL },
772   { "s8addq",		OPR(0x10,0x32), BASE, ARG_OPR },
773   { "s8addq",		OPRL(0x10,0x32), BASE, ARG_OPRL },
774   { "s8subq",		OPR(0x10,0x3B), BASE, ARG_OPR },
775   { "s8subq",		OPRL(0x10,0x3B), BASE, ARG_OPRL },
776   { "cmpule",		OPR(0x10,0x3D), BASE, ARG_OPR },
777   { "cmpule",		OPRL(0x10,0x3D), BASE, ARG_OPRL },
778   { "addl/v",		OPR(0x10,0x40), BASE, ARG_OPR },
779   { "addl/v",		OPRL(0x10,0x40), BASE, ARG_OPRL },
780   { "negl/v",		OPR(0x10,0x49), BASE, ARG_OPRZ1 },	/* pseudo */
781   { "negl/v",		OPRL(0x10,0x49), BASE, ARG_OPRLZ1 },	/* pseudo */
782   { "subl/v",		OPR(0x10,0x49), BASE, ARG_OPR },
783   { "subl/v",		OPRL(0x10,0x49), BASE, ARG_OPRL },
784   { "cmplt",		OPR(0x10,0x4D), BASE, ARG_OPR },
785   { "cmplt",		OPRL(0x10,0x4D), BASE, ARG_OPRL },
786   { "addq/v",		OPR(0x10,0x60), BASE, ARG_OPR },
787   { "addq/v",		OPRL(0x10,0x60), BASE, ARG_OPRL },
788   { "negq/v",		OPR(0x10,0x69), BASE, ARG_OPRZ1 },	/* pseudo */
789   { "negq/v",		OPRL(0x10,0x69), BASE, ARG_OPRLZ1 },	/* pseudo */
790   { "subq/v",		OPR(0x10,0x69), BASE, ARG_OPR },
791   { "subq/v",		OPRL(0x10,0x69), BASE, ARG_OPRL },
792   { "cmple",		OPR(0x10,0x6D), BASE, ARG_OPR },
793   { "cmple",		OPRL(0x10,0x6D), BASE, ARG_OPRL },
794 
795   { "and",		OPR(0x11,0x00), BASE, ARG_OPR },
796   { "and",		OPRL(0x11,0x00), BASE, ARG_OPRL },
797   { "andnot",		OPR(0x11,0x08), BASE, ARG_OPR },	/* alias */
798   { "andnot",		OPRL(0x11,0x08), BASE, ARG_OPRL },	/* alias */
799   { "bic",		OPR(0x11,0x08), BASE, ARG_OPR },
800   { "bic",		OPRL(0x11,0x08), BASE, ARG_OPRL },
801   { "cmovlbs",		OPR(0x11,0x14), BASE, ARG_OPR },
802   { "cmovlbs",		OPRL(0x11,0x14), BASE, ARG_OPRL },
803   { "cmovlbc",		OPR(0x11,0x16), BASE, ARG_OPR },
804   { "cmovlbc",		OPRL(0x11,0x16), BASE, ARG_OPRL },
805   { "nop",		OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
806   { "clr",		OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
807   { "mov",		OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
808   { "mov",		OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
809   { "mov",		OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
810   { "or",		OPR(0x11,0x20), BASE, ARG_OPR },	/* alias */
811   { "or",		OPRL(0x11,0x20), BASE, ARG_OPRL },	/* alias */
812   { "bis",		OPR(0x11,0x20), BASE, ARG_OPR },
813   { "bis",		OPRL(0x11,0x20), BASE, ARG_OPRL },
814   { "cmoveq",		OPR(0x11,0x24), BASE, ARG_OPR },
815   { "cmoveq",		OPRL(0x11,0x24), BASE, ARG_OPRL },
816   { "cmovne",		OPR(0x11,0x26), BASE, ARG_OPR },
817   { "cmovne",		OPRL(0x11,0x26), BASE, ARG_OPRL },
818   { "not",		OPR(0x11,0x28), BASE, ARG_OPRZ1 },	/* pseudo */
819   { "not",		OPRL(0x11,0x28), BASE, ARG_OPRLZ1 },	/* pseudo */
820   { "ornot",		OPR(0x11,0x28), BASE, ARG_OPR },
821   { "ornot",		OPRL(0x11,0x28), BASE, ARG_OPRL },
822   { "xor",		OPR(0x11,0x40), BASE, ARG_OPR },
823   { "xor",		OPRL(0x11,0x40), BASE, ARG_OPRL },
824   { "cmovlt",		OPR(0x11,0x44), BASE, ARG_OPR },
825   { "cmovlt",		OPRL(0x11,0x44), BASE, ARG_OPRL },
826   { "cmovge",		OPR(0x11,0x46), BASE, ARG_OPR },
827   { "cmovge",		OPRL(0x11,0x46), BASE, ARG_OPRL },
828   { "eqv",		OPR(0x11,0x48), BASE, ARG_OPR },
829   { "eqv",		OPRL(0x11,0x48), BASE, ARG_OPRL },
830   { "xornot",		OPR(0x11,0x48), BASE, ARG_OPR },	/* alias */
831   { "xornot",		OPRL(0x11,0x48), BASE, ARG_OPRL },	/* alias */
832   { "amask",		OPR(0x11,0x61), BASE, ARG_OPRZ1 },	/* ev56 but */
833   { "amask",		OPRL(0x11,0x61), BASE, ARG_OPRLZ1 },	/* ev56 but */
834   { "cmovle",		OPR(0x11,0x64), BASE, ARG_OPR },
835   { "cmovle",		OPRL(0x11,0x64), BASE, ARG_OPRL },
836   { "cmovgt",		OPR(0x11,0x66), BASE, ARG_OPR },
837   { "cmovgt",		OPRL(0x11,0x66), BASE, ARG_OPRL },
838   { "implver",		OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
839     			0xFFFFFFE0, BASE, { RC } },		/* ev56 but */
840 
841   { "mskbl",		OPR(0x12,0x02), BASE, ARG_OPR },
842   { "mskbl",		OPRL(0x12,0x02), BASE, ARG_OPRL },
843   { "extbl",		OPR(0x12,0x06), BASE, ARG_OPR },
844   { "extbl",		OPRL(0x12,0x06), BASE, ARG_OPRL },
845   { "insbl",		OPR(0x12,0x0B), BASE, ARG_OPR },
846   { "insbl",		OPRL(0x12,0x0B), BASE, ARG_OPRL },
847   { "mskwl",		OPR(0x12,0x12), BASE, ARG_OPR },
848   { "mskwl",		OPRL(0x12,0x12), BASE, ARG_OPRL },
849   { "extwl",		OPR(0x12,0x16), BASE, ARG_OPR },
850   { "extwl",		OPRL(0x12,0x16), BASE, ARG_OPRL },
851   { "inswl",		OPR(0x12,0x1B), BASE, ARG_OPR },
852   { "inswl",		OPRL(0x12,0x1B), BASE, ARG_OPRL },
853   { "mskll",		OPR(0x12,0x22), BASE, ARG_OPR },
854   { "mskll",		OPRL(0x12,0x22), BASE, ARG_OPRL },
855   { "extll",		OPR(0x12,0x26), BASE, ARG_OPR },
856   { "extll",		OPRL(0x12,0x26), BASE, ARG_OPRL },
857   { "insll",		OPR(0x12,0x2B), BASE, ARG_OPR },
858   { "insll",		OPRL(0x12,0x2B), BASE, ARG_OPRL },
859   { "zap",		OPR(0x12,0x30), BASE, ARG_OPR },
860   { "zap",		OPRL(0x12,0x30), BASE, ARG_OPRL },
861   { "zapnot",		OPR(0x12,0x31), BASE, ARG_OPR },
862   { "zapnot",		OPRL(0x12,0x31), BASE, ARG_OPRL },
863   { "mskql",		OPR(0x12,0x32), BASE, ARG_OPR },
864   { "mskql",		OPRL(0x12,0x32), BASE, ARG_OPRL },
865   { "srl",		OPR(0x12,0x34), BASE, ARG_OPR },
866   { "srl",		OPRL(0x12,0x34), BASE, ARG_OPRL },
867   { "extql",		OPR(0x12,0x36), BASE, ARG_OPR },
868   { "extql",		OPRL(0x12,0x36), BASE, ARG_OPRL },
869   { "sll",		OPR(0x12,0x39), BASE, ARG_OPR },
870   { "sll",		OPRL(0x12,0x39), BASE, ARG_OPRL },
871   { "insql",		OPR(0x12,0x3B), BASE, ARG_OPR },
872   { "insql",		OPRL(0x12,0x3B), BASE, ARG_OPRL },
873   { "sra",		OPR(0x12,0x3C), BASE, ARG_OPR },
874   { "sra",		OPRL(0x12,0x3C), BASE, ARG_OPRL },
875   { "mskwh",		OPR(0x12,0x52), BASE, ARG_OPR },
876   { "mskwh",		OPRL(0x12,0x52), BASE, ARG_OPRL },
877   { "inswh",		OPR(0x12,0x57), BASE, ARG_OPR },
878   { "inswh",		OPRL(0x12,0x57), BASE, ARG_OPRL },
879   { "extwh",		OPR(0x12,0x5A), BASE, ARG_OPR },
880   { "extwh",		OPRL(0x12,0x5A), BASE, ARG_OPRL },
881   { "msklh",		OPR(0x12,0x62), BASE, ARG_OPR },
882   { "msklh",		OPRL(0x12,0x62), BASE, ARG_OPRL },
883   { "inslh",		OPR(0x12,0x67), BASE, ARG_OPR },
884   { "inslh",		OPRL(0x12,0x67), BASE, ARG_OPRL },
885   { "extlh",		OPR(0x12,0x6A), BASE, ARG_OPR },
886   { "extlh",		OPRL(0x12,0x6A), BASE, ARG_OPRL },
887   { "mskqh",		OPR(0x12,0x72), BASE, ARG_OPR },
888   { "mskqh",		OPRL(0x12,0x72), BASE, ARG_OPRL },
889   { "insqh",		OPR(0x12,0x77), BASE, ARG_OPR },
890   { "insqh",		OPRL(0x12,0x77), BASE, ARG_OPRL },
891   { "extqh",		OPR(0x12,0x7A), BASE, ARG_OPR },
892   { "extqh",		OPRL(0x12,0x7A), BASE, ARG_OPRL },
893 
894   { "mull",		OPR(0x13,0x00), BASE, ARG_OPR },
895   { "mull",		OPRL(0x13,0x00), BASE, ARG_OPRL },
896   { "mulq",		OPR(0x13,0x20), BASE, ARG_OPR },
897   { "mulq",		OPRL(0x13,0x20), BASE, ARG_OPRL },
898   { "umulh",		OPR(0x13,0x30), BASE, ARG_OPR },
899   { "umulh",		OPRL(0x13,0x30), BASE, ARG_OPRL },
900   { "mull/v",		OPR(0x13,0x40), BASE, ARG_OPR },
901   { "mull/v",		OPRL(0x13,0x40), BASE, ARG_OPRL },
902   { "mulq/v",		OPR(0x13,0x60), BASE, ARG_OPR },
903   { "mulq/v",		OPRL(0x13,0x60), BASE, ARG_OPRL },
904 
905   { "itofs",		FP(0x14,0x004), CIX, { RA, ZB, FC } },
906   { "sqrtf/c",		FP(0x14,0x00A), CIX, ARG_FPZ1 },
907   { "sqrts/c",		FP(0x14,0x00B), CIX, ARG_FPZ1 },
908   { "itoff",		FP(0x14,0x014), CIX, { RA, ZB, FC } },
909   { "itoft",		FP(0x14,0x024), CIX, { RA, ZB, FC } },
910   { "sqrtg/c",		FP(0x14,0x02A), CIX, ARG_FPZ1 },
911   { "sqrtt/c",		FP(0x14,0x02B), CIX, ARG_FPZ1 },
912   { "sqrts/m",		FP(0x14,0x04B), CIX, ARG_FPZ1 },
913   { "sqrtt/m",		FP(0x14,0x06B), CIX, ARG_FPZ1 },
914   { "sqrtf",		FP(0x14,0x08A), CIX, ARG_FPZ1 },
915   { "sqrts",		FP(0x14,0x08B), CIX, ARG_FPZ1 },
916   { "sqrtg",		FP(0x14,0x0AA), CIX, ARG_FPZ1 },
917   { "sqrtt",		FP(0x14,0x0AB), CIX, ARG_FPZ1 },
918   { "sqrts/d",		FP(0x14,0x0CB), CIX, ARG_FPZ1 },
919   { "sqrtt/d",		FP(0x14,0x0EB), CIX, ARG_FPZ1 },
920   { "sqrtf/uc",		FP(0x14,0x10A), CIX, ARG_FPZ1 },
921   { "sqrts/uc",		FP(0x14,0x10B), CIX, ARG_FPZ1 },
922   { "sqrtg/uc",		FP(0x14,0x12A), CIX, ARG_FPZ1 },
923   { "sqrtt/uc",		FP(0x14,0x12B), CIX, ARG_FPZ1 },
924   { "sqrts/um",		FP(0x14,0x14B), CIX, ARG_FPZ1 },
925   { "sqrtt/um",		FP(0x14,0x16B), CIX, ARG_FPZ1 },
926   { "sqrtf/u",		FP(0x14,0x18A), CIX, ARG_FPZ1 },
927   { "sqrts/u",		FP(0x14,0x18B), CIX, ARG_FPZ1 },
928   { "sqrtg/u",		FP(0x14,0x1AA), CIX, ARG_FPZ1 },
929   { "sqrtt/u",		FP(0x14,0x1AB), CIX, ARG_FPZ1 },
930   { "sqrts/ud",		FP(0x14,0x1CB), CIX, ARG_FPZ1 },
931   { "sqrtt/ud",		FP(0x14,0x1EB), CIX, ARG_FPZ1 },
932   { "sqrtf/sc",		FP(0x14,0x40A), CIX, ARG_FPZ1 },
933   { "sqrtg/sc",		FP(0x14,0x42A), CIX, ARG_FPZ1 },
934   { "sqrtf/s",		FP(0x14,0x48A), CIX, ARG_FPZ1 },
935   { "sqrtg/s",		FP(0x14,0x4AA), CIX, ARG_FPZ1 },
936   { "sqrtf/suc",	FP(0x14,0x50A), CIX, ARG_FPZ1 },
937   { "sqrts/suc",	FP(0x14,0x50B), CIX, ARG_FPZ1 },
938   { "sqrtg/suc",	FP(0x14,0x52A), CIX, ARG_FPZ1 },
939   { "sqrtt/suc",	FP(0x14,0x52B), CIX, ARG_FPZ1 },
940   { "sqrts/sum",	FP(0x14,0x54B), CIX, ARG_FPZ1 },
941   { "sqrtt/sum",	FP(0x14,0x56B), CIX, ARG_FPZ1 },
942   { "sqrtf/su",		FP(0x14,0x58A), CIX, ARG_FPZ1 },
943   { "sqrts/su",		FP(0x14,0x58B), CIX, ARG_FPZ1 },
944   { "sqrtg/su",		FP(0x14,0x5AA), CIX, ARG_FPZ1 },
945   { "sqrtt/su",		FP(0x14,0x5AB), CIX, ARG_FPZ1 },
946   { "sqrts/sud",	FP(0x14,0x5CB), CIX, ARG_FPZ1 },
947   { "sqrtt/sud",	FP(0x14,0x5EB), CIX, ARG_FPZ1 },
948   { "sqrts/suic",	FP(0x14,0x70B), CIX, ARG_FPZ1 },
949   { "sqrtt/suic",	FP(0x14,0x72B), CIX, ARG_FPZ1 },
950   { "sqrts/suim",	FP(0x14,0x74B), CIX, ARG_FPZ1 },
951   { "sqrtt/suim",	FP(0x14,0x76B), CIX, ARG_FPZ1 },
952   { "sqrts/sui",	FP(0x14,0x78B), CIX, ARG_FPZ1 },
953   { "sqrtt/sui",	FP(0x14,0x7AB), CIX, ARG_FPZ1 },
954   { "sqrts/suid",	FP(0x14,0x7CB), CIX, ARG_FPZ1 },
955   { "sqrtt/suid",	FP(0x14,0x7EB), CIX, ARG_FPZ1 },
956 
957   { "addf/c",		FP(0x15,0x000), BASE, ARG_FP },
958   { "subf/c",		FP(0x15,0x001), BASE, ARG_FP },
959   { "mulf/c",		FP(0x15,0x002), BASE, ARG_FP },
960   { "divf/c",		FP(0x15,0x003), BASE, ARG_FP },
961   { "cvtdg/c",		FP(0x15,0x01E), BASE, ARG_FPZ1 },
962   { "addg/c",		FP(0x15,0x020), BASE, ARG_FP },
963   { "subg/c",		FP(0x15,0x021), BASE, ARG_FP },
964   { "mulg/c",		FP(0x15,0x022), BASE, ARG_FP },
965   { "divg/c",		FP(0x15,0x023), BASE, ARG_FP },
966   { "cvtgf/c",		FP(0x15,0x02C), BASE, ARG_FPZ1 },
967   { "cvtgd/c",		FP(0x15,0x02D), BASE, ARG_FPZ1 },
968   { "cvtgq/c",		FP(0x15,0x02F), BASE, ARG_FPZ1 },
969   { "cvtqf/c",		FP(0x15,0x03C), BASE, ARG_FPZ1 },
970   { "cvtqg/c",		FP(0x15,0x03E), BASE, ARG_FPZ1 },
971   { "addf",		FP(0x15,0x080), BASE, ARG_FP },
972   { "negf",		FP(0x15,0x081), BASE, ARG_FPZ1 },	/* pseudo */
973   { "subf",		FP(0x15,0x081), BASE, ARG_FP },
974   { "mulf",		FP(0x15,0x082), BASE, ARG_FP },
975   { "divf",		FP(0x15,0x083), BASE, ARG_FP },
976   { "cvtdg",		FP(0x15,0x09E), BASE, ARG_FPZ1 },
977   { "addg",		FP(0x15,0x0A0), BASE, ARG_FP },
978   { "negg",		FP(0x15,0x0A1), BASE, ARG_FPZ1 },	/* pseudo */
979   { "subg",		FP(0x15,0x0A1), BASE, ARG_FP },
980   { "mulg",		FP(0x15,0x0A2), BASE, ARG_FP },
981   { "divg",		FP(0x15,0x0A3), BASE, ARG_FP },
982   { "cmpgeq",		FP(0x15,0x0A5), BASE, ARG_FP },
983   { "cmpglt",		FP(0x15,0x0A6), BASE, ARG_FP },
984   { "cmpgle",		FP(0x15,0x0A7), BASE, ARG_FP },
985   { "cvtgf",		FP(0x15,0x0AC), BASE, ARG_FPZ1 },
986   { "cvtgd",		FP(0x15,0x0AD), BASE, ARG_FPZ1 },
987   { "cvtgq",		FP(0x15,0x0AF), BASE, ARG_FPZ1 },
988   { "cvtqf",		FP(0x15,0x0BC), BASE, ARG_FPZ1 },
989   { "cvtqg",		FP(0x15,0x0BE), BASE, ARG_FPZ1 },
990   { "addf/uc",		FP(0x15,0x100), BASE, ARG_FP },
991   { "subf/uc",		FP(0x15,0x101), BASE, ARG_FP },
992   { "mulf/uc",		FP(0x15,0x102), BASE, ARG_FP },
993   { "divf/uc",		FP(0x15,0x103), BASE, ARG_FP },
994   { "cvtdg/uc",		FP(0x15,0x11E), BASE, ARG_FPZ1 },
995   { "addg/uc",		FP(0x15,0x120), BASE, ARG_FP },
996   { "subg/uc",		FP(0x15,0x121), BASE, ARG_FP },
997   { "mulg/uc",		FP(0x15,0x122), BASE, ARG_FP },
998   { "divg/uc",		FP(0x15,0x123), BASE, ARG_FP },
999   { "cvtgf/uc",		FP(0x15,0x12C), BASE, ARG_FPZ1 },
1000   { "cvtgd/uc",		FP(0x15,0x12D), BASE, ARG_FPZ1 },
1001   { "cvtgq/vc",		FP(0x15,0x12F), BASE, ARG_FPZ1 },
1002   { "addf/u",		FP(0x15,0x180), BASE, ARG_FP },
1003   { "subf/u",		FP(0x15,0x181), BASE, ARG_FP },
1004   { "mulf/u",		FP(0x15,0x182), BASE, ARG_FP },
1005   { "divf/u",		FP(0x15,0x183), BASE, ARG_FP },
1006   { "cvtdg/u",		FP(0x15,0x19E), BASE, ARG_FPZ1 },
1007   { "addg/u",		FP(0x15,0x1A0), BASE, ARG_FP },
1008   { "subg/u",		FP(0x15,0x1A1), BASE, ARG_FP },
1009   { "mulg/u",		FP(0x15,0x1A2), BASE, ARG_FP },
1010   { "divg/u",		FP(0x15,0x1A3), BASE, ARG_FP },
1011   { "cvtgf/u",		FP(0x15,0x1AC), BASE, ARG_FPZ1 },
1012   { "cvtgd/u",		FP(0x15,0x1AD), BASE, ARG_FPZ1 },
1013   { "cvtgq/v",		FP(0x15,0x1AF), BASE, ARG_FPZ1 },
1014   { "addf/sc",		FP(0x15,0x400), BASE, ARG_FP },
1015   { "subf/sc",		FP(0x15,0x401), BASE, ARG_FP },
1016   { "mulf/sc",		FP(0x15,0x402), BASE, ARG_FP },
1017   { "divf/sc",		FP(0x15,0x403), BASE, ARG_FP },
1018   { "cvtdg/sc",		FP(0x15,0x41E), BASE, ARG_FPZ1 },
1019   { "addg/sc",		FP(0x15,0x420), BASE, ARG_FP },
1020   { "subg/sc",		FP(0x15,0x421), BASE, ARG_FP },
1021   { "mulg/sc",		FP(0x15,0x422), BASE, ARG_FP },
1022   { "divg/sc",		FP(0x15,0x423), BASE, ARG_FP },
1023   { "cvtgf/sc",		FP(0x15,0x42C), BASE, ARG_FPZ1 },
1024   { "cvtgd/sc",		FP(0x15,0x42D), BASE, ARG_FPZ1 },
1025   { "cvtgq/sc",		FP(0x15,0x42F), BASE, ARG_FPZ1 },
1026   { "addf/s",		FP(0x15,0x480), BASE, ARG_FP },
1027   { "negf/s",		FP(0x15,0x481), BASE, ARG_FPZ1 },	/* pseudo */
1028   { "subf/s",		FP(0x15,0x481), BASE, ARG_FP },
1029   { "mulf/s",		FP(0x15,0x482), BASE, ARG_FP },
1030   { "divf/s",		FP(0x15,0x483), BASE, ARG_FP },
1031   { "cvtdg/s",		FP(0x15,0x49E), BASE, ARG_FPZ1 },
1032   { "addg/s",		FP(0x15,0x4A0), BASE, ARG_FP },
1033   { "negg/s",		FP(0x15,0x4A1), BASE, ARG_FPZ1 },	/* pseudo */
1034   { "subg/s",		FP(0x15,0x4A1), BASE, ARG_FP },
1035   { "mulg/s",		FP(0x15,0x4A2), BASE, ARG_FP },
1036   { "divg/s",		FP(0x15,0x4A3), BASE, ARG_FP },
1037   { "cmpgeq/s",		FP(0x15,0x4A5), BASE, ARG_FP },
1038   { "cmpglt/s",		FP(0x15,0x4A6), BASE, ARG_FP },
1039   { "cmpgle/s",		FP(0x15,0x4A7), BASE, ARG_FP },
1040   { "cvtgf/s",		FP(0x15,0x4AC), BASE, ARG_FPZ1 },
1041   { "cvtgd/s",		FP(0x15,0x4AD), BASE, ARG_FPZ1 },
1042   { "cvtgq/s",		FP(0x15,0x4AF), BASE, ARG_FPZ1 },
1043   { "addf/suc",		FP(0x15,0x500), BASE, ARG_FP },
1044   { "subf/suc",		FP(0x15,0x501), BASE, ARG_FP },
1045   { "mulf/suc",		FP(0x15,0x502), BASE, ARG_FP },
1046   { "divf/suc",		FP(0x15,0x503), BASE, ARG_FP },
1047   { "cvtdg/suc",	FP(0x15,0x51E), BASE, ARG_FPZ1 },
1048   { "addg/suc",		FP(0x15,0x520), BASE, ARG_FP },
1049   { "subg/suc",		FP(0x15,0x521), BASE, ARG_FP },
1050   { "mulg/suc",		FP(0x15,0x522), BASE, ARG_FP },
1051   { "divg/suc",		FP(0x15,0x523), BASE, ARG_FP },
1052   { "cvtgf/suc",	FP(0x15,0x52C), BASE, ARG_FPZ1 },
1053   { "cvtgd/suc",	FP(0x15,0x52D), BASE, ARG_FPZ1 },
1054   { "cvtgq/svc",	FP(0x15,0x52F), BASE, ARG_FPZ1 },
1055   { "addf/su",		FP(0x15,0x580), BASE, ARG_FP },
1056   { "subf/su",		FP(0x15,0x581), BASE, ARG_FP },
1057   { "mulf/su",		FP(0x15,0x582), BASE, ARG_FP },
1058   { "divf/su",		FP(0x15,0x583), BASE, ARG_FP },
1059   { "cvtdg/su",		FP(0x15,0x59E), BASE, ARG_FPZ1 },
1060   { "addg/su",		FP(0x15,0x5A0), BASE, ARG_FP },
1061   { "subg/su",		FP(0x15,0x5A1), BASE, ARG_FP },
1062   { "mulg/su",		FP(0x15,0x5A2), BASE, ARG_FP },
1063   { "divg/su",		FP(0x15,0x5A3), BASE, ARG_FP },
1064   { "cvtgf/su",		FP(0x15,0x5AC), BASE, ARG_FPZ1 },
1065   { "cvtgd/su",		FP(0x15,0x5AD), BASE, ARG_FPZ1 },
1066   { "cvtgq/sv",		FP(0x15,0x5AF), BASE, ARG_FPZ1 },
1067 
1068   { "adds/c",		FP(0x16,0x000), BASE, ARG_FP },
1069   { "subs/c",		FP(0x16,0x001), BASE, ARG_FP },
1070   { "muls/c",		FP(0x16,0x002), BASE, ARG_FP },
1071   { "divs/c",		FP(0x16,0x003), BASE, ARG_FP },
1072   { "addt/c",		FP(0x16,0x020), BASE, ARG_FP },
1073   { "subt/c",		FP(0x16,0x021), BASE, ARG_FP },
1074   { "mult/c",		FP(0x16,0x022), BASE, ARG_FP },
1075   { "divt/c",		FP(0x16,0x023), BASE, ARG_FP },
1076   { "cvtts/c",		FP(0x16,0x02C), BASE, ARG_FPZ1 },
1077   { "cvttq/c",		FP(0x16,0x02F), BASE, ARG_FPZ1 },
1078   { "cvtqs/c",		FP(0x16,0x03C), BASE, ARG_FPZ1 },
1079   { "cvtqt/c",		FP(0x16,0x03E), BASE, ARG_FPZ1 },
1080   { "adds/m",		FP(0x16,0x040), BASE, ARG_FP },
1081   { "subs/m",		FP(0x16,0x041), BASE, ARG_FP },
1082   { "muls/m",		FP(0x16,0x042), BASE, ARG_FP },
1083   { "divs/m",		FP(0x16,0x043), BASE, ARG_FP },
1084   { "addt/m",		FP(0x16,0x060), BASE, ARG_FP },
1085   { "subt/m",		FP(0x16,0x061), BASE, ARG_FP },
1086   { "mult/m",		FP(0x16,0x062), BASE, ARG_FP },
1087   { "divt/m",		FP(0x16,0x063), BASE, ARG_FP },
1088   { "cvtts/m",		FP(0x16,0x06C), BASE, ARG_FPZ1 },
1089   { "cvttq/m",		FP(0x16,0x06F), BASE, ARG_FPZ1 },
1090   { "cvtqs/m",		FP(0x16,0x07C), BASE, ARG_FPZ1 },
1091   { "cvtqt/m",		FP(0x16,0x07E), BASE, ARG_FPZ1 },
1092   { "adds",		FP(0x16,0x080), BASE, ARG_FP },
1093   { "negs", 		FP(0x16,0x081), BASE, ARG_FPZ1 },	/* pseudo */
1094   { "subs",		FP(0x16,0x081), BASE, ARG_FP },
1095   { "muls",		FP(0x16,0x082), BASE, ARG_FP },
1096   { "divs",		FP(0x16,0x083), BASE, ARG_FP },
1097   { "addt",		FP(0x16,0x0A0), BASE, ARG_FP },
1098   { "negt", 		FP(0x16,0x0A1), BASE, ARG_FPZ1 },	/* pseudo */
1099   { "subt",		FP(0x16,0x0A1), BASE, ARG_FP },
1100   { "mult",		FP(0x16,0x0A2), BASE, ARG_FP },
1101   { "divt",		FP(0x16,0x0A3), BASE, ARG_FP },
1102   { "cmptun",		FP(0x16,0x0A4), BASE, ARG_FP },
1103   { "cmpteq",		FP(0x16,0x0A5), BASE, ARG_FP },
1104   { "cmptlt",		FP(0x16,0x0A6), BASE, ARG_FP },
1105   { "cmptle",		FP(0x16,0x0A7), BASE, ARG_FP },
1106   { "cvtts",		FP(0x16,0x0AC), BASE, ARG_FPZ1 },
1107   { "cvttq",		FP(0x16,0x0AF), BASE, ARG_FPZ1 },
1108   { "cvtqs",		FP(0x16,0x0BC), BASE, ARG_FPZ1 },
1109   { "cvtqt",		FP(0x16,0x0BE), BASE, ARG_FPZ1 },
1110   { "adds/d",		FP(0x16,0x0C0), BASE, ARG_FP },
1111   { "subs/d",		FP(0x16,0x0C1), BASE, ARG_FP },
1112   { "muls/d",		FP(0x16,0x0C2), BASE, ARG_FP },
1113   { "divs/d",		FP(0x16,0x0C3), BASE, ARG_FP },
1114   { "addt/d",		FP(0x16,0x0E0), BASE, ARG_FP },
1115   { "subt/d",		FP(0x16,0x0E1), BASE, ARG_FP },
1116   { "mult/d",		FP(0x16,0x0E2), BASE, ARG_FP },
1117   { "divt/d",		FP(0x16,0x0E3), BASE, ARG_FP },
1118   { "cvtts/d",		FP(0x16,0x0EC), BASE, ARG_FPZ1 },
1119   { "cvttq/d",		FP(0x16,0x0EF), BASE, ARG_FPZ1 },
1120   { "cvtqs/d",		FP(0x16,0x0FC), BASE, ARG_FPZ1 },
1121   { "cvtqt/d",		FP(0x16,0x0FE), BASE, ARG_FPZ1 },
1122   { "adds/uc",		FP(0x16,0x100), BASE, ARG_FP },
1123   { "subs/uc",		FP(0x16,0x101), BASE, ARG_FP },
1124   { "muls/uc",		FP(0x16,0x102), BASE, ARG_FP },
1125   { "divs/uc",		FP(0x16,0x103), BASE, ARG_FP },
1126   { "addt/uc",		FP(0x16,0x120), BASE, ARG_FP },
1127   { "subt/uc",		FP(0x16,0x121), BASE, ARG_FP },
1128   { "mult/uc",		FP(0x16,0x122), BASE, ARG_FP },
1129   { "divt/uc",		FP(0x16,0x123), BASE, ARG_FP },
1130   { "cvtts/uc",		FP(0x16,0x12C), BASE, ARG_FPZ1 },
1131   { "cvttq/vc",		FP(0x16,0x12F), BASE, ARG_FPZ1 },
1132   { "adds/um",		FP(0x16,0x140), BASE, ARG_FP },
1133   { "subs/um",		FP(0x16,0x141), BASE, ARG_FP },
1134   { "muls/um",		FP(0x16,0x142), BASE, ARG_FP },
1135   { "divs/um",		FP(0x16,0x143), BASE, ARG_FP },
1136   { "addt/um",		FP(0x16,0x160), BASE, ARG_FP },
1137   { "subt/um",		FP(0x16,0x161), BASE, ARG_FP },
1138   { "mult/um",		FP(0x16,0x162), BASE, ARG_FP },
1139   { "divt/um",		FP(0x16,0x163), BASE, ARG_FP },
1140   { "cvtts/um",		FP(0x16,0x16C), BASE, ARG_FPZ1 },
1141   { "cvttq/vm",		FP(0x16,0x16F), BASE, ARG_FPZ1 },
1142   { "adds/u",		FP(0x16,0x180), BASE, ARG_FP },
1143   { "subs/u",		FP(0x16,0x181), BASE, ARG_FP },
1144   { "muls/u",		FP(0x16,0x182), BASE, ARG_FP },
1145   { "divs/u",		FP(0x16,0x183), BASE, ARG_FP },
1146   { "addt/u",		FP(0x16,0x1A0), BASE, ARG_FP },
1147   { "subt/u",		FP(0x16,0x1A1), BASE, ARG_FP },
1148   { "mult/u",		FP(0x16,0x1A2), BASE, ARG_FP },
1149   { "divt/u",		FP(0x16,0x1A3), BASE, ARG_FP },
1150   { "cvtts/u",		FP(0x16,0x1AC), BASE, ARG_FPZ1 },
1151   { "cvttq/v",		FP(0x16,0x1AF), BASE, ARG_FPZ1 },
1152   { "adds/ud",		FP(0x16,0x1C0), BASE, ARG_FP },
1153   { "subs/ud",		FP(0x16,0x1C1), BASE, ARG_FP },
1154   { "muls/ud",		FP(0x16,0x1C2), BASE, ARG_FP },
1155   { "divs/ud",		FP(0x16,0x1C3), BASE, ARG_FP },
1156   { "addt/ud",		FP(0x16,0x1E0), BASE, ARG_FP },
1157   { "subt/ud",		FP(0x16,0x1E1), BASE, ARG_FP },
1158   { "mult/ud",		FP(0x16,0x1E2), BASE, ARG_FP },
1159   { "divt/ud",		FP(0x16,0x1E3), BASE, ARG_FP },
1160   { "cvtts/ud",		FP(0x16,0x1EC), BASE, ARG_FPZ1 },
1161   { "cvttq/vd",		FP(0x16,0x1EF), BASE, ARG_FPZ1 },
1162   { "cvtst",		FP(0x16,0x2AC), BASE, ARG_FPZ1 },
1163   { "adds/suc",		FP(0x16,0x500), BASE, ARG_FP },
1164   { "subs/suc",		FP(0x16,0x501), BASE, ARG_FP },
1165   { "muls/suc",		FP(0x16,0x502), BASE, ARG_FP },
1166   { "divs/suc",		FP(0x16,0x503), BASE, ARG_FP },
1167   { "addt/suc",		FP(0x16,0x520), BASE, ARG_FP },
1168   { "subt/suc",		FP(0x16,0x521), BASE, ARG_FP },
1169   { "mult/suc",		FP(0x16,0x522), BASE, ARG_FP },
1170   { "divt/suc",		FP(0x16,0x523), BASE, ARG_FP },
1171   { "cvtts/suc",	FP(0x16,0x52C), BASE, ARG_FPZ1 },
1172   { "cvttq/svc",	FP(0x16,0x52F), BASE, ARG_FPZ1 },
1173   { "adds/sum",		FP(0x16,0x540), BASE, ARG_FP },
1174   { "subs/sum",		FP(0x16,0x541), BASE, ARG_FP },
1175   { "muls/sum",		FP(0x16,0x542), BASE, ARG_FP },
1176   { "divs/sum",		FP(0x16,0x543), BASE, ARG_FP },
1177   { "addt/sum",		FP(0x16,0x560), BASE, ARG_FP },
1178   { "subt/sum",		FP(0x16,0x561), BASE, ARG_FP },
1179   { "mult/sum",		FP(0x16,0x562), BASE, ARG_FP },
1180   { "divt/sum",		FP(0x16,0x563), BASE, ARG_FP },
1181   { "cvtts/sum",	FP(0x16,0x56C), BASE, ARG_FPZ1 },
1182   { "cvttq/svm",	FP(0x16,0x56F), BASE, ARG_FPZ1 },
1183   { "adds/su",		FP(0x16,0x580), BASE, ARG_FP },
1184   { "negs/su",		FP(0x16,0x581), BASE, ARG_FPZ1 },	/* pseudo */
1185   { "subs/su",		FP(0x16,0x581), BASE, ARG_FP },
1186   { "muls/su",		FP(0x16,0x582), BASE, ARG_FP },
1187   { "divs/su",		FP(0x16,0x583), BASE, ARG_FP },
1188   { "addt/su",		FP(0x16,0x5A0), BASE, ARG_FP },
1189   { "negt/su",		FP(0x16,0x5A1), BASE, ARG_FPZ1 },	/* pseudo */
1190   { "subt/su",		FP(0x16,0x5A1), BASE, ARG_FP },
1191   { "mult/su",		FP(0x16,0x5A2), BASE, ARG_FP },
1192   { "divt/su",		FP(0x16,0x5A3), BASE, ARG_FP },
1193   { "cmptun/su",	FP(0x16,0x5A4), BASE, ARG_FP },
1194   { "cmpteq/su",	FP(0x16,0x5A5), BASE, ARG_FP },
1195   { "cmptlt/su",	FP(0x16,0x5A6), BASE, ARG_FP },
1196   { "cmptle/su",	FP(0x16,0x5A7), BASE, ARG_FP },
1197   { "cvtts/su",		FP(0x16,0x5AC), BASE, ARG_FPZ1 },
1198   { "cvttq/sv",		FP(0x16,0x5AF), BASE, ARG_FPZ1 },
1199   { "adds/sud",		FP(0x16,0x5C0), BASE, ARG_FP },
1200   { "subs/sud",		FP(0x16,0x5C1), BASE, ARG_FP },
1201   { "muls/sud",		FP(0x16,0x5C2), BASE, ARG_FP },
1202   { "divs/sud",		FP(0x16,0x5C3), BASE, ARG_FP },
1203   { "addt/sud",		FP(0x16,0x5E0), BASE, ARG_FP },
1204   { "subt/sud",		FP(0x16,0x5E1), BASE, ARG_FP },
1205   { "mult/sud",		FP(0x16,0x5E2), BASE, ARG_FP },
1206   { "divt/sud",		FP(0x16,0x5E3), BASE, ARG_FP },
1207   { "cvtts/sud",	FP(0x16,0x5EC), BASE, ARG_FPZ1 },
1208   { "cvttq/svd",	FP(0x16,0x5EF), BASE, ARG_FPZ1 },
1209   { "cvtst/s",		FP(0x16,0x6AC), BASE, ARG_FPZ1 },
1210   { "adds/suic",	FP(0x16,0x700), BASE, ARG_FP },
1211   { "subs/suic",	FP(0x16,0x701), BASE, ARG_FP },
1212   { "muls/suic",	FP(0x16,0x702), BASE, ARG_FP },
1213   { "divs/suic",	FP(0x16,0x703), BASE, ARG_FP },
1214   { "addt/suic",	FP(0x16,0x720), BASE, ARG_FP },
1215   { "subt/suic",	FP(0x16,0x721), BASE, ARG_FP },
1216   { "mult/suic",	FP(0x16,0x722), BASE, ARG_FP },
1217   { "divt/suic",	FP(0x16,0x723), BASE, ARG_FP },
1218   { "cvtts/suic",	FP(0x16,0x72C), BASE, ARG_FPZ1 },
1219   { "cvttq/svic",	FP(0x16,0x72F), BASE, ARG_FPZ1 },
1220   { "cvtqs/suic",	FP(0x16,0x73C), BASE, ARG_FPZ1 },
1221   { "cvtqt/suic",	FP(0x16,0x73E), BASE, ARG_FPZ1 },
1222   { "adds/suim",	FP(0x16,0x740), BASE, ARG_FP },
1223   { "subs/suim",	FP(0x16,0x741), BASE, ARG_FP },
1224   { "muls/suim",	FP(0x16,0x742), BASE, ARG_FP },
1225   { "divs/suim",	FP(0x16,0x743), BASE, ARG_FP },
1226   { "addt/suim",	FP(0x16,0x760), BASE, ARG_FP },
1227   { "subt/suim",	FP(0x16,0x761), BASE, ARG_FP },
1228   { "mult/suim",	FP(0x16,0x762), BASE, ARG_FP },
1229   { "divt/suim",	FP(0x16,0x763), BASE, ARG_FP },
1230   { "cvtts/suim",	FP(0x16,0x76C), BASE, ARG_FPZ1 },
1231   { "cvttq/svim",	FP(0x16,0x76F), BASE, ARG_FPZ1 },
1232   { "cvtqs/suim",	FP(0x16,0x77C), BASE, ARG_FPZ1 },
1233   { "cvtqt/suim",	FP(0x16,0x77E), BASE, ARG_FPZ1 },
1234   { "adds/sui",		FP(0x16,0x780), BASE, ARG_FP },
1235   { "negs/sui", 	FP(0x16,0x781), BASE, ARG_FPZ1 },	/* pseudo */
1236   { "subs/sui",		FP(0x16,0x781), BASE, ARG_FP },
1237   { "muls/sui",		FP(0x16,0x782), BASE, ARG_FP },
1238   { "divs/sui",		FP(0x16,0x783), BASE, ARG_FP },
1239   { "addt/sui",		FP(0x16,0x7A0), BASE, ARG_FP },
1240   { "negt/sui", 	FP(0x16,0x7A1), BASE, ARG_FPZ1 },	/* pseudo */
1241   { "subt/sui",		FP(0x16,0x7A1), BASE, ARG_FP },
1242   { "mult/sui",		FP(0x16,0x7A2), BASE, ARG_FP },
1243   { "divt/sui",		FP(0x16,0x7A3), BASE, ARG_FP },
1244   { "cvtts/sui",	FP(0x16,0x7AC), BASE, ARG_FPZ1 },
1245   { "cvttq/svi",	FP(0x16,0x7AF), BASE, ARG_FPZ1 },
1246   { "cvtqs/sui",	FP(0x16,0x7BC), BASE, ARG_FPZ1 },
1247   { "cvtqt/sui",	FP(0x16,0x7BE), BASE, ARG_FPZ1 },
1248   { "adds/suid",	FP(0x16,0x7C0), BASE, ARG_FP },
1249   { "subs/suid",	FP(0x16,0x7C1), BASE, ARG_FP },
1250   { "muls/suid",	FP(0x16,0x7C2), BASE, ARG_FP },
1251   { "divs/suid",	FP(0x16,0x7C3), BASE, ARG_FP },
1252   { "addt/suid",	FP(0x16,0x7E0), BASE, ARG_FP },
1253   { "subt/suid",	FP(0x16,0x7E1), BASE, ARG_FP },
1254   { "mult/suid",	FP(0x16,0x7E2), BASE, ARG_FP },
1255   { "divt/suid",	FP(0x16,0x7E3), BASE, ARG_FP },
1256   { "cvtts/suid",	FP(0x16,0x7EC), BASE, ARG_FPZ1 },
1257   { "cvttq/svid",	FP(0x16,0x7EF), BASE, ARG_FPZ1 },
1258   { "cvtqs/suid",	FP(0x16,0x7FC), BASE, ARG_FPZ1 },
1259   { "cvtqt/suid",	FP(0x16,0x7FE), BASE, ARG_FPZ1 },
1260 
1261   { "cvtlq",		FP(0x17,0x010), BASE, ARG_FPZ1 },
1262   { "fnop",		FP(0x17,0x020), BASE, { ZA, ZB, ZC } },	/* pseudo */
1263   { "fclr",		FP(0x17,0x020), BASE, { ZA, ZB, FC } },	/* pseudo */
1264   { "fabs",		FP(0x17,0x020), BASE, ARG_FPZ1 },	/* pseudo */
1265   { "fmov",		FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */
1266   { "cpys",		FP(0x17,0x020), BASE, ARG_FP },
1267   { "fneg",		FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */
1268   { "cpysn",		FP(0x17,0x021), BASE, ARG_FP },
1269   { "cpyse",		FP(0x17,0x022), BASE, ARG_FP },
1270   { "mt_fpcr",		FP(0x17,0x024), BASE, { FA, RBA, RCA } },
1271   { "mf_fpcr",		FP(0x17,0x025), BASE, { FA, RBA, RCA } },
1272   { "fcmoveq",		FP(0x17,0x02A), BASE, ARG_FP },
1273   { "fcmovne",		FP(0x17,0x02B), BASE, ARG_FP },
1274   { "fcmovlt",		FP(0x17,0x02C), BASE, ARG_FP },
1275   { "fcmovge",		FP(0x17,0x02D), BASE, ARG_FP },
1276   { "fcmovle",		FP(0x17,0x02E), BASE, ARG_FP },
1277   { "fcmovgt",		FP(0x17,0x02F), BASE, ARG_FP },
1278   { "cvtql",		FP(0x17,0x030), BASE, ARG_FPZ1 },
1279   { "cvtql/v",		FP(0x17,0x130), BASE, ARG_FPZ1 },
1280   { "cvtql/sv",		FP(0x17,0x530), BASE, ARG_FPZ1 },
1281 
1282   { "trapb",		MFC(0x18,0x0000), BASE, ARG_NONE },
1283   { "draint",		MFC(0x18,0x0000), BASE, ARG_NONE },	/* alias */
1284   { "excb",		MFC(0x18,0x0400), BASE, ARG_NONE },
1285   { "mb",		MFC(0x18,0x4000), BASE, ARG_NONE },
1286   { "wmb",		MFC(0x18,0x4400), BASE, ARG_NONE },
1287   { "fetch",		MFC(0x18,0x8000), BASE, { ZA, PRB } },
1288   { "fetch_m",		MFC(0x18,0xA000), BASE, { ZA, PRB } },
1289   { "rpcc",		MFC(0x18,0xC000), BASE, { RA } },
1290   { "rc",		MFC(0x18,0xE000), BASE, { RA } },
1291   { "ecb",		MFC(0x18,0xE800), BASE, { ZA, PRB } },	/* ev56 una */
1292   { "rs",		MFC(0x18,0xF000), BASE, { RA } },
1293   { "wh64",		MFC(0x18,0xF800), BASE, { ZA, PRB } },	/* ev56 una */
1294   { "wh64en",		MFC(0x18,0xFC00), BASE, { ZA, PRB } },	/* ev7 una */
1295 
1296   { "hw_mfpr",		OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1297   { "hw_mfpr",		OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1298   { "hw_mfpr",		OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
1299   { "hw_mfpr/i",	OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
1300   { "hw_mfpr/a",	OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
1301   { "hw_mfpr/ai",	OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
1302   { "hw_mfpr/p",	OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
1303   { "hw_mfpr/pi",	OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
1304   { "hw_mfpr/pa",	OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
1305   { "hw_mfpr/pai",	OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
1306   { "pal19",		PCD(0x19), BASE, ARG_PCD },
1307 
1308   { "jmp",		MBR_(0x1A,0), MBR_MASK | 0x3FFF,	/* pseudo */
1309 			BASE, { ZA, CPRB } },
1310   { "jmp",		MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
1311   { "jsr",		MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
1312   { "ret",		MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */
1313 			0xFFFFFFFF, BASE, { 0 } },
1314   { "ret",		MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
1315   { "jcr",		MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
1316   { "jsr_coroutine",	MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
1317 
1318   { "hw_ldl",		EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1319   { "hw_ldl",		EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1320   { "hw_ldl",		EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM },
1321   { "hw_ldl/a",		EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1322   { "hw_ldl/a",		EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1323   { "hw_ldl/a",		EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM },
1324   { "hw_ldl/al",	EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1325   { "hw_ldl/ar",	EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1326   { "hw_ldl/av",	EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1327   { "hw_ldl/avl",	EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1328   { "hw_ldl/aw",	EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1329   { "hw_ldl/awl",	EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1330   { "hw_ldl/awv",	EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1331   { "hw_ldl/awvl",	EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1332   { "hw_ldl/l",		EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1333   { "hw_ldl/p",		EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1334   { "hw_ldl/p",		EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1335   { "hw_ldl/p",		EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM },
1336   { "hw_ldl/pa",	EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1337   { "hw_ldl/pa",	EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1338   { "hw_ldl/pal",	EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1339   { "hw_ldl/par",	EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1340   { "hw_ldl/pav",	EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1341   { "hw_ldl/pavl",	EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1342   { "hw_ldl/paw",	EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1343   { "hw_ldl/pawl",	EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1344   { "hw_ldl/pawv",	EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1345   { "hw_ldl/pawvl",	EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1346   { "hw_ldl/pl",	EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1347   { "hw_ldl/pr",	EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1348   { "hw_ldl/pv",	EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1349   { "hw_ldl/pvl",	EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1350   { "hw_ldl/pw",	EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1351   { "hw_ldl/pwl",	EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1352   { "hw_ldl/pwv",	EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1353   { "hw_ldl/pwvl",	EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1354   { "hw_ldl/r",		EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1355   { "hw_ldl/v",		EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1356   { "hw_ldl/v",		EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM },
1357   { "hw_ldl/vl",	EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1358   { "hw_ldl/w",		EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1359   { "hw_ldl/w",		EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM },
1360   { "hw_ldl/wa",	EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM },
1361   { "hw_ldl/wl",	EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1362   { "hw_ldl/wv",	EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1363   { "hw_ldl/wvl",	EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1364   { "hw_ldl_l",		EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1365   { "hw_ldl_l/a",	EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1366   { "hw_ldl_l/av",	EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1367   { "hw_ldl_l/aw",	EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1368   { "hw_ldl_l/awv",	EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1369   { "hw_ldl_l/p",	EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1370   { "hw_ldl_l/p",	EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM },
1371   { "hw_ldl_l/pa",	EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1372   { "hw_ldl_l/pav",	EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1373   { "hw_ldl_l/paw",	EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1374   { "hw_ldl_l/pawv",	EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1375   { "hw_ldl_l/pv",	EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1376   { "hw_ldl_l/pw",	EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1377   { "hw_ldl_l/pwv",	EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1378   { "hw_ldl_l/v",	EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1379   { "hw_ldl_l/w",	EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1380   { "hw_ldl_l/wv",	EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1381   { "hw_ldq",		EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1382   { "hw_ldq",		EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1383   { "hw_ldq",		EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM },
1384   { "hw_ldq/a",		EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1385   { "hw_ldq/a",		EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1386   { "hw_ldq/a",		EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM },
1387   { "hw_ldq/al",	EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1388   { "hw_ldq/ar",	EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1389   { "hw_ldq/av",	EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1390   { "hw_ldq/avl",	EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1391   { "hw_ldq/aw",	EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1392   { "hw_ldq/awl",	EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1393   { "hw_ldq/awv",	EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1394   { "hw_ldq/awvl",	EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1395   { "hw_ldq/l",		EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1396   { "hw_ldq/p",		EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1397   { "hw_ldq/p",		EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1398   { "hw_ldq/p",		EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM },
1399   { "hw_ldq/pa",	EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1400   { "hw_ldq/pa",	EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1401   { "hw_ldq/pal",	EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1402   { "hw_ldq/par",	EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1403   { "hw_ldq/pav",	EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1404   { "hw_ldq/pavl",	EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1405   { "hw_ldq/paw",	EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1406   { "hw_ldq/pawl",	EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1407   { "hw_ldq/pawv",	EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1408   { "hw_ldq/pawvl",	EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1409   { "hw_ldq/pl",	EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1410   { "hw_ldq/pr",	EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1411   { "hw_ldq/pv",	EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1412   { "hw_ldq/pvl",	EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1413   { "hw_ldq/pw",	EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1414   { "hw_ldq/pwl",	EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1415   { "hw_ldq/pwv",	EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1416   { "hw_ldq/pwvl",	EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1417   { "hw_ldq/r",		EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1418   { "hw_ldq/v",		EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1419   { "hw_ldq/v",		EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM },
1420   { "hw_ldq/vl",	EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1421   { "hw_ldq/w",		EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1422   { "hw_ldq/w",		EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM },
1423   { "hw_ldq/wa",	EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM },
1424   { "hw_ldq/wl",	EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1425   { "hw_ldq/wv",	EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1426   { "hw_ldq/wvl",	EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1427   { "hw_ldq_l",		EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1428   { "hw_ldq_l/a",	EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1429   { "hw_ldq_l/av",	EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1430   { "hw_ldq_l/aw",	EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1431   { "hw_ldq_l/awv",	EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1432   { "hw_ldq_l/p",	EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1433   { "hw_ldq_l/p",	EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM },
1434   { "hw_ldq_l/pa",	EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1435   { "hw_ldq_l/pav",	EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1436   { "hw_ldq_l/paw",	EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1437   { "hw_ldq_l/pawv",	EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1438   { "hw_ldq_l/pv",	EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1439   { "hw_ldq_l/pw",	EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1440   { "hw_ldq_l/pwv",	EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1441   { "hw_ldq_l/v",	EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1442   { "hw_ldq_l/w",	EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1443   { "hw_ldq_l/wv",	EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1444   { "hw_ld",		EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1445   { "hw_ld",		EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1446   { "hw_ld/a",		EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1447   { "hw_ld/a",		EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1448   { "hw_ld/al",		EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1449   { "hw_ld/aq",		EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1450   { "hw_ld/aq",		EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1451   { "hw_ld/aql",	EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1452   { "hw_ld/aqv",	EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1453   { "hw_ld/aqvl",	EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1454   { "hw_ld/ar",		EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1455   { "hw_ld/arq",	EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1456   { "hw_ld/av",		EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1457   { "hw_ld/avl",	EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1458   { "hw_ld/aw",		EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1459   { "hw_ld/awl",	EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1460   { "hw_ld/awq",	EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1461   { "hw_ld/awql",	EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1462   { "hw_ld/awqv",	EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1463   { "hw_ld/awqvl",	EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1464   { "hw_ld/awv",	EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1465   { "hw_ld/awvl",	EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1466   { "hw_ld/l",		EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1467   { "hw_ld/p",		EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1468   { "hw_ld/p",		EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1469   { "hw_ld/pa",		EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1470   { "hw_ld/pa",		EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1471   { "hw_ld/pal",	EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1472   { "hw_ld/paq",	EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1473   { "hw_ld/paq",	EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1474   { "hw_ld/paql",	EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1475   { "hw_ld/paqv",	EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1476   { "hw_ld/paqvl",	EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1477   { "hw_ld/par",	EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1478   { "hw_ld/parq",	EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1479   { "hw_ld/pav",	EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1480   { "hw_ld/pavl",	EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1481   { "hw_ld/paw",	EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1482   { "hw_ld/pawl",	EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1483   { "hw_ld/pawq",	EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1484   { "hw_ld/pawql",	EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1485   { "hw_ld/pawqv",	EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1486   { "hw_ld/pawqvl",	EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1487   { "hw_ld/pawv",	EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1488   { "hw_ld/pawvl",	EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1489   { "hw_ld/pl",		EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1490   { "hw_ld/pq",		EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1491   { "hw_ld/pq",		EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1492   { "hw_ld/pql",	EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1493   { "hw_ld/pqv",	EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1494   { "hw_ld/pqvl",	EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1495   { "hw_ld/pr",		EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1496   { "hw_ld/prq",	EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1497   { "hw_ld/pv",		EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1498   { "hw_ld/pvl",	EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1499   { "hw_ld/pw",		EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1500   { "hw_ld/pwl",	EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1501   { "hw_ld/pwq",	EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1502   { "hw_ld/pwql",	EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1503   { "hw_ld/pwqv",	EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1504   { "hw_ld/pwqvl",	EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1505   { "hw_ld/pwv",	EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1506   { "hw_ld/pwvl",	EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1507   { "hw_ld/q",		EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1508   { "hw_ld/q",		EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1509   { "hw_ld/ql",		EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1510   { "hw_ld/qv",		EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1511   { "hw_ld/qvl",	EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1512   { "hw_ld/r",		EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1513   { "hw_ld/rq",		EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1514   { "hw_ld/v",		EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1515   { "hw_ld/vl",		EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1516   { "hw_ld/w",		EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1517   { "hw_ld/wl",		EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1518   { "hw_ld/wq",		EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1519   { "hw_ld/wql",	EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1520   { "hw_ld/wqv",	EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1521   { "hw_ld/wqvl",	EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1522   { "hw_ld/wv",		EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1523   { "hw_ld/wvl",	EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1524   { "pal1b",		PCD(0x1B), BASE, ARG_PCD },
1525 
1526   { "sextb",		OPR(0x1C, 0x00), BWX, ARG_OPRZ1 },
1527   { "sextw",		OPR(0x1C, 0x01), BWX, ARG_OPRZ1 },
1528   { "ctpop",		OPR(0x1C, 0x30), CIX, ARG_OPRZ1 },
1529   { "perr",		OPR(0x1C, 0x31), MAX, ARG_OPR },
1530   { "ctlz",		OPR(0x1C, 0x32), CIX, ARG_OPRZ1 },
1531   { "cttz",		OPR(0x1C, 0x33), CIX, ARG_OPRZ1 },
1532   { "unpkbw",		OPR(0x1C, 0x34), MAX, ARG_OPRZ1 },
1533   { "unpkbl",		OPR(0x1C, 0x35), MAX, ARG_OPRZ1 },
1534   { "pkwb",		OPR(0x1C, 0x36), MAX, ARG_OPRZ1 },
1535   { "pklb",		OPR(0x1C, 0x37), MAX, ARG_OPRZ1 },
1536   { "minsb8", 		OPR(0x1C, 0x38), MAX, ARG_OPR },
1537   { "minsb8", 		OPRL(0x1C, 0x38), MAX, ARG_OPRL },
1538   { "minsw4", 		OPR(0x1C, 0x39), MAX, ARG_OPR },
1539   { "minsw4", 		OPRL(0x1C, 0x39), MAX, ARG_OPRL },
1540   { "minub8", 		OPR(0x1C, 0x3A), MAX, ARG_OPR },
1541   { "minub8", 		OPRL(0x1C, 0x3A), MAX, ARG_OPRL },
1542   { "minuw4", 		OPR(0x1C, 0x3B), MAX, ARG_OPR },
1543   { "minuw4", 		OPRL(0x1C, 0x3B), MAX, ARG_OPRL },
1544   { "maxub8",		OPR(0x1C, 0x3C), MAX, ARG_OPR },
1545   { "maxub8",		OPRL(0x1C, 0x3C), MAX, ARG_OPRL },
1546   { "maxuw4",		OPR(0x1C, 0x3D), MAX, ARG_OPR },
1547   { "maxuw4",		OPRL(0x1C, 0x3D), MAX, ARG_OPRL },
1548   { "maxsb8",		OPR(0x1C, 0x3E), MAX, ARG_OPR },
1549   { "maxsb8",		OPRL(0x1C, 0x3E), MAX, ARG_OPRL },
1550   { "maxsw4",		OPR(0x1C, 0x3F), MAX, ARG_OPR },
1551   { "maxsw4",		OPRL(0x1C, 0x3F), MAX, ARG_OPRL },
1552   { "ftoit",		FP(0x1C, 0x70), CIX, { FA, ZB, RC } },
1553   { "ftois",		FP(0x1C, 0x78), CIX, { FA, ZB, RC } },
1554 
1555   { "hw_mtpr",		OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1556   { "hw_mtpr",		OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1557   { "hw_mtpr",		OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1558   { "hw_mtpr/i", 	OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
1559   { "hw_mtpr/a", 	OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
1560   { "hw_mtpr/ai",	OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
1561   { "hw_mtpr/p", 	OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
1562   { "hw_mtpr/pi",	OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
1563   { "hw_mtpr/pa",	OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
1564   { "hw_mtpr/pai",	OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
1565   { "pal1d",		PCD(0x1D), BASE, ARG_PCD },
1566 
1567   { "hw_rei",		SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE },
1568   { "hw_rei_stall",	SPCD(0x1E,0x3FFC000), EV5, ARG_NONE },
1569   { "hw_jmp", 		EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1570   { "hw_jsr", 		EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1571   { "hw_ret", 		EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1572   { "hw_jcr", 		EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1573   { "hw_coroutine",	EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1574   { "hw_jmp/stall",	EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1575   { "hw_jsr/stall", 	EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1576   { "hw_ret/stall",	EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1577   { "hw_jcr/stall", 	EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1578   { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1579   { "pal1e",		PCD(0x1E), BASE, ARG_PCD },
1580 
1581   { "hw_stl",		EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1582   { "hw_stl",		EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1583   { "hw_stl",		EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */
1584   { "hw_stl/a",		EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1585   { "hw_stl/a",		EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1586   { "hw_stl/a",		EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM },
1587   { "hw_stl/ac",	EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1588   { "hw_stl/ar",	EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1589   { "hw_stl/av",	EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1590   { "hw_stl/avc",	EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1591   { "hw_stl/c",		EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1592   { "hw_stl/p",		EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1593   { "hw_stl/p",		EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1594   { "hw_stl/p",		EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM },
1595   { "hw_stl/pa",	EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1596   { "hw_stl/pa",	EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1597   { "hw_stl/pac",	EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1598   { "hw_stl/pav",	EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1599   { "hw_stl/pavc",	EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1600   { "hw_stl/pc",	EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1601   { "hw_stl/pr",	EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1602   { "hw_stl/pv",	EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1603   { "hw_stl/pvc",	EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1604   { "hw_stl/r",		EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1605   { "hw_stl/v",		EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1606   { "hw_stl/vc",	EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1607   { "hw_stl_c",		EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1608   { "hw_stl_c/a",	EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1609   { "hw_stl_c/av",	EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1610   { "hw_stl_c/p",	EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1611   { "hw_stl_c/p",	EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM },
1612   { "hw_stl_c/pa",	EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1613   { "hw_stl_c/pav",	EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1614   { "hw_stl_c/pv",	EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1615   { "hw_stl_c/v",	EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1616   { "hw_stq",		EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1617   { "hw_stq",		EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1618   { "hw_stq",		EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */
1619   { "hw_stq/a",		EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1620   { "hw_stq/a",		EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1621   { "hw_stq/a",		EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM },
1622   { "hw_stq/ac",	EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1623   { "hw_stq/ar",	EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1624   { "hw_stq/av",	EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1625   { "hw_stq/avc",	EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1626   { "hw_stq/c",		EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1627   { "hw_stq/p",		EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1628   { "hw_stq/p",		EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1629   { "hw_stq/p",		EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM },
1630   { "hw_stq/pa",	EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1631   { "hw_stq/pa",	EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1632   { "hw_stq/pac",	EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1633   { "hw_stq/par",	EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1634   { "hw_stq/par",	EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1635   { "hw_stq/pav",	EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1636   { "hw_stq/pavc",	EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1637   { "hw_stq/pc",	EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1638   { "hw_stq/pr",	EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1639   { "hw_stq/pv",	EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1640   { "hw_stq/pvc",	EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1641   { "hw_stq/r",		EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
1642   { "hw_stq/v",		EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1643   { "hw_stq/vc",	EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1644   { "hw_stq_c",		EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1645   { "hw_stq_c/a",	EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1646   { "hw_stq_c/av",	EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1647   { "hw_stq_c/p",	EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1648   { "hw_stq_c/p",	EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM },
1649   { "hw_stq_c/pa",	EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1650   { "hw_stq_c/pav",	EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1651   { "hw_stq_c/pv",	EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1652   { "hw_stq_c/v",	EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1653   { "hw_st",		EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1654   { "hw_st",		EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1655   { "hw_st/a",		EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1656   { "hw_st/a",		EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1657   { "hw_st/ac",		EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1658   { "hw_st/aq",		EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1659   { "hw_st/aq",		EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1660   { "hw_st/aqc",	EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1661   { "hw_st/aqv",	EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1662   { "hw_st/aqvc",	EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1663   { "hw_st/ar",		EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1664   { "hw_st/arq",	EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1665   { "hw_st/av",		EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1666   { "hw_st/avc",	EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1667   { "hw_st/c",		EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1668   { "hw_st/p",		EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1669   { "hw_st/p",		EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1670   { "hw_st/pa",		EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1671   { "hw_st/pa",		EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1672   { "hw_st/pac",	EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1673   { "hw_st/paq",	EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1674   { "hw_st/paq",	EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1675   { "hw_st/paqc",	EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1676   { "hw_st/paqv",	EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1677   { "hw_st/paqvc",	EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1678   { "hw_st/par",	EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1679   { "hw_st/parq",	EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1680   { "hw_st/pav",	EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1681   { "hw_st/pavc",	EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1682   { "hw_st/pc",		EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1683   { "hw_st/pq",		EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1684   { "hw_st/pq",		EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1685   { "hw_st/pqc",	EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1686   { "hw_st/pqv",	EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1687   { "hw_st/pqvc",	EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1688   { "hw_st/pr",		EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1689   { "hw_st/prq",	EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1690   { "hw_st/pv",		EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1691   { "hw_st/pvc",	EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1692   { "hw_st/q",		EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1693   { "hw_st/q",		EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1694   { "hw_st/qc",		EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1695   { "hw_st/qv",		EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1696   { "hw_st/qvc",	EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1697   { "hw_st/r",		EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1698   { "hw_st/v",		EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1699   { "hw_st/vc",		EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1700   { "pal1f",		PCD(0x1F), BASE, ARG_PCD },
1701 
1702   { "ldf",		MEM(0x20), BASE, ARG_FMEM },
1703   { "ldg",		MEM(0x21), BASE, ARG_FMEM },
1704   { "lds",		MEM(0x22), BASE, ARG_FMEM },
1705   { "ldt",		MEM(0x23), BASE, ARG_FMEM },
1706   { "stf",		MEM(0x24), BASE, ARG_FMEM },
1707   { "stg",		MEM(0x25), BASE, ARG_FMEM },
1708   { "sts",		MEM(0x26), BASE, ARG_FMEM },
1709   { "stt",		MEM(0x27), BASE, ARG_FMEM },
1710 
1711   { "ldl",		MEM(0x28), BASE, ARG_MEM },
1712   { "ldq",		MEM(0x29), BASE, ARG_MEM },
1713   { "ldl_l",		MEM(0x2A), BASE, ARG_MEM },
1714   { "ldq_l",		MEM(0x2B), BASE, ARG_MEM },
1715   { "stl",		MEM(0x2C), BASE, ARG_MEM },
1716   { "stq",		MEM(0x2D), BASE, ARG_MEM },
1717   { "stl_c",		MEM(0x2E), BASE, ARG_MEM },
1718   { "stq_c",		MEM(0x2F), BASE, ARG_MEM },
1719 
1720   { "br",		BRA(0x30), BASE, { ZA, BDISP } },	/* pseudo */
1721   { "br",		BRA(0x30), BASE, ARG_BRA },
1722   { "fbeq",		BRA(0x31), BASE, ARG_FBRA },
1723   { "fblt",		BRA(0x32), BASE, ARG_FBRA },
1724   { "fble",		BRA(0x33), BASE, ARG_FBRA },
1725   { "bsr",		BRA(0x34), BASE, ARG_BRA },
1726   { "fbne",		BRA(0x35), BASE, ARG_FBRA },
1727   { "fbge",		BRA(0x36), BASE, ARG_FBRA },
1728   { "fbgt",		BRA(0x37), BASE, ARG_FBRA },
1729   { "blbc",		BRA(0x38), BASE, ARG_BRA },
1730   { "beq",		BRA(0x39), BASE, ARG_BRA },
1731   { "blt",		BRA(0x3A), BASE, ARG_BRA },
1732   { "ble",		BRA(0x3B), BASE, ARG_BRA },
1733   { "blbs",		BRA(0x3C), BASE, ARG_BRA },
1734   { "bne",		BRA(0x3D), BASE, ARG_BRA },
1735   { "bge",		BRA(0x3E), BASE, ARG_BRA },
1736   { "bgt",		BRA(0x3F), BASE, ARG_BRA },
1737 };
1738 
1739 const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);
1740 
1741 /* OSF register names.  */
1742 
1743 static const char * const osf_regnames[64] = {
1744   "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
1745   "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
1746   "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
1747   "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
1748   "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
1749   "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1750   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1751   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
1752 };
1753 
1754 /* VMS register names.  */
1755 
1756 static const char * const vms_regnames[64] = {
1757   "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
1758   "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
1759   "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
1760   "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ",
1761   "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
1762   "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
1763   "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
1764   "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ"
1765 };
1766 
1767 /* Disassemble Alpha instructions.  */
1768 
1769 int
print_insn_alpha(bfd_vma memaddr,struct disassemble_info * info)1770 print_insn_alpha (bfd_vma memaddr, struct disassemble_info *info)
1771 {
1772   static const struct alpha_opcode *opcode_index[AXP_NOPS+1];
1773   const char * const * regnames;
1774   const struct alpha_opcode *opcode, *opcode_end;
1775   const unsigned char *opindex;
1776   unsigned insn, op, isa_mask;
1777   int need_comma;
1778 
1779   /* Initialize the majorop table the first time through */
1780   if (!opcode_index[0])
1781     {
1782       opcode = alpha_opcodes;
1783       opcode_end = opcode + alpha_num_opcodes;
1784 
1785       for (op = 0; op < AXP_NOPS; ++op)
1786 	{
1787 	  opcode_index[op] = opcode;
1788 	  while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
1789 	    ++opcode;
1790 	}
1791       opcode_index[op] = opcode;
1792     }
1793 
1794   if (info->flavour == bfd_target_evax_flavour)
1795     regnames = vms_regnames;
1796   else
1797     regnames = osf_regnames;
1798 
1799   isa_mask = AXP_OPCODE_NOPAL;
1800   switch (info->mach)
1801     {
1802     case bfd_mach_alpha_ev4:
1803       isa_mask |= AXP_OPCODE_EV4;
1804       break;
1805     case bfd_mach_alpha_ev5:
1806       isa_mask |= AXP_OPCODE_EV5;
1807       break;
1808     case bfd_mach_alpha_ev6:
1809       isa_mask |= AXP_OPCODE_EV6;
1810       break;
1811     }
1812 
1813   /* Read the insn into a host word */
1814   {
1815     bfd_byte buffer[4];
1816     int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
1817     if (status != 0)
1818       {
1819 	(*info->memory_error_func) (status, memaddr, info);
1820 	return -1;
1821       }
1822     insn = bfd_getl32 (buffer);
1823   }
1824 
1825   /* Get the major opcode of the instruction.  */
1826   op = AXP_OP (insn);
1827 
1828   /* Find the first match in the opcode table.  */
1829   opcode_end = opcode_index[op + 1];
1830   for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
1831     {
1832       if ((insn ^ opcode->opcode) & opcode->mask)
1833 	continue;
1834 
1835       if (!(opcode->flags & isa_mask))
1836 	continue;
1837 
1838       /* Make two passes over the operands.  First see if any of them
1839 	 have extraction functions, and, if they do, make sure the
1840 	 instruction is valid.  */
1841       {
1842 	int invalid = 0;
1843 	for (opindex = opcode->operands; *opindex != 0; opindex++)
1844 	  {
1845 	    const struct alpha_operand *operand = alpha_operands + *opindex;
1846 	    if (operand->extract)
1847 	      (*operand->extract) (insn, &invalid);
1848 	  }
1849 	if (invalid)
1850 	  continue;
1851       }
1852 
1853       /* The instruction is valid.  */
1854       goto found;
1855     }
1856 
1857   /* No instruction found */
1858   (*info->fprintf_func) (info->stream, ".long %#08x", insn);
1859 
1860   return 4;
1861 
1862 found:
1863   (*info->fprintf_func) (info->stream, "%s", opcode->name);
1864   if (opcode->operands[0] != 0)
1865     (*info->fprintf_func) (info->stream, "\t");
1866 
1867   /* Now extract and print the operands.  */
1868   need_comma = 0;
1869   for (opindex = opcode->operands; *opindex != 0; opindex++)
1870     {
1871       const struct alpha_operand *operand = alpha_operands + *opindex;
1872       int value;
1873 
1874       /* Operands that are marked FAKE are simply ignored.  We
1875 	 already made sure that the extract function considered
1876 	 the instruction to be valid.  */
1877       if ((operand->flags & AXP_OPERAND_FAKE) != 0)
1878 	continue;
1879 
1880       /* Extract the value from the instruction.  */
1881       if (operand->extract)
1882 	value = (*operand->extract) (insn, (int *) NULL);
1883       else
1884 	{
1885 	  value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
1886 	  if (operand->flags & AXP_OPERAND_SIGNED)
1887 	    {
1888 	      int signbit = 1 << (operand->bits - 1);
1889 	      value = (value ^ signbit) - signbit;
1890 	    }
1891 	}
1892 
1893       if (need_comma &&
1894 	  ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA))
1895 	   != AXP_OPERAND_PARENS))
1896 	{
1897 	  (*info->fprintf_func) (info->stream, ",");
1898 	}
1899       if (operand->flags & AXP_OPERAND_PARENS)
1900 	(*info->fprintf_func) (info->stream, "(");
1901 
1902       /* Print the operand as directed by the flags.  */
1903       if (operand->flags & AXP_OPERAND_IR)
1904 	(*info->fprintf_func) (info->stream, "%s", regnames[value]);
1905       else if (operand->flags & AXP_OPERAND_FPR)
1906 	(*info->fprintf_func) (info->stream, "%s", regnames[value + 32]);
1907       else if (operand->flags & AXP_OPERAND_RELATIVE)
1908 	(*info->print_address_func) (memaddr + 4 + value, info);
1909       else if (operand->flags & AXP_OPERAND_SIGNED)
1910 	(*info->fprintf_func) (info->stream, "%d", value);
1911       else
1912 	(*info->fprintf_func) (info->stream, "%#x", value);
1913 
1914       if (operand->flags & AXP_OPERAND_PARENS)
1915 	(*info->fprintf_func) (info->stream, ")");
1916       need_comma = 1;
1917     }
1918 
1919   return 4;
1920 }
1921