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Searched refs:irq (Results 1 – 25 of 208) sorted by relevance

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/illumos-kvm-cmd/hw/
H A Darm_gic.c59 #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled argument
66 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 argument
67 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 argument
68 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model argument
74 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger argument
76 (((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32])
80 #define GIC_TARGET(irq) s->irq_target[irq] argument
116 int irq; in gic_update() local
130 for (irq = 0; irq < GIC_NIRQ; irq++) { in gic_update()
176 GIC_SET_PENDING(irq, GIC_TARGET(irq)); in gic_set_irq()
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H A Dirq.c33 void qemu_set_irq(qemu_irq irq, int level) in qemu_set_irq() argument
35 if (!irq) in qemu_set_irq()
38 irq->handler(irq->opaque, irq->n, level); in qemu_set_irq()
67 struct IRQState *irq = opaque; in qemu_notirq() local
69 irq->handler(irq->opaque, irq->n, !level); in qemu_notirq()
72 qemu_irq qemu_irq_invert(qemu_irq irq) in qemu_irq_invert() argument
75 qemu_irq_raise(irq); in qemu_irq_invert()
76 return qemu_allocate_irqs(qemu_notirq, irq, 1)[0]; in qemu_irq_invert()
H A Dmips_int.c27 static void cpu_mips_irq_request(void *opaque, int irq, int level) in cpu_mips_irq_request() argument
31 if (irq < 0 || irq > 7) in cpu_mips_irq_request()
35 env->CP0_Cause |= 1 << (irq + CP0Ca_IP); in cpu_mips_irq_request()
37 env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); in cpu_mips_irq_request()
54 env->irq[i] = qi[i]; in cpu_mips_irq_init_cpu()
58 void cpu_mips_soft_irq(CPUState *env, int irq, int level) in cpu_mips_soft_irq() argument
60 if (irq < 0 || irq > 2) { in cpu_mips_soft_irq()
64 qemu_set_irq(env->irq[irq], level); in cpu_mips_soft_irq()
H A Darmv7m_nvic.c92 if (irq >= 16) in armv7m_nvic_set_pending()
93 irq += 16; in armv7m_nvic_set_pending()
101 uint32_t irq; in armv7m_nvic_acknowledge_irq() local
104 if (irq == 1023) in armv7m_nvic_acknowledge_irq()
106 if (irq >= 32) in armv7m_nvic_acknowledge_irq()
107 irq -= 16; in armv7m_nvic_acknowledge_irq()
108 return irq; in armv7m_nvic_acknowledge_irq()
114 if (irq >= 16) in armv7m_nvic_complete_irq()
115 irq += 16; in armv7m_nvic_complete_irq()
123 int irq; in nvic_readl() local
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H A Di8259.c87 mask = 1 << irq; in pic_set_irq1()
153 int irq2, irq; in pic_update_irq() local
164 if (irq >= 0) { in pic_update_irq()
201 irq_count[irq]++; in i8259_set_irq()
210 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); in i8259_set_irq()
235 int irq, irq2, intno; in pic_read_irq() local
238 if (irq >= 0) { in pic_read_irq()
252 if (irq == 2) { in pic_read_irq()
262 irq = irq2 + 8; in pic_read_irq()
269 irq = 7; in pic_read_irq()
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H A Dirq.h10 void qemu_set_irq(qemu_irq irq, int level);
12 static inline void qemu_irq_raise(qemu_irq irq) in qemu_irq_raise() argument
14 qemu_set_irq(irq, 1); in qemu_irq_raise()
17 static inline void qemu_irq_lower(qemu_irq irq) in qemu_irq_lower() argument
19 qemu_set_irq(irq, 0); in qemu_irq_lower()
22 static inline void qemu_irq_pulse(qemu_irq irq) in qemu_irq_pulse() argument
24 qemu_set_irq(irq, 1); in qemu_irq_pulse()
25 qemu_set_irq(irq, 0); in qemu_irq_pulse()
33 qemu_irq qemu_irq_invert(qemu_irq irq);
H A Domap_uart.c32 qemu_irq irq; member
53 qemu_irq irq, omap_clk fclk, omap_clk iclk, in omap_uart_init() argument
62 s->irq = irq; in omap_uart_init()
64 s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, in omap_uart_init()
68 s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, in omap_uart_init()
165 qemu_irq irq, omap_clk fclk, omap_clk iclk, in omap2_uart_init() argument
170 struct omap_uart_s *s = omap_uart_init(base, irq, in omap2_uart_init()
186 s->serial = serial_mm_init(s->base, 2, s->irq, in omap_uart_attach()
191 s->serial = serial_mm_init(s->base, 2, s->irq, in omap_uart_attach()
H A Dpc.h13 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
16 qemu_irq irq, int baudbase,
26 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverStat…
32 void pic_set_irq(int irq, int level);
33 void pic_set_irq_new(void *opaque, int irq, int level);
58 PITState *pit_init(int base, qemu_irq irq);
67 PITState *kvm_pit_init(int base, qemu_irq irq);
91 void pc_register_ferr_irq(qemu_irq irq);
92 void pc_cmos_set_s3_resume(void *opaque, int irq, int level);
93 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
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H A Darm_timer.c30 qemu_irq irq; member
39 qemu_irq_raise(s->irq); in arm_timer_update()
41 qemu_irq_lower(s->irq); in arm_timer_update()
190 qemu_irq irq; member
198 s->level[irq] = level; in sp804_set_irq()
264 sysbus_init_irq(dev, &s->irq); in sp804_init()
269 s->timer[0]->irq = qi[0]; in sp804_init()
270 s->timer[1]->irq = qi[1]; in sp804_init()
338 sysbus_init_irq(dev, &s->timer[0]->irq); in icp_pit_init()
339 sysbus_init_irq(dev, &s->timer[1]->irq); in icp_pit_init()
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H A Darm11mpcore.c35 static void mpcore_rirq_set_irq(void *opaque, int irq, int level) in mpcore_rirq_set_irq() argument
41 qemu_set_irq(s->rvic[i][irq], level); in mpcore_rirq_set_irq()
43 if (irq < 32) { in mpcore_rirq_set_irq()
44 irq = mpcore_irq_map[irq]; in mpcore_rirq_set_irq()
45 if (irq >= 0) { in mpcore_rirq_set_irq()
46 qemu_set_irq(s->cpuic[irq], level); in mpcore_rirq_set_irq()
H A Dxilinx.h6 xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr) in xilinx_intc_create() argument
14 sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); in xilinx_intc_create()
20 xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int nr, int freq) in xilinx_timer_create() argument
29 sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); in xilinx_timer_create()
35 xilinx_ethlite_create(NICInfo *nd, target_phys_addr_t base, qemu_irq irq, in xilinx_ethlite_create() argument
48 sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); in xilinx_ethlite_create()
H A Detraxfs_pic.c112 static void nmi_handler(void *opaque, int irq, int level) in nmi_handler() argument
117 mask = 1 << irq; in nmi_handler()
126 static void irq_handler(void *opaque, int irq, int level) in irq_handler() argument
130 if (irq >= 30) in irq_handler()
131 return nmi_handler(opaque, irq, level); in irq_handler()
133 irq -= 1; in irq_handler()
134 fs->regs[R_R_VECT] &= ~(1 << irq); in irq_handler()
135 fs->regs[R_R_VECT] |= (!!level << irq); in irq_handler()
H A Dpxa2xx_pcmcia.c18 qemu_irq irq; member
127 if (!s->irq) in pxa2xx_pcmcia_set_irq()
130 qemu_set_irq(s->irq, level); in pxa2xx_pcmcia_set_irq()
162 s->slot.irq = qemu_allocate_irqs(pxa2xx_pcmcia_set_irq, s, 1)[0]; in pxa2xx_pcmcia_init()
201 if (s->irq) in pxa2xx_pcmcia_dettach()
202 qemu_irq_lower(s->irq); in pxa2xx_pcmcia_dettach()
210 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq) in pxa2xx_pcmcia_set_irq_cb() argument
213 s->irq = irq; in pxa2xx_pcmcia_set_irq_cb()
H A Dpxa2xx_pic.c70 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level) in pxa2xx_pic_set_irq() argument
73 int int_set = (irq >= 32); in pxa2xx_pic_set_irq()
74 irq &= 31; in pxa2xx_pic_set_irq()
77 s->int_pending[int_set] |= 1 << irq; in pxa2xx_pic_set_irq()
79 s->int_pending[int_set] &= ~(1 << irq); in pxa2xx_pic_set_irq()
85 int i, int_set, irq; in pxa2xx_pic_highest() local
93 irq = s->priority[i] & 0x3f; in pxa2xx_pic_highest()
96 bit = 1 << (irq & 31); in pxa2xx_pic_highest()
97 int_set = (irq >= 32); in pxa2xx_pic_highest()
102 ichp |= (1 << 15) | irq; in pxa2xx_pic_highest()
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H A Dmcf5206.c20 qemu_irq irq; member
37 qemu_irq_raise(s->irq); in m5206_timer_update()
39 qemu_irq_lower(s->irq); in m5206_timer_update()
138 s->irq = irq; in m5206_timer_init()
192 int irq; in m5206_mbar_update() local
196 irq = m5206_find_pending_irq(s); in m5206_mbar_update()
197 if (irq) { in m5206_mbar_update()
199 tmp = s->icr[irq]; in m5206_mbar_update()
205 switch (irq) { in m5206_mbar_update()
233 s->ipr |= 1 << irq; in m5206_mbar_set_irq()
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H A Dpxa.h80 qemu_irq irq);
82 qemu_irq irq);
88 qemu_irq irq);
95 BlockDriverState *bd, qemu_irq irq, void *dma);
104 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
113 qemu_irq irq);
120 qemu_irq irq, uint32_t page_size);
186 qemu_irq irq; member
H A Domap2.c34 qemu_irq irq; member
595 s->irq = irq; in omap_eac_init()
611 qemu_irq irq; member
627 qemu_set_irq(s->irq, s->irqst & s->irqen); in omap_sti_interrupt_update()
781 s->irq = irq; in omap_sti_init()
993 qemu_irq irq[3]; member
1794 s->irq[0] = mpu_int; in omap_prcm_init()
1795 s->irq[1] = dsp_int; in omap_prcm_init()
1796 s->irq[2] = iva_int; in omap_prcm_init()
2397 s->irq[0][OMAP_INT_24XX_MMC_IRQ], in omap2420_mpu_init()
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H A Detraxfs.c56 qemu_irq irq[30], nmi[2], *cpu_irq; in bareetraxfs_init() local
99 irq[i] = qdev_get_gpio_in(dev, i); in bareetraxfs_init()
107 etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1); in bareetraxfs_init()
124 sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL); in bareetraxfs_init()
125 sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL); in bareetraxfs_init()
129 irq[0x14 + i]); in bareetraxfs_init()
H A Ddevices.h27 void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
45 void *retu_init(qemu_irq irq, int vilma);
46 void *tahvo_init(qemu_irq irq, int betty);
60 TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq);
67 void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq,
H A Dstellaris_input.c14 qemu_irq irq; member
43 qemu_set_irq(s->buttons[i].irq, down); in stellaris_gamepad_put_key()
76 void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode) in stellaris_gamepad_init() argument
84 s->buttons[i].irq = irq[i]; in stellaris_gamepad_init()
H A Dr2d.c235 qemu_irq *irq; in r2d_init() local
257 irq = r2d_fpga_init(0x04000000, sh7750_irl(s)); in r2d_init()
258 sysbus_create_varargs("sh_pci", 0x1e200000, irq[PCI_INTA], irq[PCI_INTB], in r2d_init()
259 irq[PCI_INTC], irq[PCI_INTD], NULL); in r2d_init()
261 sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]); in r2d_init()
265 mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1, in r2d_init()
H A Dversatilepb.c30 int irq; member
50 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
66 static void vpb_sic_set_irq(void *opaque, int irq, int level) in vpb_sic_set_irq() argument
70 s->level |= 1u << irq; in vpb_sic_set_irq()
72 s->level &= ~(1u << irq); in vpb_sic_set_irq()
73 if (s->pic_enable & (1u << irq)) in vpb_sic_set_irq()
74 qemu_set_irq(s->parent[irq], level); in vpb_sic_set_irq()
156 s->irq = 31; in vpb_sic_init()
H A Drc4030.c442 uint32_t irq = 0; in update_jazz_irq() local
444 for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) { in update_jazz_irq()
445 if (s->isr_jazz & (1 << irq)) { in update_jazz_irq()
446 printf(" %s", irq_names[irq]); in update_jazz_irq()
447 if (!(s->imr_jazz & (1 << irq))) { in update_jazz_irq()
467 s->isr_jazz |= 1 << irq; in rc4030_irq_jazz_request()
469 s->isr_jazz &= ~(1 << irq); in rc4030_irq_jazz_request()
487 uint32_t irq; in jazzio_readw() local
495 irq = 0; in jazzio_readw()
499 val = (irq + 1) << 2; in jazzio_readw()
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H A Dxilinx_uartlite.c53 qemu_irq irq; member
64 unsigned int irq; in uart_update_irq() local
69 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE); in uart_update_irq()
70 qemu_set_irq(s->irq, irq); in uart_update_irq()
201 sysbus_init_irq(dev, &s->irq); in xilinx_uartlite_init()
H A Domap1.c86 qemu_irq irq; member
259 s->irq = irq; in omap_mpu_timer_init()
383 s->timer.irq = irq; in omap_wd_timer_init()
485 s->timer.irq = irq; in omap_os_timer_init()
1797 qemu_irq irq; member
2823 s->irq = irq[0]; in omap_rtc_init()
2863 int irq; in omap_mcbsp_intr_update() local
2873 irq = 0; in omap_mcbsp_intr_update()
2877 if (irq) in omap_mcbsp_intr_update()
2888 irq = 0; in omap_mcbsp_intr_update()
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