Home
last modified time | relevance | path

Searched refs:insn (Results 1 – 25 of 27) sorted by relevance

12

/illumos-kvm-cmd/target-arm/
H A Dtranslate.c874 val = (insn & 0xf) | ((insn >> 4) & 0xf0); in gen_add_datah_offset()
1292 offset = (insn & 0xff) << ((insn >> 7) & 2); in gen_iwmmxt_address()
2450 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); in cp15_user_ok()
2471 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); in cp15_tls_load_store()
2590 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22) argument
2592 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7) argument
2594 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5) argument
2863 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1); in disas_vfp_insn()
7693 op = ((insn >> 22) & 6) | ((insn >> 7) & 1); in disas_thumb2_insn()
7952 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4); in disas_thumb2_insn()
[all …]
H A Dhelper.c517 int op1 = (insn >> 8) & 0xf; in HELPER()
524 int op1 = (insn >> 8) & 0xf; in HELPER()
1260 int src = (insn >> 16) & 0xf; in HELPER()
1261 int operand = insn & 0xf; in HELPER()
1273 int operand = insn & 0xf; in HELPER()
1317 op1 = (insn >> 21) & 7; in HELPER()
1318 op2 = (insn >> 5) & 7; in HELPER()
1319 crm = insn & 0xf; in HELPER()
1587 op1 = (insn >> 21) & 7; in HELPER()
1588 op2 = (insn >> 5) & 7; in HELPER()
[all …]
/illumos-kvm-cmd/
H A Dhppa-dis.c400 #define get_opcode(insn) (((insn) >> 26) & 0x3f) argument
530 return insn; in hppa_rebuild_insn()
1760 #define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \ argument
1763 #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \ argument
1957 unsigned int insn, i; in print_insn_hppa() local
2135 extract_3 (insn)); in print_insn_hppa()
2300 GET_FIELD (insn, 17, 18), GET_FIELD (insn, 20, 21), in print_insn_hppa()
2301 GET_FIELD (insn, 22, 23), GET_FIELD (insn, 24, 25)); in print_insn_hppa()
2521 if (insn & 0x2) in print_insn_hppa()
2826 return sizeof (insn); in print_insn_hppa()
[all …]
H A Dcris-dis.c1561 insn, in get_opcode_entry()
1601 unsigned int insn, in cris_constraint() argument
1712 retval = (((insn >> 12) & 15) == (insn & 15)); in cris_constraint()
1860 && (insn & 0x400) && (insn & 15) == 15 in bytes_to_skip()
1911 unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15)); in print_flags()
2081 if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL) in print_with_operands()
2221 if (insn & 0x400) in print_with_operands()
2428 if (insn & 0x400) in print_with_operands()
2483 if (insn & 1) in print_with_operands()
2519 tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1); in print_with_operands()
[all …]
H A Darm-dis.c1641 for (insn = coprocessor_opcodes; insn->assembler; insn++) in print_insn_coprocessor()
1647 insn = insn + IWMMXT_INSN_COUNT; in print_insn_coprocessor()
2246 for (insn = neon_opcodes; insn->assembler; insn++) in print_insn_neon()
2248 if ((given & insn->mask) == insn->value) in print_insn_neon()
2687 for (insn = arm_opcodes; insn->assembler; insn++) in print_insn_arm_internal()
2692 insn = insn + IWMMXT_INSN_COUNT; in print_insn_arm_internal()
2694 if ((given & insn->mask) == insn->value in print_insn_arm_internal()
3041 for (insn = thumb_opcodes; insn->assembler; insn++) in print_insn_thumb16()
3042 if ((given & insn->mask) == insn->value) in print_insn_thumb16()
3323 for (insn = thumb32_opcodes; insn->assembler; insn++) in print_insn_thumb32()
[all …]
H A Dalpha-dis.c442 return insn | (((insn >> 21) & 0x1f) << 16); in insert_rba()
449 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) in extract_rba()
461 return insn | ((insn >> 21) & 0x1f); in insert_rca()
468 && ((insn >> 21) & 0x1f) != (insn & 0x1f)) in extract_rca()
480 return insn | (31 << 21); in insert_za()
484 extract_za(unsigned insn, int *invalid) in extract_za() argument
495 return insn | (31 << 16); in insert_zb()
510 return insn | 31; in insert_zc()
1776 unsigned insn, op, isa_mask; in print_insn_alpha() local
1822 insn = bfd_getl32 (buffer); in print_insn_alpha()
[all …]
H A Dsh4-dis.c1248 if (insn == 0x000) in print_insn_ddt()
1253 if ((insn & 0x800) && (insn & 0x3ff)) in print_insn_ddt()
1257 if (((insn & 0xc) == 0 && (insn & 0x2a0)) in print_insn_ddt()
1258 || ((insn & 3) == 0 && (insn & 0x150))) in print_insn_ddt()
1289 (insn >> 6) & 3, in print_insn_ddt()
1312 print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1, in print_insn_ddt()
1315 insn_y = (insn & 3) | ((insn >> 1) & 8); in print_insn_ddt()
1322 print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1, in print_insn_ddt()
1519 unsigned char insn[4]; in print_insn_sh() local
1615 field_b = insn[1] << 8 | insn[0]; in print_insn_sh()
[all …]
H A Dsparc-dis.c2288 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) argument
2290 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) argument
2446 is_delayed_branch (unsigned long insn) in is_delayed_branch() argument
2710 unsigned long insn; in print_insn_sparc() local
2757 insn = getword (buffer); in print_insn_sparc()
2794 if (X_RS1 (insn) != X_RD (insn) in print_insn_sparc()
2798 if (X_RS2 (insn) != X_RD (insn) in print_insn_sparc()
2867 reg (X_RD (insn)); in print_insn_sparc()
3069 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) in print_insn_sparc()
3077 if (X_RD (insn) < 16 || X_RD (insn) > 25) in print_insn_sparc()
[all …]
H A Dppc-dis.c912 return insn | (((insn >> 21) & 0x1f) << 16); in insert_bat()
920 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) in extract_bat()
937 return insn | (((insn >> 16) & 0x1f) << 11); in insert_bba()
945 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) in extract_bba()
976 insn |= 1 << 21; in insert_bdm()
1347 return ((insn >> 6) & 0x1f) | (insn & 0x20); in extract_mb6()
1462 return insn | (((insn >> 21) & 0x1f) << 11); in insert_rbs()
1470 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) in extract_rbs()
1491 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); in extract_sh6()
1511 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); in extract_spr()
[all …]
H A Dia64-dis.c10292 int disent = locate_opcode_ent (insn, type); in ia64_dis_opcode()
10340 return make_ia64_opcode (insn, name, place, in ia64_dis_opcode()
10446 insn = slot[slotnum]; in print_insn_ia64()
10451 idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit)); in print_insn_ia64()
10458 || (insn & 0x3f) == 0) in print_insn_ia64()
10480 value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7) in print_insn_ia64()
10481 | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21) in print_insn_ia64()
10488 | (((insn >> 36) & 0x1) << 20) in print_insn_ia64()
10489 | ((insn >> 6) & 0xfffff); in print_insn_ia64()
10494 value = (((insn >> 13) & 0xfffff) in print_insn_ia64()
[all …]
H A Dcpu-exec.c1009 uint32_t insn = *pc; in cpu_signal_handler() local
1013 switch (insn >> 26) { in cpu_signal_handler()
1038 uint32_t insn; in cpu_signal_handler() local
1058 insn = *(uint32_t *)pc; in cpu_signal_handler()
1059 if ((insn >> 30) == 3) { in cpu_signal_handler()
1060 switch((insn >> 19) & 0x3f) { in cpu_signal_handler()
1239 uint32_t insn = *(uint32_t *)pc; in cpu_signal_handler() local
1243 switch (insn >> 26) { in cpu_signal_handler()
1254 is_write = (insn >> 9) & 1; in cpu_signal_handler()
1258 switch ((insn >> 6) & 15) { in cpu_signal_handler()
H A Dmips-dis.c626 (((insn)->membership & isa) != 0 \
4135 unsigned long insn; in _print_insn_mips() local
4171 int insn;
4195 insn = bfd_getb16 (buffer);
4197 insn = bfd_getl16 (buffer);
4201 if ((insn & 0xf800) == 0xf000)
4204 extend = insn & 0x7ff;
4218 insn = bfd_getb16 (buffer);
4220 insn = bfd_getl16 (buffer);
4223 if ((insn & 0xf800) == 0xf000)
[all …]
H A Dmicroblaze-dis.c613 enum microblaze_instr microblaze_decode_insn (long insn,
1011 microblaze_decode_insn (long insn, in microblaze_decode_insn() argument
1022 op = get_insn_microblaze(insn, &t1, &t2, &t3); in microblaze_decode_insn()
1023 *rd = (insn & RD_MASK) >> RD_LOW; in microblaze_decode_insn()
1024 *ra = (insn & RA_MASK) >> RA_LOW; in microblaze_decode_insn()
1025 *rb = (insn & RB_MASK) >> RB_LOW; in microblaze_decode_insn()
1026 t3 = (insn & IMM_MASK) >> IMM_LOW; in microblaze_decode_insn()
H A Ds390-dis.c246 s390_extract_operand (unsigned char *insn, const struct s390_operand *operand) in s390_extract_operand() argument
252 insn += operand->shift / 8; in s390_extract_operand()
258 val |= (unsigned int) *insn++; in s390_extract_operand()
/illumos-kvm-cmd/target-m68k/
H A Dtranslate.c60 #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7] argument
61 #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7] argument
62 #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7] argument
2542 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); in DISAS_INSN()
2543 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); in DISAS_INSN()
2653 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); in DISAS_INSN()
2673 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); in DISAS_INSN()
2707 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); in DISAS_INSN()
2714 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); in DISAS_INSN()
2722 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); in DISAS_INSN()
[all …]
/illumos-kvm-cmd/target-sparc/
H A Dtranslate.c116 #define IS_IMM (insn & (1<<13))
1289 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); in do_branch()
1330 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); in do_fbranch()
1372 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); in do_branch_reg()
1589 r_asi = gen_get_asi(insn, addr); in gen_ld_asi()
1602 r_asi = gen_get_asi(insn, addr); in gen_st_asi()
1613 r_asi = gen_get_asi(insn, addr); in gen_ldf_asi()
1802 rs1 = GET_FIELD(insn, 13, 17); in get_src1()
1876 insn = ldl_code(dc->pc); in disas_sparc_insn()
1877 opc = GET_FIELD(insn, 0, 1); in disas_sparc_insn()
[all …]
/illumos-kvm-cmd/hw/
H A Dlsi53c895a.c1018 uint32_t insn; in lsi_execute_script() local
1026 insn = read_dword(s, s->dsp); in lsi_execute_script()
1027 if (!insn) { in lsi_execute_script()
1037 s->dcmd = insn >> 24; in lsi_execute_script()
1039 switch (insn >> 30) { in lsi_execute_script()
1046 s->dbc = insn & 0xffffff; in lsi_execute_script()
1050 if (insn & (1 << 29)) { in lsi_execute_script()
1154 opcode = (insn >> 27) & 7; in lsi_execute_script()
1161 id = insn; in lsi_execute_script()
1246 reg = ((insn >> 16) & 0x7f) | (insn & 0x80); in lsi_execute_script()
[all …]
/illumos-kvm-cmd/tests/cris/
H A Dcheck_clrjmp1.s17 ; There was a bug causing this insn to set special register p0
18 ; (byte-clear) to 8 (low 8 bits of location after insn).
25 ; The corresponding bug would cause this insn too, to set p0.
/illumos-kvm-cmd/target-alpha/
H A Dtranslate.c1477 opc = insn >> 26; in translate_one()
1478 ra = (insn >> 21) & 0x1F; in translate_one()
1479 rb = (insn >> 16) & 0x1F; in translate_one()
1480 rc = insn & 0x1F; in translate_one()
1486 lit = (insn >> 13) & 0xFF; in translate_one()
1487 palcode = insn & 0x03FFFFFF; in translate_one()
1491 fn11 = (insn >> 5) & 0x000007FF; in translate_one()
1493 fn7 = (insn >> 5) & 0x0000007F; in translate_one()
1494 fn2 = (insn >> 5) & 0x00000003; in translate_one()
3144 uint32_t insn; in gen_intermediate_code_internal() local
[all …]
/illumos-kvm-cmd/target-mips/
H A Dop_helper.c63 #define HELPER_LD(name, insn, type) \ argument
66 return (type) insn##_raw(addr); \
69 #define HELPER_LD(name, insn, type) \ argument
74 case 0: return (type) insn##_kernel(addr); break; \
75 case 1: return (type) insn##_super(addr); break; \
77 case 2: return (type) insn##_user(addr); break; \
89 #define HELPER_ST(name, insn, type) \ in HELPER_LD() argument
92 insn##_raw(addr, val); \ in HELPER_LD()
95 #define HELPER_ST(name, insn, type) \
100 case 0: insn##_kernel(addr, val); break; \
[all …]
H A Dtranslate.c915 #define OP_LD(insn,fname) \ argument
916 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
931 #define OP_ST(insn,fname) \ argument
932 static inline void op_st_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
945 #define OP_LD_ATOMIC(insn,fname) \ argument
946 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
956 #define OP_LD_ATOMIC(insn,fname) \ argument
957 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
10536 uint16_t insn; in decode_micromips32_opc() local
10542 insn = lduw_code(ctx->pc + 2); in decode_micromips32_opc()
[all …]
/illumos-kvm-cmd/tcg/hppa/
H A Dtcg-target.c151 uint32_t insn = *insn_ptr; in patch_reloc() local
163 insn &= ~0x1ffdu; in patch_reloc()
164 insn |= reassemble_12(pcrel); in patch_reloc()
168 insn &= ~0x1f1ffdu; in patch_reloc()
169 insn |= reassemble_17(pcrel); in patch_reloc()
175 *insn_ptr = insn; in patch_reloc()
/illumos-kvm-cmd/linux-user/
H A Dmain.c610 unsigned int n, insn; in cpu_loop() local
698 get_user_u16(insn, env->regs[15]); in cpu_loop()
699 n = insn & 0xff; in cpu_loop()
703 get_user_u32(insn, env->regs[15]); in cpu_loop()
704 n = (insn & 0xf) | ((insn >> 4) & 0xff0); in cpu_loop()
710 get_user_u16(insn, env->regs[15] - 2); in cpu_loop()
711 n = insn & 0xff; in cpu_loop()
714 get_user_u32(insn, env->regs[15] - 4); in cpu_loop()
715 n = insn & 0xffffff; in cpu_loop()
/illumos-kvm-cmd/target-ppc/
H A Dtranslate_init.c9229 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) in register_insn() argument
9231 if (insn->opc2 != 0xFF) { in register_insn()
9232 if (insn->opc3 != 0xFF) { in register_insn()
9233 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, in register_insn()
9234 insn->opc3, &insn->handler) < 0) in register_insn()
9237 if (register_ind_insn(ppc_opcodes, insn->opc1, in register_insn()
9238 insn->opc2, &insn->handler) < 0) in register_insn()
9242 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) in register_insn()
/illumos-kvm-cmd/tests/
H A Dtest-i386.c459 #define TEST_LOOP(insn) \ argument
466 insn " 1f\n\t" \
471 printf("%-10s ECX=" FMTLX " ZF=%ld r=%d\n", insn, ecx, zf, res); \

Completed in 329 milliseconds

12