Lines Matching refs:op

2450     int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);  in cp15_user_ok()  local
2454 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT))) in cp15_user_ok()
2459 if ((cpm == 5 && op == 4) in cp15_user_ok()
2460 || (cpm == 10 && (op == 4 || op == 5))) in cp15_user_ok()
2471 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); in cp15_tls_load_store() local
2480 switch (op) { in cp15_tls_load_store()
2497 switch (op) { in cp15_tls_load_store()
2646 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; in disas_vfp_insn() local
2863 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1); in disas_vfp_insn()
2865 if (op == 15) { in disas_vfp_insn()
2873 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) { in disas_vfp_insn()
2879 if (op == 15 && in disas_vfp_insn()
2890 if (op == 15 && rn == 15) { in disas_vfp_insn()
2903 if (op == 15 && rn > 3) in disas_vfp_insn()
2938 if (op == 15) { in disas_vfp_insn()
2981 switch (op) { in disas_vfp_insn()
3180 printf ("op:%d\n", op); in disas_vfp_insn()
3185 if (op == 15 && (rn >= 8 && rn <= 11)) in disas_vfp_insn()
3187 else if (op == 15 && dp && ((rn & 0x1c) == 0x18)) in disas_vfp_insn()
3190 else if (op == 15 && rn == 15) in disas_vfp_insn()
3200 if (op == 15 && delta_m == 0) { in disas_vfp_insn()
3214 if (op == 15) { in disas_vfp_insn()
3792 int op; in disas_neon_ls_insn() local
3817 op = (insn >> 8) & 0xf; in disas_neon_ls_insn()
3819 if (op > 10) in disas_neon_ls_insn()
3821 nregs = neon_ls_element_type[op].nregs; in disas_neon_ls_insn()
3822 interleave = neon_ls_element_type[op].interleave; in disas_neon_ls_insn()
3823 spacing = neon_ls_element_type[op].spacing; in disas_neon_ls_insn()
4196 int op; in disas_neon_data_insn() local
4220 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1); in disas_neon_data_insn()
4221 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9 in disas_neon_data_insn()
4222 || op == 10 || op == 11 || op == 16)) { in disas_neon_data_insn()
4227 switch (op) { in disas_neon_data_insn()
4292 switch (op) { in disas_neon_data_insn()
4342 switch (op) { in disas_neon_data_insn()
4598 op = (insn >> 8) & 0xf; in disas_neon_data_insn()
4610 if (op < 8) { in disas_neon_data_insn()
4615 if (op <= 4) in disas_neon_data_insn()
4644 switch (op) { in disas_neon_data_insn()
4685 if (op == 1 || op == 3) { in disas_neon_data_insn()
4689 } else if (op == 4 || (op == 5 && u)) { in disas_neon_data_insn()
4699 switch (op) { in disas_neon_data_insn()
4748 if (op == 1 || op == 3) { in disas_neon_data_insn()
4753 } else if (op == 4 || (op == 5 && u)) { in disas_neon_data_insn()
4757 if (op == 4) in disas_neon_data_insn()
4765 if (op == 4) in disas_neon_data_insn()
4775 if (op == 4) in disas_neon_data_insn()
4793 } else if (op < 10) { in disas_neon_data_insn()
4842 if (op == 8 && !u) { in disas_neon_data_insn()
4845 if (op == 8) in disas_neon_data_insn()
4857 } else if (op == 10) { in disas_neon_data_insn()
4887 } else if (op >= 14) { in disas_neon_data_insn()
4895 if (!(op & 1)) { in disas_neon_data_insn()
4914 op = (insn >> 8) & 0xf; in disas_neon_data_insn()
4918 switch (op) { in disas_neon_data_insn()
4957 if (op & 1 && op < 12) { in disas_neon_data_insn()
4969 if (op == 14 && invert) { in disas_neon_data_insn()
4986 op = (insn >> 8) & 0xf; in disas_neon_data_insn()
5011 prewiden = neon_3reg_wide[op][0]; in disas_neon_data_insn()
5012 src1_wide = neon_3reg_wide[op][1]; in disas_neon_data_insn()
5013 src2_wide = neon_3reg_wide[op][2]; in disas_neon_data_insn()
5015 if (size == 0 && (op == 9 || op == 11 || op == 13)) in disas_neon_data_insn()
5056 switch (op) { in disas_neon_data_insn()
5098 if (op == 5 || op == 13 || (op >= 8 && op <= 11)) { in disas_neon_data_insn()
5100 if (op == 10 || op == 11) { in disas_neon_data_insn()
5104 if (op != 13) { in disas_neon_data_insn()
5108 switch (op) { in disas_neon_data_insn()
5124 } else if (op == 4 || op == 6) { in disas_neon_data_insn()
5170 switch (op) { in disas_neon_data_insn()
5184 if (op == 12) { in disas_neon_data_insn()
5190 } else if (op == 13) { in disas_neon_data_insn()
5196 } else if (op & 1) { in disas_neon_data_insn()
5207 if (op < 8) { in disas_neon_data_insn()
5210 switch (op) { in disas_neon_data_insn()
5237 if (size == 0 && (op == 3 || op == 7 || op == 11)) in disas_neon_data_insn()
5255 if (op == 6 || op == 7) { in disas_neon_data_insn()
5258 if (op != 11) { in disas_neon_data_insn()
5261 switch (op) { in disas_neon_data_insn()
5341 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf); in disas_neon_data_insn()
5343 switch (op) { in disas_neon_data_insn()
5375 gen_neon_widen(cpu_V0, tmp, size, op & 1); in disas_neon_data_insn()
5377 gen_neon_widen(cpu_V1, tmp, size, op & 1); in disas_neon_data_insn()
5384 if (op >= 12) { in disas_neon_data_insn()
5464 if (op == 36 && q == 0) { in disas_neon_data_insn()
5539 if (op == 30 || op == 31 || op >= 58) { in disas_neon_data_insn()
5546 switch (op) { in disas_neon_data_insn()
5610 if (op == 19) in disas_neon_data_insn()
5622 if (op == 20) in disas_neon_data_insn()
5654 if (op == 27) in disas_neon_data_insn()
5661 if (op == 28) in disas_neon_data_insn()
5717 if (op == 30 || op == 31 || op >= 58) { in disas_neon_data_insn()
7295 thumb2_logic_op(int op) in thumb2_logic_op() argument
7297 return (op < 8); in thumb2_logic_op()
7307 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1) in gen_thumb2_data_op() argument
7312 switch (op) { in gen_thumb2_data_op()
7386 int op; in disas_thumb2_insn() local
7527 op = (insn >> 4) & 0x3; in disas_thumb2_insn()
7528 if (op == 2) { in disas_thumb2_insn()
7534 gen_load_exclusive(s, rs, rd, addr, op); in disas_thumb2_insn()
7536 gen_store_exclusive(s, rm, rs, rd, addr, op); in disas_thumb2_insn()
7569 op = (insn & 0x1f); in disas_thumb2_insn()
7571 tmp = tcg_const_i32(op); in disas_thumb2_insn()
7589 tmp = tcg_const_i32(op); in disas_thumb2_insn()
7644 op = (insn >> 21) & 0xf; in disas_thumb2_insn()
7645 if (op == 6) { in disas_thumb2_insn()
7680 logic_cc = (conds && thumb2_logic_op(op)); in disas_thumb2_insn()
7682 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2)) in disas_thumb2_insn()
7693 op = ((insn >> 22) & 6) | ((insn >> 7) & 1); in disas_thumb2_insn()
7694 if (op < 4 && (insn & 0xf000) != 0xf000) in disas_thumb2_insn()
7696 switch (op) { in disas_thumb2_insn()
7702 op = (insn >> 21) & 3; in disas_thumb2_insn()
7704 gen_arm_shift_reg(tmp, op, tmp2, logic_cc); in disas_thumb2_insn()
7716 op = (insn >> 20) & 7; in disas_thumb2_insn()
7717 switch (op) { in disas_thumb2_insn()
7728 if ((op >> 1) == 1) { in disas_thumb2_insn()
7738 op = (insn >> 20) & 7; in disas_thumb2_insn()
7740 if ((op & 3) == 3 || (shift & 3) == 3) in disas_thumb2_insn()
7744 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); in disas_thumb2_insn()
7749 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); in disas_thumb2_insn()
7750 if (op < 4) { in disas_thumb2_insn()
7754 if (op & 1) in disas_thumb2_insn()
7756 if (op & 2) in disas_thumb2_insn()
7763 switch (op) { in disas_thumb2_insn()
7794 op = (insn >> 4) & 0xf; in disas_thumb2_insn()
7803 if (op) in disas_thumb2_insn()
7811 gen_mulxy(tmp, tmp2, op & 2, op & 1); in disas_thumb2_insn()
7821 if (op) in disas_thumb2_insn()
7839 if (op) in disas_thumb2_insn()
7886 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); in disas_thumb2_insn()
7889 if ((op & 0x50) == 0x10) { in disas_thumb2_insn()
7893 if (op & 0x20) in disas_thumb2_insn()
7899 } else if ((op & 0xe) == 0xc) { in disas_thumb2_insn()
7901 if (op & 1) in disas_thumb2_insn()
7904 if (op & 0x10) { in disas_thumb2_insn()
7918 if (op & 0x20) { in disas_thumb2_insn()
7922 if (op & 8) { in disas_thumb2_insn()
7924 gen_mulxy(tmp, tmp2, op & 2, op & 1); in disas_thumb2_insn()
7934 if (op & 4) { in disas_thumb2_insn()
7938 } else if (op & 0x40) { in disas_thumb2_insn()
8000 op = (insn >> 20) & 7; in disas_thumb2_insn()
8001 switch (op) { in disas_thumb2_insn()
8018 msr_mask(env, s, (insn >> 8) & 0xf, op == 1), in disas_thumb2_insn()
8019 op == 1, tmp)) in disas_thumb2_insn()
8051 op = (insn >> 4) & 0xf; in disas_thumb2_insn()
8052 switch (op) { in disas_thumb2_insn()
8103 op = (insn >> 22) & 0xf; in disas_thumb2_insn()
8106 gen_test_cc(op ^ 1, s->condlabel); in disas_thumb2_insn()
8130 op = (insn >> 21) & 7; in disas_thumb2_insn()
8139 switch (op) { in disas_thumb2_insn()
8168 if (op & 1) in disas_thumb2_insn()
8174 if (op & 4) { in disas_thumb2_insn()
8176 if ((op & 1) && shift == 0) in disas_thumb2_insn()
8182 if ((op & 1) && shift == 0) in disas_thumb2_insn()
8263 op = (insn >> 21) & 0xf; in disas_thumb2_insn()
8264 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0, in disas_thumb2_insn()
8305 op = (insn >> 8) & 7; in disas_thumb2_insn()
8307 switch (op) { in disas_thumb2_insn()
8344 op = ((insn >> 21) & 3) | ((insn >> 22) & 4); in disas_thumb2_insn()
8347 if (rs == 15 && op != 2) { in disas_thumb2_insn()
8348 if (op & 2) in disas_thumb2_insn()
8352 switch (op) { in disas_thumb2_insn()
8371 switch (op) { in disas_thumb2_insn()
8397 uint32_t val, insn, op, rm, rn, rd, shift, cond; in disas_thumb_insn() local
8420 op = (insn >> 11) & 3; in disas_thumb_insn()
8421 if (op == 3) { in disas_thumb_insn()
8452 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0); in disas_thumb_insn()
8460 op = (insn >> 11) & 3; in disas_thumb_insn()
8462 if (op == 0) { /* mov */ in disas_thumb_insn()
8472 switch (op) { in disas_thumb_insn()
8514 op = (insn >> 8) & 3; in disas_thumb_insn()
8515 switch (op) { in disas_thumb_insn()
8551 op = (insn >> 6) & 0xf; in disas_thumb_insn()
8552 if (op == 2 || op == 3 || op == 4 || op == 7) { in disas_thumb_insn()
8562 if (op == 9) { /* neg */ in disas_thumb_insn()
8565 } else if (op != 0xf) { /* mvn doesn't read its first operand */ in disas_thumb_insn()
8572 switch (op) { in disas_thumb_insn()
8673 if (op != 0xf) in disas_thumb_insn()
8690 op = (insn >> 9) & 7; in disas_thumb_insn()
8696 if (op < 3) /* store */ in disas_thumb_insn()
8699 switch (op) { in disas_thumb_insn()
8725 if (op >= 3) /* load */ in disas_thumb_insn()
8827 op = (insn >> 8) & 0xf; in disas_thumb_insn()
8828 switch (op) { in disas_thumb_insn()