Lines Matching refs:state

19     uint32_t state;  member
112 if ((s->chan[ch].state & DCSR_STOPIRQEN) && in pxa2xx_dma_update()
113 (s->chan[ch].state & DCSR_STOPINTR)) in pxa2xx_dma_update()
118 if ((s->chan[ch].state & DCSR_EORIRQEN) && in pxa2xx_dma_update()
119 (s->chan[ch].state & DCSR_EORINT)) in pxa2xx_dma_update()
124 if ((s->chan[ch].state & DCSR_RASIRQEN) && in pxa2xx_dma_update()
125 (s->chan[ch].state & DCSR_RASINTR)) in pxa2xx_dma_update()
130 if (s->chan[ch].state & DCSR_STARTINTR) in pxa2xx_dma_update()
135 if (s->chan[ch].state & DCSR_ENDINTR) in pxa2xx_dma_update()
152 if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST)) in pxa2xx_dma_descriptor_fetch()
170 s->chan[ch].state |= DCSR_STARTINTR; in pxa2xx_dma_descriptor_fetch()
190 while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) { in pxa2xx_dma_run()
219 ch->state |= DCSR_EORINT; in pxa2xx_dma_run()
220 if (ch->state & DCSR_EORSTOPEN) in pxa2xx_dma_run()
221 ch->state |= DCSR_STOPINTR; in pxa2xx_dma_run()
222 if ((ch->state & DCSR_EORJMPEN) && in pxa2xx_dma_run()
223 !(ch->state & DCSR_NODESCFETCH)) in pxa2xx_dma_run()
234 ch->state |= DCSR_ENDINTR; in pxa2xx_dma_run()
236 if ((ch->state & DCSR_NODESCFETCH) || in pxa2xx_dma_run()
238 (ch->state & DCSR_EORSTOPEN)) { in pxa2xx_dma_run()
239 ch->state |= DCSR_STOPINTR; in pxa2xx_dma_run()
240 ch->state &= ~DCSR_RUN; in pxa2xx_dma_run()
245 ch->state |= DCSR_STOPINTR; in pxa2xx_dma_run()
276 return s->chan[channel].state | DCSR_REQPEND; in pxa2xx_dma_read()
277 return s->chan[channel].state; in pxa2xx_dma_read()
337 s->chan[channel].state &= 0x0000071f & ~(value & in pxa2xx_dma_write()
340 s->chan[channel].state |= value & 0xfc800000; in pxa2xx_dma_write()
342 if (s->chan[channel].state & DCSR_STOPIRQEN) in pxa2xx_dma_write()
343 s->chan[channel].state &= ~DCSR_STOPINTR; in pxa2xx_dma_write()
348 s->chan[channel].state &= ~DCSR_STOPINTR; in pxa2xx_dma_write()
354 s->chan[channel].state &= ~DCSR_STOPINTR; in pxa2xx_dma_write()
362 s->chan[channel].state |= DCSR_STOPINTR; in pxa2xx_dma_write()
365 s->chan[channel].state &= ~DCSR_CMPST; in pxa2xx_dma_write()
367 s->chan[channel].state |= DCSR_CMPST; in pxa2xx_dma_write()
452 qemu_put_be32s(f, &s->chan[i].state); in pxa2xx_dma_save()
479 qemu_get_be32s(f, &s->chan[i].state); in pxa2xx_dma_load()
502 s->chan[i].state = DCSR_STOPINTR; in pxa2xx_dma_init()
538 s->chan[ch].state |= DCSR_RASINTR; in pxa2xx_dma_request()
540 s->chan[ch].state &= ~DCSR_RASINTR; in pxa2xx_dma_request()
542 s->chan[ch].state |= DCSR_EORINT; in pxa2xx_dma_request()